TLF35584QKVS2

OPTIREG™ PMIC TLF35584 Functional Safety PMIC Features • • • • • • • • • • • • • • High efficient power management integrated circuit (PMIC) Serial step up and step down pre regulator for wide input voltage range from 3.0 to 40 V with full performance and low over all power loss Low drop post regulator 5.0 V/200 mA for communication supply (QCO) Low drop post regulator 5.0 V/600 mA (TLF35584QxVS1) or 3.3 V/600 mA (TLF35584QxVS2) for µC supply (QUC) Voltage reference 5.0 V ±1% for ADC supply, 150 mA current capability (QVR) Two trackers for sensor supply following voltage reference 150 mA current capability each (QT1 and QT2) Standby regulator 5.0 V/10 mA (TLF35584QxVS1) or 3.3 V/10 mA (TLF35584QxVS2) (QST) Provides enable, sync out signal and voltage monitoring for an optional external post regulator for core supply Independent voltage monitoring block and error pin monitoring Configurable window and functional watchdog Safe State Control with two safe state signals with programmable delay 16-bit SPI, interrupt and reset function PRO-SIL™ Features: - ISO 26262 compliant supporting up to ASIL-D - Safety Documentation (Safety Manual & Safety Analysis Summary Report) Green Product (RoHS compliant) Potential applications • • • • • • Electric Power Steering Battery Management Inverter Transmission Engine Management Domain Control Product validation Qualified for Automotive Applications. Product validation according to AEC-Q100/101. Device Overview Please read the Important Notice and Warnings at the end of this document www.infineon.com/OPTIREG-PMIC Rev 1.0 2019-03-25 OPTIREG™ PMIC TLF35584 Functional Safety PMIC Description Description The OPTIREG™ PMIC TLF35584 is a high efficient Functional Safety PMIC (Power Management Integrated Circuit). Type Package TLF35584QVVS1 (5.0 V Variant) PG-VQFN-48 TLF35584QVVS2 (3.3 V Variant) PG-VQFN-48 TLF35584QKVS1 (5.0 V Variant) PG-LQFP-64 TLF35584QKVS2 (3.3 V Variant) PG-LQFP-64 Application Example LDO_Stby 3.3V (5.0V) (as LDO_µC) VST QST ENA ENABLE (KL 15) FRE ENABLE WAK WAKE/INH 3.3V/5.0V V_STBY WakeUp Timer Logic Set fSTEPDOWN high/low by FRE: open/GND STU Set STEPUP usage yes/no by STU: open/GND Comparator VS2 V_Bat (KL30) (PG-LQFP-64 only) VS1 Internal Supply and Clock Feedback DRG RSH SW1 Step downRegulator Step UpRegulator BSG RSL (PG-LQFP-64 only) PG1 PG2 Feedback Bandgap 1 for Regulators FB1 FB2 FB3 (PG-LQFP-64 only) FB4 (PG-LQFP-64 only) V_LDO_µC Bandgap 2 for Voltage Mon. Reset Output INTERRUPT µC SPI INT CHIP SELECT SCS CLOCK SCL DATA_IN SDI DATA_OUT WDI Safe State 1 Safe State 2 QUC LDO_µC 3.3V (5.0V) Tracker 1 5.0V Tracker 2 5.0V Functional Watchdog Volt_Ref. 5.0V ERR SS1 SS2 Error Monitoring Safe State Control TLF35584 Driver Driver 3.3V (5V) Note: • • Feedback Set ext SMPR yes/no by SEC: open/GND 3.3V/5.0V V_LDO_µC For µC supply QCO 5.0V V_LDO_Com For communication supply (CAN/FlexRay) QT1 5.0V V_TR1 For sensor supply SQT1 (PG-LQFP-64 only) QT2 5.0V V_TR2 For sensor supply SQT2 (PG-LQFP-64 only) QVR 5.0V V_Volt_Ref MPS AG4 (PG-LQFP-64 only) GST AGS2 AGS1 AG3 AG2 AG1 (signal delayed) V_LDO_µC Sync Enable SQUC (PG-LQFP-64 only) LDO_Com 5.0V SPI Series Protection resistors /ErrorPin V_Core For µC core supply VCI INTERRUPT Generator Window Watchdog Enable ext.Core sup SEC SDO Trigger SMU EVC External switchmode post regulator (optional) Sync_Out SYN Voltage Monitoring/ Reset Function ROT Reset Control V_PREREG SW2 e.g. 1.3V V_Core The following information is given as an example for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. Please contact us for additional supportive documentation. For further information you may contact http://www.infineon.com/OPTIREG-PMIC Note: This figure is a very simplyfied example on an application circuit. The function must be verified in the real application. Device Overview 2 Rev 1.0 2019-03-25 OPTIREG™ PMIC TLF35584 Functional Safety PMIC 1 Absolute maximum ratings 1 Absolute maximum ratings Table 1 Absolute maximum ratings2) Tj = -40°C to 150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Typ. Unit Note or condition Max. Voltages Boost driver ground VBSG -0.3 – 0.3 V – Input standby LDO VVST -0.3 – 40 V 3)4) Input voltage pin 1 (pre regulator) VVS1 -0.3 – 40 V – Input voltage pin 2 (pre regulator) VVS2 -0.3 – 40 V PG-LQFP-64 only External step up power stage, gate VDRG -0.3 – 40 V – External power stage, sense resistor high VRSH -0.3 – 40 V – External power stage, sense resistor low VRSL -0.3 – 6.0 V – Enable input VENA -0.3 – 40 V – Enable input IENA -5 – – mA 5) Wake input VWAK -0.3 – 40 V – Wake input IWAK -5 – – mA – Reset output VROT -0.3 – 6.0 V – SPI chip select input VSCS -0.3 – 6.0 V – SPI clock input VSCL -0.3 – 6.0 V – SPI data in (MOSI) input VSDI -0.3 – 6.0 V – SPI data out (MISO output) VSDO -0.3 – 6.0 V – Interrupt output VINT -0.3 – 6.0 V – Window watchdog trigger input VWDI -0.3 – 6.0 V – Error pin input VERR -0.3 – 6.0 V – Safe state 1 output VSS1 -0.3 – 6.0 V – Safe state 2 output VSS2 -0.3 – 6.0 V – Output voltage reference LDO VQVR -0.3 – 6.0 V – Output tracker 2 VQT2 -1.0 – 40 V – 2 3 4 5 Not subject to production test, specified by design. Maximum rating is 60 V, if rise time from 0 to 60 V is longer than 10 ms Maximum rating is 49 V, for an overall time of 10 s (in the range of 40 V to 49 V) during the lifetime of the product independent from the rise time. Consider external series resistor for negative voltages < -0.3 V to ensure maximum rating of current Device Overview 3 Rev 1.0 2019-03-25 OPTIREG™ PMIC TLF35584 Functional Safety PMIC 1 Absolute maximum ratings Table 1 Absolute maximum ratings2) (continued) Tj = -40°C to 150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Typ. Unit Note or condition Max. Sense Pin for tracker 2 VSQT2 -0.3 – 40 V PG-LQFP-64 only Output tracker 1 VQT1 -1.0 – 40 V – Sense Pin for tracker 1 VSQT1 -0.3 – 40 V PG-LQFP-64 only Output communication LDO VQCO -0.3 – 6.0 V – Output microcontroller LDO VQUC -0.3 – 6.0 V – Sense Pin for microcontroller LDO VSQUC -0.3 – 6.0 V PG-LQFP-64 only External core voltage monitor input VVCI -0.3 – 6.0 V – HW config: ext. core voltage monitor VSEC -0.3 – 6.0 V – Synchronization output VSYN -0.3 – 6.0 V – Enable output for ext. core supply VEVC -0.3 – 6.0 V – Step down feedback input 4 VFB4 -0.3 – 7.0 V PG-LQFP-64 only Step down feedback input 3 VFB3 -0.3 – 7.0 V PG-LQFP-64 only Step down feedback input 2 VFB2 -0.3 – 7.0 V – Step down feedback input 1 VFB1 -0.3 – 7.0 V – Step down power ground 2 VPG2 -0.3 – 0.3 V – Step down power ground 1 VPG1 -0.3 – 0.3 V – Step down switching node 2 VSW2 -0.3 – 40 V PG-LQFP-64 only Step down switching node 1 VSW1 -0.3 – 40 V – HW config: step up pre regulator VSTU -0.3 – 6.0 V – HW config: step down frequency VFRE -0.3 – 6.0 V – Output standby LDO VQST -0.3 – 6.0 V – Input MPS VMPS -0.3 – 6.0 V – Junction temperature Tj -40 – 150 °C – Storage temperature Tstg -55 – 150 °C – VESD -2 – 2 kV HBM6) Temperatures ESD susceptibility ESD susceptibility to GND 2 6 Not subject to production test, specified by design. ESD susceptibility, HBM according to JEDEC HBM Human Body Model ANSI/ESDA/JEDEC JS001 (1.5 kΩ, 100 pF) Device Overview 4 Rev 1.0 2019-03-25 OPTIREG™ PMIC TLF35584 Functional Safety PMIC 1 Absolute maximum ratings Table 1 Absolute maximum ratings2) (continued) Tj = -40°C to 150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Typ. Unit Note or condition Max. ESD susceptibility to GND VESD -500 – 500 V CDM7) ESD susceptibility (corner pins) to GND VESD,Corner -750 – 750 V CDM 2 7 Not subject to production test, specified by design. ESD susceptibility, Charged Device Model “CDM” ESDA STM5.3.1 or ANSI/ESD S.5.3.1 Device Overview 5 Rev 1.0 2019-03-25 OPTIREG™ PMIC TLF35584 Functional Safety PMIC 2 Package information 8) 8 Dimensions in mm 0.05 MAX. STANDOFF (0.65) (0.2) Package information 8) 2 0. ± 13 0.08 48x COPLANARITY 0.5±0.07 2) 5) .3 .2 6) 36 25 (0 37 24 7±0.1 (6.8) 5.2±0.1 3) 45° 0.1±0.05 (0 1) 05 0. B C SEATING PLANE 7±0.1 (6.8) A 48 13 INDEX MARKING 0.15±0.05 0.4 x 45° 0.9 MAX. 0.5 3) 5.2±0.1 1) VERTICAL BURR 0.03 MAX. AT ALL SIDES 2) THESE FOUR METAL AREAS HAVE EXPOSED DIEPAD POTENTIAL 3) EXCLUDE MOLD RESIDUES ALL DIMENSIONS ARE IN UNITS MM THE DRAWING IS IN COMPLIANCE WITH ISO 128 & PROJECTION METHOD 1 [ 0.23±0.05 48x 0.1 A B C ] 1) 0.2 A-B D H 4x 0.25 GAUGE PLANE EXPOSED DIEPAD Ey By 64 64 1 INDEX MARKING 0°..7° +0.0 BOTTOM VIEW 12 10 B 0.6±0.15 0.08 C 64x COPLANARITY 1) D A H C 0.2 A-B D 64x SEATING PLANE 12 10 Z VIEW 0.15-0.065 1.6 MAX. Z 0.1±0.05 STAND OFF PG-VQFN-48 package outline 1.4±0.05 Figure 1 INDEX MARKING 1 12 0.1±0.03 1 Ax +0.07 0.2-0.03 0.5 0.08 A-B D C 64x Ex AVAIL. EXPOSED DIEPAD SIZE 1) DOES NOT INCLUDE PLASTIC OR METAL PROTRUSION OF 0.25 MAX. PER SIDE ALL DIMENSIONS ARE IN UNITS MM THE DRAWING IS IN COMPLIANCE WITH ISO 128 & PROJECTION METHOD 1 [ Figure 2 8 ] Ex Ey Ax 6.3 6.3 5.3 6.0 6.0 5.0 4.5 4.5 3.5 By 5.3 5.0 3.5 PG-LQFP-64 package outline Dimensions in mm Device Overview 6 Rev 1.0 2019-03-25 Trademarks All referenced product or service names and trademarks are the property of their respective owners. Edition 2019-03-25 Published by Infineon Technologies AG 81726 Munich, Germany © 2019 Infineon Technologies AG All Rights Reserved. Do you have a question about any aspect of this document? Email: erratum@infineon.com Document reference IFX-jmv1546509847065 IMPORTANT NOTICE The information contained in this application note is given as a hint for the implementation of the product only and shall in no event be regarded as a description or warranty of a certain functionality, condition or quality of the product. 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