TLI49611LHALA1

Bipolar Hall Latch Hall Effect Latch for Industrial Applications Product description Overview Characteristic Supply Voltage Supply Current Sensitivity Interface Temperature Bipolar Hall Effect Latch 3.0 V ~ 32 V 1.6 mA BOP: 2 mT BRP: -2 mT Open Drain Output -40°C to 125°C Figure 1 TLI4961-1M in the PG-SOT23-3-15 (left hand) and TLI4961-1L in the PG-SSO-3-2 (right hand) package Features • • • • • • • • • • • • 3.0 V to 32 V operating supply voltage Operation from unregulated power supply Reverse polarity protection (-18 V) Overvoltage capability up to 42 V without external resistor Output overcurrent and overtemperature protection Active error compensation High stability of magnetic thresholds Low jitter (typ. 0.35 μs) High ESD performance Leaded, non halogen-free package PG-SSO-3-2 (TLI4961-1L) Small, halogen-free SMD package PG-SOT23-3-15 (TLI4961-1M) For industrial and consumer applications, not qualified for automotive applications For automotive applications please refer to the Infineon TLE Hall Switches/Latches series Table 1 Ordering information Product name Product type Ordering code Package TLI4961-1L Bipolar Hall Latch SP001052198 PG-SSO-3-2 TLI4961-1M Bipolar Hall Latch SP001031008 PG-SOT23-3-15 Datasheet www.infineon.com Please read the Important Notice and Warnings at the end of this document Rev. 1.3 2021-05-03 Bipolar Hall Latch Hall Effect Latch for Industrial Applications Product description Target applications Target applications for the TLI496x Hall Latch family are all applications which require a high precision Hall Latch with an operating temperature range from -40°C to 125°C. Its superior supply voltage range from 3.0 V to 32 V with overvoltage capability up to 42 V without external resistor makes it ideally suited for industrial applications. The magnetic behavior as a latch and switching thresholds of typical ±2 mT make the device especially suited for the use with a pole wheel for index counting applications and for rotor position detection as in brushless DC motor commutation. Datasheet 2 Rev. 1.3 2021-05-03 Bipolar Hall Latch Hall Effect Latch for Industrial Applications Table of contents Table of contents Product description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Target applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1 1.1 1.2 1.3 1.4 1.5 1.6 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Pin configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Functional block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Default start-up behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 2.1 2.2 2.3 2.4 Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Electrical and magnetic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Package outline PG-SOT23-3-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Packing information PG-SOT23-3-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Package outline PG-SSO-3-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Footprint PG-SOT23-3-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 PG-SOT23-3-15 distance between chip and package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 PG-SSO-3-2 distance between chip and package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Package marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Datasheet 3 Rev. 1.3 2021-05-03 Bipolar Hall Latch Hall Effect Latch for Industrial Applications 1 Functional description 1 Functional description 1.1 General The TLI4961-1L/1M is an integrated Hall effect designed specifically for highly accurate applications with superior supply voltage capability and temperature stability of the magnetic thresholds. 1.2 Pin configuration (top view) Center of Sensitive Area 2.08± 0.1 3 1.35± 0.1 0.65± 0.1 1 2 1.45± 0.1 1 2 3 PG-SSO-3-2 SOT23 Figure 2 Pin configuration and center of sensitive area 1.3 Pin description Table 2 Pin description PG-SOT23-3-15 Pin no. Symbol Function 1 VDD Supply voltage 2 Q Output 3 GND Ground Table 3 Pin description PG-SSO-3-2 Pin No. Symbol Function 1 VDD Supply voltage 2 GND Ground 3 Q Output Datasheet 4 Rev. 1.3 2021-05-03 Bipolar Hall Latch Hall Effect Latch for Industrial Applications 1 Functional description 1.4 Block diagram VDD Voltage Regulator To All Subcircuits Oscillator and Sequencer Bias and Compensation Circuits Spinning Hall Probe Amplifier Demodulator Chopper Multiplexer Reference Q Control Low Pass Filter Comparator with Hysteresis Overtemperature & overcurrent protection GND Figure 3 Datasheet Functional block diagram TLI4961-1L/1M 5 Rev. 1.3 2021-05-03 Bipolar Hall Latch Hall Effect Latch for Industrial Applications 1 Functional description 1.5 Functional block description The chopped Hall IC switch comprises a Hall probe, bias generator, compensation circuits, oscillator and output transistor. The bias generator provides currents for the Hall probe and the active circuits. Compensation circuits stabilize the temperature behavior and reduce influence of technology variations. The active error compensation (chopping technique) rejects offsets in the signal path and the influence of mechanical stress to the Hall probe caused by molding and soldering processes and other thermal stress in the package. The chopped measurement principle together with the threshold generator and the comparator ensures highly accurate and temperature stable magnetic thresholds. The output transistor has an integrated overcurrent and overtemperature protection. B OP Applied Magnetic Field BR P td td tf tr VQ 90% 10% Figure 4 Timing diagram TLI4961-1L/1M VQ B BRP Figure 5 Datasheet 0 BOP Output signal TLI4961-1L/1M 6 Rev. 1.3 2021-05-03 Bipolar Hall Latch Hall Effect Latch for Industrial Applications 1 Functional description 1.6 Default start-up behavior The magnetic thresholds exhibit a hysteresis BHYS = BOP - BRP. In case of a power-on with a magnetic field B within hysteresis (BOP > B > BRP) the output of the sensor is set to the pull up voltage level (VQ) per default. After the first crossing of BOP or BRP of the magnetic field the internal decision logic is set to the corresponding magnetic input value. VDDA is the internal supply voltage which is following the external supply voltage VDD. This means for B > BOP the output is switching, for B < BRP and BOP > B > BRP the output stays at VQ. V DDA tPon 3V The device always applies VQ level at start -up Power on ramp VQ t independent from the applied magnetic field ! Magnetic field above threshold B > BOP t VQ Magnetic field below threshold B < BRP t VQ Magnetic field in hysteresis BOP > B > BRP t Figure 6 Datasheet Start-up behavior of the TLI4961-1L/1M 7 Rev. 1.3 2021-05-03 Bipolar Hall Latch Hall Effect Latch for Industrial Applications 2 Specification 2 Specification 2.1 Application circuit The following Figure 7 shows one option of an application circuit. As explained above the resistor RS can be left out (see Figure 8). The resistor RQ has to be in a dimension to match the applied VS to keep IQ limited to the operating range of maximum 25 mA. e.g.: VS = 12 V; IQ = 12 V/1200 Ω = 10 mA Vs RS = 100Ω VDD TLI496x CDD = 47nF RQ = 1.2kΩ Q TVS diode e.g. ESD24VS2U GND Figure 7 Note: The TVS diode is only required for ESD robustness >4kV Application circuit 1: with external resistor Vs VDD TLI496x CDD = 47nF RQ = 1.2kΩ Q TVS diode e.g. ESD24VS2U GND Figure 8 Datasheet Note: The TVS diode is only required for ESD robustness >4kV Application circuit 2: without external resistor 8 Rev. 1.3 2021-05-03 Bipolar Hall Latch Hall Effect Latch for Industrial Applications 2 Specification 2.2 Absolute maximum ratings Table 4 Absolute maximum rating parameters Parameter Symbol Values Min. Typ. Unit Note or Test Condition Max. Supply voltage1) VDD -18 – 32 42 V – 10h, no external resistor required Output voltage VQ -0.5 – 32 V – Reverse output current IQ -70 – – mA – Junction temperature1) TJ -40 – 150 °C for 2000h Storage temperature TS -40 – 150 °C – Thermal resistance Junction ambient RthJA – – 300 200 K/W for PGSOT23-3-15 (2s2p) for PG-SSO-3-2 (2s2p) Thermal resistance Junction lead RthJL – – 100 150 K/W for PGSOT23-3-15 for PG-SSO-3-2 1) This lifetime statement is an anticipation based on an extrapolation of Infineon’s qualification test results. The actual lifetime of a component depends on its form of application and type of use etc. and may deviate from such statement. The lifetime statement shall in no event extend the agreed warranty period. Attention: Stresses above the max. values listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. Calculation of the dissipated power PDIS and junction temperature TJ of the chip (SOT23 example): e.g. for: VDD = 12 V, IS = 2.5 mA, VQSAT = 0.5 V, IQ = 20 mA Power dissipation: PDIS = 12 V x 2.5 mA + 0.5 V x 20 mA = 30 mW + 10 mW = 40 mW Temperature ∆T = RthJA x PDIS = 300 K/W x 40 mW = 12 K For TA = 50°C: TJ = TA + ∆T = 50°C + 12 K = 62°C Datasheet 9 Rev. 1.3 2021-05-03 Bipolar Hall Latch Hall Effect Latch for Industrial Applications 2 Specification Table 5 ESD protection1) (TA = 25°C) Parameter Symbol Values Min. Typ. Unit Note or Test Condition Max. ESD voltage (HBM)2) VESD -4 – 4 kV R = 1.5 kΩ, C = 100 pF ESD voltage (CDM)3) VESD -1 – 1 kV – ESD voltage (system level)4) VESD -15 – 15 kV with circuit shown in Figure 7 and Figure 8 1) 2) 3) 4) Characterization of ESD is carried out on a sample basis, not subject to production test. Human Body Model (HBM) tests according to ANSI/ESDA/JEDEC JS-001. Charge device model (CDM) tests according to JESD22-C101. Gun test (2 kΩ / 330 pF or 330 Ω / 150 pF) according to ISO 10605-2008. 2.3 Operating range The following operating conditions must not be exceeded in order to ensure correct operation of the TLI4961-1L/1M. All parameters specified in the following sections refer to these operating conditions unless otherwise mentioned. The maximum tested magnetic field is 600 mT. Table 6 Operating conditions parameters Parameter Symbol Values Min. Typ. Unit Note or Test Condition Max. Supply voltage VDD 3.0 – 321) V – Output voltage VQ -0.3 – 32 V – Junction temperature TJ -40 – 125 °C – Output current IQ 0 – 25 mA – Magnetic signal input frequency2) fSW 0 – 10 kHz – 1) 2) Latch-up test with factor 1.5 is not covered. Please see max ratings also. For operation at the maximum switching frequency the magnetic input signal must be 1.4 times higher than for static fields.This is due to the -3 dB corner frequency of the internal low-pass filter in the signal path. Datasheet 10 Rev. 1.3 2021-05-03 Bipolar Hall Latch Hall Effect Latch for Industrial Applications 2 Specification 2.4 Electrical and magnetic characteristics Product characteristics involve the spread of values guaranteed within the specified voltage and ambient temperature range. Typical characteristics are the median of the production and correspond to VDD = 12 V and TA = 25°C. The below listed specification is valid in combination with the application circuit shown in Figure 7 and Figure 8. Table 7 General electrical characteristics Parameter Symbol Values Min. Typ. Unit Note or Test Condition Max. Supply current IS 1.1 1.6 2.5 mA – Reverse current ISR – 0.05 1 mA for VDD = -18 V Output saturation voltage VQSAT – 0.2 0.5 V IQ = 20 mA – 0.24 0.6 V IQ = 25 mA Output leakage current IQLEAK – – 10 μA – Output current limitation IQLIMIT 30 56 70 mA internally limited and thermal shutdown Output fall time1) tf 0.17 0.4 1 μs 1.2 kΩ / 50 pF, see Figure 4 Output rise time1) tr 0.4 0.5 1 μs 1.2 kΩ / 50 pF, see Figure 4 Output jitter1) 2) tQJ – 0.35 1 μs for square wave signal with 1 kHz Delay time1) 3) td 12 15 30 μs see Figure 4 Power-on time1) 4) tPON – 80 150 μs VDD = 3 V, B ≤ BRP 0.5 mT or B ≥ BOP + 0.5 mT Chopper frequency1) fOSC – 350 kHz – 1) 2) 3) 4) Not subject to production test, verified by design/characterization. Output jitter is the 1 σ value of the output switching distribution. Systematic delay between magnetic threshold reached and output switching. Time from applying VDD = 3.0 V to the sensor until the output is valid. Datasheet 11 Rev. 1.3 2021-05-03 Bipolar Hall Latch Hall Effect Latch for Industrial Applications 2 Specification Table 8 Magnetic characteristics Parameter Symbol T (°C) Values Min. Operating point BOP Release point BRP Hysteresis BHYS Typ. Max. -40 0.6 2.1 3.6 25 0.5 2.0 3.5 125 0.3 1.8 3.2 -40 -3.6 -2.1 -0.6 25 -3.5 -2.0 -0.5 125 -3.2 -1.8 -0.3 -40 2.5 4.2 5.9 25 2.4 4.0 5.6 125 2.1 3.2 5.0 – Effective noise value of the magnetic switching points1) BNeff 25 – 62 Temperature compensation of magnetic thresholds2) TC – – -1200 – 1) 2) Unit Note or Test Condition mT – mT – mT – μT – ppm – /K The magnetic noise is normal distributed and can be assumed as nearly independent to frequency without sampling noise or digital noise effects. The typical value represents the rms-value and corresponds therefore to a 1 σ probability of normal distribution. Consequently a 3 σ value corresponds to 99.7% probability of appearance. Not subject to production test, verified by design/characterization. Field direction definition N S Figure 9 Datasheet N Branded Side S Definition of magnetic field direction PG-SOT23-3-15 (left hand) and PG-SSO-3-2 (right hand) 12 Rev. 1.3 2021-05-03 Bipolar Hall Latch Hall Effect Latch for Industrial Applications 3 Package information 3 Package information The TLI4961-1L/1M is available in the small halogen-free SMD package PG-SOT23-3-15 and the through-hole leaded package PG-SSO-3-2. Package outline PG-SOT23-3-15 0.4 +0.1 -0.05 1) 2 C 0.95 0.08...0.1 5 1.3 ±0.1 1 2.4 ±0.15 3 0.1 MAX. 10° MAX. B 1 ±0.1 10° MAX. 2.9 ±0.1 0.15 MIN. 3.1 A 0...8° 1.9 0.2 0.25 M B C M A 1) Lead width can be 0.6 max. in dambar area Figure 10 PG-SOT23-3-15 package outline (all dimensions in mm) 3.2 Packing information PG-SOT23-3-15 4 0.2 8 2.65 2.13 0.9 Pin 1 3.15 1.15 SOT23-TP V02 Figure 11 Datasheet Packing of the PG-SOT23-3-15 in a tape 13 Rev. 1.3 2021-05-03 Bipolar Hall Latch Hall Effect Latch for Industrial Applications 3 Package information 3.3 Package outline PG-SSO-3-2 0.8 ±0.1 x 45˚±2° 7˚±2° 0.2 2 A 1.52 ±0.05 1 MAX.1) 7˚±2° 0.35 ±0.1 x 45˚±2° 1.9 MAX. 3.29 ±0.08 4.06 ±0.08 3 ±0.06 0.15 MAX 4.16 ±0.05 (0.25) B (0.79) 0.6 MAX. 0.2 +0.04 0.4 ±0.05 3x 0.5 B 1 2 3 2x 1.27 1-1 6 ±0.5 C 18 ±0.5 9 ±0.5 23.8 ±0.5 2C 38 MAX. 12.7 ±1 A Adhesive Tape Tape 6.35 ±0.4 4 ±0.3 0.39 ±0.1 12.7 ±0.3 1) No solder function area Figure 12 Datasheet 0.25 -0.15 Total tolerance at 10 pitches ±1 PG-SSO-3-2 package outline (all dimensions in mm) 14 Rev. 1.3 2021-05-03 Bipolar Hall Latch Hall Effect Latch for Industrial Applications 3 Package information 3.4 Footprint PG-SOT23-3-15 0.8 1.4 min 0.9 1.6 1.3 0.9 1.4 min 0.8 1.2 0.8 1.2 0.8 Reflow Soldering Wave Soldering Figure 13 Footprint PG-SOT23-3-15 3.5 PG-SOT23-3-15 distance between chip and package Figure 14 Distance between chip and package 3.6 PG-SSO-3-2 distance between chip and package Branded Side Figure 15 Datasheet Distance between chip and package 15 Rev. 1.3 2021-05-03 Bipolar Hall Latch Hall Effect Latch for Industrial Applications 3 Package information Package marking I11 Figure 17 Datasheet Year (y) = 0...9 Month (m) = 1...9, o - October n - November d - December Marking of TLI4961-1M Year (y) = 0...9 Calendar Week (ww) = 01...52 I11 yyww Figure 16 ym 3.7 Marking of TLI4961-1L 16 Rev. 1.3 2021-05-03 Bipolar Hall Latch Hall Effect Latch for Industrial Applications Revision history Revision history Revision Date Changes Revision 1.3 2021-05-03 Error correction of product name from TLI4964-1L/1M to TLI4961-1M Revision 1.2 2019-12-20 • • • • • Revision 1.1 2012-10-15 Added TLI4961-1L with PG-SSO-3-2 package Revision 1.0 Datasheet Updated text and figure in Chapter 2.6 Updated standards in Table 5 Added maximum tested magnetic field in Chapter 3.3 Updated Figure 15 Editorial changes Initial release 17 Rev. 1.3 2021-05-03 Trademarks All referenced product or service names and trademarks are the property of their respective owners. Edition 2021-05-03 Published by Infineon Technologies AG 81726 Munich, Germany © 2021 Infineon Technologies AG All Rights Reserved. Do you have a question about any aspect of this document? Email: erratum@infineon.com Document reference IFX-nnt1620014101071 IMPORTANT NOTICE The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics (“Beschaffenheitsgarantie”). With respect to any examples, hints or any typical values stated herein and/or any information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. In addition, any information given in this document is subject to customer’s compliance with its obligations stated in this document and any applicable legal requirements, norms and standards concerning customer’s products and any use of the product of Infineon Technologies in customer’s applications. The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of customer’s technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this document with respect to such application. WARNINGS Due to technical requirements products may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies office. Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized representatives of Infineon Technologies, Infineon Technologies’ products may not be used in any applications where a failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury.