Ultra Low Quiescent Current Linear
Voltage Regulator
TLS810C1
TLS810C1EJV33
Linear Voltage Regulator
Data Sheet
Rev. 1.1, 2015-11-02
Automotive Power
TLS810C1
1
TLS810C1EJV33
Overview
Features
•
Ultra Low Quiescent Current of 8.5 µA
•
Wide Input Voltage Range of 2.75 V to 42 V
•
Output Current Capacity up to 100 mA
•
Low Drop Out Voltage of typ. 250 mV @ 100 mA
•
Output Current Limit Protection
•
Overtemperature Shutdown
•
Reset
•
Available in PG-DSO-8 EP Package
•
Wide Temperature Range
•
Green Product (RoHS Compliant)
•
AEC Qualified
Figure 1
PG-DSO-8 EP
Type
Package
Marking
TLS810C1EJV33
PG-DSO-8 EP
810C1V33
Data Sheet
2
Rev. 1.1, 2015-11-02
TLS810C1EJV33
Overview
Description
The TLS810C1 is a linear voltage regulator featuring wide input voltage range, low drop out voltage and ultra
low quiescent current.
With an input voltage range of 2.75 V to 42 V and ultra low quiescent of only 8.5 µA, the regulator is perfectly
suitable for automotive or any other supply systems connected permanently to the battery.
The TLS810C1EJV33 is the fixed 3.3 V output version with an accuracy of 2 % and output current capability up
to 100 mA.
The new regulation concept implemented in TLS810C1 combines fast regulation and very good stability while
requiring only a small ceramic capacitor of 1 μF at the output.
The tracking region starts already at input voltages of 2.75 V (extended operating range). This makes the
TLS810C1 also suitable to supply automotive systems that need to operate during cranking condition.
Internal protection features like output current limitation and overtemperature shutdown are implemented
to protect the device against immediate damage due to failures like output short circuit to GND, over-current
and over-temperature.
The output voltage is supervised by the Reset feature, including undervoltage reset and delayed reset release
at power-on.
Choosing External Components
An input capacitor CI is recommended to compensate line influences. The output capacitor CQ is necessary for
the stability of the regulating circuit. Stability is guaranteed at values CQ≥ 1 µF and an ESR ≤ 100 Ω within the
whole operating range.
Data Sheet
3
Rev. 1.1, 2015-11-02
TLS810C1EJV33
Block Diagram
2
Block Diagram
I
Q
Current
Limitation
RO
Reset
Bandgap
Reference
Temperature
Shutdown
GND
Figure 2
Data Sheet
D
Block Diagram TLS810C1
4
Rev. 1.1 2015-11-02
TLS810C1EJV33
Pin Configuration
3
Pin Configuration
3.1
Pin Assignment in PG-DSO-8 EP Package
I
1
8
Q
N.C.
2
7
N.C.
N.C.
3
6
RO
GND
4
5
D
Figure 3
Pin Configuration TLS810C1 in PG-DSO-8 EP package
3.2
Pin Definitions and Functions in PG-DSO-8 EP Package
Pin
Symbol
Function
1
I
Input
It is recommended to place a small ceramic capacitor (e.g. 100 nF) to GND, close
to the IC terminals, in order to compensate line influences.
2
N.C.
Not connected
3
N.C.
Not connected
4
GND
Ground
5
D
Reset Delay Timing
Connect a ceramic capacitor to GND for adjusting the reset delay time.
Leave open if the reset function is not needed.
6
RO
Reset Output
Integrated pull-up resistor.
Open collector output.
Leave open if the reset function is not needed.
7
N.C.
Not connected
Data Sheet
5
Rev. 1.1 2015-11-02
TLS810C1EJV33
Pin Configuration
Pin
Symbol
Function
8
Q
Output
Connect an output capacitor CQ to GND close to the IC’s terminals, respecting the
values specified for its capacitance and ESR in Table 2 “Functional Range” on
Page 8.
Pad
–
Exposed Pad
Connect to heatsink area.
Connect to GND.
Data Sheet
6
Rev. 1.1 2015-11-02
TLS810C1EJV33
General Product Characteristics
4
General Product Characteristics
4.1
Absolute Maximum Ratings
Table 1
Absolute Maximum Ratings1)
Tj = -40 °C to +150 °C; all voltages with respect to ground (unless otherwise specified)
Parameter
Symbol
Values
Unit
Note or
Test Condition
Number
Min.
Typ.
Max.
VI
-0.3
–
45
V
–
P_4.1.1
VQ
-0.3
–
7
V
–
P_4.1.2
VRO, VD
-0.3
–
7
V
–
P_4.1.3
Junction Temperature
Tj
-40
–
150
°C
–
P_4.1.4
Storage Temperature
Tstg
-55
–
150
°C
–
P_4.1.5
VESD,HBM
-2
–
2
kV
HBM2)
Voltage Input I
Voltage
Voltage Output Q
Voltage
Reset Output RO, Reset Delay D
Voltage
Temperatures
ESD Absorption
ESD Susceptibility to GND
ESD Susceptibility to GND
VESD,CDM
-750
–
750
V
P_4.1.6
3)
CDM at all pins P_4.1.7
1) Not subject to production testing, specified by design.
2) ESD susceptibility, HBM according to ANSI/ESDA/JEDEC JS001 (1.5 kΩ, 100 pF)
3) ESD susceptibility, Charged Device Model “CDM” according JEDEC JESD22-C101
Notes
1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are
not designed for continuous repetitive operation.
Data Sheet
7
Rev. 1.1 2015-11-02
TLS810C1EJV33
General Product Characteristics
4.2
Functional Range
Table 2
Functional Range
Parameter
Symbol
Values
Min.
Input Voltage Range
VI
Typ.
VQ,nom+Vdr –
Unit
Note or
Number
Test Condition
V
–1)
P_4.2.1
2)
P_4.2.2
Max.
42
Extended Input Voltage Range VI,ext
2.75
–
42
V
–
Output Capacitor
1
–
–
µF
–3)4)
P_4.2.3
4)
P_4.2.4
CQ
Output Capacitor’s ESR
ESR(CQ) –
–
100
Ω
–
Junction temperature
Tj
–
150
°C
–
1)
2)
3)
4)
-40
P_4.2.5
Output current is limited internally and depends on the input voltage, see Electrical Characteristics for more details.
When VI is between VI,ext.min and VQ,nom + Vdr, VQ = VI - Vdr. When VI is below VI,ext,min, VQ can drop down to 0 V.
The minimum output capacitance requirement is applicable for a worst case capacitance tolerance of 30%.
Not subject to production testing, specified by design.
Note: Within the functional or operating range, the IC operates as described in the circuit description. The
electrical characteristics are specified within the conditions given in the Electrical Characteristics table.
Data Sheet
8
Rev. 1.1 2015-11-02
TLS810C1EJV33
General Product Characteristics
4.3
Thermal Resistance
Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go
to www.jedec.org.
Table 3
Thermal Resistance TLS810C1 in PG-DSO-8 EP Package
Parameter
Symbol
Values
Min.
Typ.
Max.
–
19
–
Unit
Note or
Test Condition
Number
K/W
–
P_4.3.1
Package Version
Junction to Case1)
RthJC
2)
Junction to Ambient
RthJA
–
51
–
K/W
2s2p board
P_4.3.2
Junction to Ambient
RthJA
–
167
–
K/W
1s0p board, footprint
only3)
P_4.3.3
Junction to Ambient
RthJA
–
71
–
K/W
1s0p board, 300 mm2 P_4.3.4
heatsink area on PCB3)
Junction to Ambient
RthJA
–
60
–
K/W
1s0p board, 600 mm2 P_4.3.5
heatsink area on PCB3)
1) Not subject to production test, specified by design
2) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm³ board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm
Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.
3) Specified RthJA value is according to JEDEC JESD 51-3 at natural convection on FR4 1s0p board; The Product
(Chip+Package) was simulated on a 76.2 × 114.3 × 1.5 mm3 board with 1 copper layer (1 x 70µm Cu).
Data Sheet
9
Rev. 1.1 2015-11-02
TLS810C1EJV33
Block Description and Electrical Characteristics
5
Block Description and Electrical Characteristics
5.1
Voltage Regulation
The output voltage VQ is divided by a resistor network. This fractional voltage is compared to an internal
voltage reference and the pass transistor is driven accordingly.
The control loop stability depends on the output capacitor CQ, the load current, the chip temperature and the
internal circuit structure. To ensure stable operation, the output capacitor’s capacitance and its equivalent
series resistor ESR requirements given in “Functional Range” on Page 8 have to be maintained. For details
see the typical performance graph Output Capacitor Series Resistor ESR(CQ) versus Output Current IQ.
Since the output capacitor is used to buffer load steps, it should be sized according to the application’s needs.
An input capacitor CI is not required for stability, but is recommended to compensate line fluctuations. An
additional reverse polarity protection diode and a combination of several capacitors for filtering should be
used, in case the input is connected directly to the battery line. Connect the capacitors close to the regulator
terminals.
In order to prevent overshoots during start-up, a smooth ramping up function is implemented. This ensures
almost no overshoots during start-up, mostly independent from load and output capacitance.
Whenever the load current exceeds the specified limit, e.g. in case of a short circuit, the output current is
limited and the output voltage decreases.
The overtemperature shutdown circuit prevents the IC from immediate destruction under fault conditions
(e.g. output continuously short-circuit) by switching off the power stage. After the chip has cooled down, the
regulator restarts. This oscillatory thermal behaviour causes the junction temperature to exceed the
maximum rating of 150°C and can significantly reduce the IC’s lifetime.
Supply
II
I
Q
IQ
Regulated
Output Voltage
Current
Limitation
C
CI
VI
Bandgap
Reference
Temperature
Shutdown
CQ
ESR
VQ
LOAD
GND
Figure 4
Data Sheet
Block Diagram Voltage Regulation
10
Rev. 1.1 2015-11-02
TLS810C1EJV33
Block Description and Electrical Characteristics
Table 4
Electrical Characteristics
Tj = -40 °C to +150 °C, VI = 13.5 V, all voltages with respect to ground (unless otherwise specified).
Typical values are given at Tj = 25 °C, VI = 13.5 V.
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit Note or Test Condition
Number
Output Voltage Precision
VQ
3.23
3.30
3.37
V
50 µA ≤ IQ ≤ 100 mA,
4 V ≤ VI ≤ 28 V
P_5.1.1
Output Voltage Precision
VQ
3.23
3.30
3.37
V
50 µA ≤ IQ ≤ 50 mA,
4 V ≤ VI ≤ 42 V
P_5.1.2
Output Current Limitation
IQ,lim
110
190
260
mA
0 V ≤ VQ ≤ VQ,nom - 0.1 V
P_5.1.3
Line Regulation
steady-state
ΔVQ,line
–
1
20
mV
IQ = 1 mA, 6 V ≤ VI ≤ 32 V
P_5.1.4
Load Regulation
steady-state
ΔVQ,load
-20
-1
–
mV
VI = 6 V,
50 µA ≤ IQ ≤ 100 mA
P_5.1.5
Dropout Voltage1)
Vdr = VI - VQ
Vdr
–
250
650
mV
IQ = 100 mA
P_5.1.6
Ripple Rejection2)
PSRR
–
60
–
dB
IQ = 50 mA,
fripple = 100 Hz,
Vripple = 0.5 Vp-p
P_5.1.7
Overtemperature
Shutdown Threshold
Tj,sd
151
175
–
°C
Tj increasing
P_5.1.8
Overtemperature
Shutdown Threshold
Hysteresis
Tj,sdh
–
10
–
K
Tj decreasing
P_5.1.9
1) Measured when the output voltage VQ has dropped 100 mV from the nominal value obtained at VI = 13.5V
2) Not subject to production test, specified by design
Data Sheet
11
Rev. 1.1 2015-11-02
TLS810C1EJV33
Block Description and Electrical Characteristics
5.2
Typical Performance Characteristics Voltage Regulation
Typical Performance Characteristics
Output Voltage VQ versus
Junction Temperature Tj
Output Current IQ versus
Input Voltage VI
3.5
300
Tj = −40 °C
Tj = 25 °C
3.45
Tj = 150 °C
250
3.4
200
IQmax [mA]
VQ [V]
3.35
3.3
150
3.25
100
3.2
50
3.15
3.1
VI = 13.5 V
IQ = 50 mA
0
50
Tj [°C]
100
0
150
Dropout Voltage Vdr versus
Junction Temperature Tj
0
Tj = 25 °C
350
Tj = 150 °C
300
300
250
250
Vdr [mV]
Vdr [mV]
40
Tj = −40 °C
IQ = 50 mA
IQ = 100 mA
200
200
150
150
100
100
50
50
Data Sheet
30
400
IQ = 10 mA
0
20
VI [V]
Dropout Voltage Vdr versus
Output Current IQ
400
350
10
0
50
Tj [°C]
100
0
150
0
20
40
60
80
100
IQ [mA]
12
Rev. 1.1 2015-11-02
TLS810C1EJV33
Block Description and Electrical Characteristics
Load Regulation ΔVQ,load versus
Output Current IQ
Load Regulation ΔVQ,line versus
Input Voltage VI
10
10
Tj = −40 °C
8
Tj = 25 °C
Tj = 150 °C
6
4
4
2
2
0
−2
−4
−4
−6
−6
−8
−8
VI = 6 V
0
20
Tj = 150 °C
0
−2
−10
Tj = 25 °C
6
dVline [mV]
dVload [mV]
Tj = −40 °C
8
40
60
80
−10
100
IQ = 1 mA
10
15
20
IQ [mA]
4
80
3.5
70
3
60
2.5
50
2
30
1
20
IQ = 50 mA
Tj = 25 °C
0.5
0
1
2
3
4
10
0
−2
10
5
VI [V]
Data Sheet
35
40
40
1.5
0
30
Power Supply Ripple Rejection PSRR versus
Ripple Frequency fr
PSRR [dB]
VQ [V]
Output Voltage VQ versus
Input Voltage VI
25
VI [V]
IQ = 10 mA
CQ = 1 μF
VI = 13.5 V
Vripple = 0.5 Vpp
Tj = 25 °C
−1
10
0
1
10
10
2
10
3
10
f [kHz]
13
Rev. 1.1 2015-11-02
TLS810C1EJV33
Block Description and Electrical Characteristics
Output Capacitor Series Resistor ESR(CQ) versus
Output Current IQ
3
10
Unstable Region
2
10
ESR(CQ) [Ω]
1
10
Stable Region
0
10
−1
10
CQ = 1 μF
VI = 3...28 V
−2
10
0
20
40
60
80
100
IQ [mA]
Data Sheet
14
Rev. 1.1 2015-11-02
TLS810C1EJV33
Block Description and Electrical Characteristics
5.3
Current Consumption
Table 5
Electrical Characteristics Current Consumption
Tj = -40 °C to +150 °C, VI = 13.5 V (unless otherwise specified).
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit Note or Test Condition
Number
Current Consumption
Iq = II - IQ
Iq
–
8.5
10.5
µA
IQ = 50 µA, Tj = 25 °C
P_5.3.1
Current Consumption
Iq = II - IQ
Iq
–
11
14
µA
IQ = 50 µA, Tj < 105 °C
P_5.3.2
Current Consumption
Iq = II - IQ
Iq
–
11.5
15
µA
IQ = 50 µA, Tj < 125 °C
P_5.3.3
Current Consumption
Iq = II - IQ
Iq
–
11.5
15
µA
IQ= 100 mA, Tj < 125 °C
P_5.3.4
Data Sheet
15
Rev. 1.1 2015-11-02
TLS810C1EJV33
Block Description and Electrical Characteristics
5.4
Typical Performance Characteristics Current Consumption
Typical Performance Characteristics
Current Consumption Iq versus
Output Current IQ
Current Consumption Iq versus
Input Voltage VI
40
24
Tj = −40 °C
Tj = −40 °C
Tj = 25 °C
Tj = 25 °C
35
Tj = 105 °C
Tj = 105 °C
20
Tj = 125 °C
Tj = 125 °C
30
16
Iq [μA]
Iq [μA]
25
12
20
15
8
10
4
5
VI = 13.5 V
0
IQ = 50 μA
0
0
20
40
60
80
100
IQ [mA]
10
15
20
25
VI [V]
30
35
40
Current Consumption Iq versus
Junction Temperature Tj
24
20
Iq [μA]
16
12
8
4
0
Data Sheet
VI = 13.5 V
IQ = 50 μA
0
50
Tj [°C]
100
150
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TLS810C1EJV33
Block Description and Electrical Characteristics
5.5
Reset Function
The reset function provides several features:
Output Undervoltage Reset
An output undervoltage condition is indicated by setting the Reset Output RO to “low”. This signal may be
used to reset a microcontroller during low supply voltage.
Power-On Reset Delay Time
The power-on reset delay time trd allows microcontoller and oscillator to start up. This delay time is the time
frame from exceeding the reset switching threshold VRT until the reset is released by switching the reset output
“RO” from “low” to “high”. The power-on reset delay time trd is defined by an external delay capacitor CD
connected to pin D charged by the delay capacitor charge current ID,ch starting from VD = 0 V.
If the application needs a power-on reset delay time trd different from the value given in Table 6, the delay
capacitor’s value can be derived from the specified value and the desired power-on delay time:
CD =
trd,new
• 100 nF
trd
(5.1)
with
•
CD: capacitance of the delay capacitor to be chosen
•
trd,new: desired power-on reset delay time
•
trd: power-on reset delay time specified in this datasheet
For a precise calculation also take the delay capacitor’s tolerance into consideration.
Reset Reaction Time
The reset reaction rime trr considers the internal reaction time trr,int and the discharge time trr,d defined by the
external delay capacitor CD (see typical performance graph for details). Hence, the total reset reaction time
becomes:
trr = t rr,int + trr,d
(5.2)
with
•
trr: reset reaction time
•
trr,int: internal reset reaction time
•
trr,d: reset discharge
Optional Reset Output Pull-Up Resistor RRO,ext
The Reset Output RO is an open collector output with an integrated pull-up resistor. If needed, an external
pull-up resistor to the output Q can be added. In Table 6 a minimum value for the external resistor RRO,ext is
given.
Data Sheet
17
Rev. 1.1 2015-11-02
TLS810C1EJV33
Block Description and Electrical Characteristics
I
Q
RRO
Int.
Supply
Control
VDD
ID ,ch
RRO ,ext
Reset
IRO
VDST
VRADJ ,th
CQ
RO
optional
Supply
MicroController
ID ,dch
GND
D
GND
CD
Figure 5
Data Sheet
Block Diagram Reset Function
18
Rev. 1.1 2015-11-02
TLS810C1EJV33
Block Description and Electrical Characteristics
VI
t
t < trr,total
VQ
VRT,high
VRT,low
1V
t
trd
VD
VDU
VDRL
t
trd
trr,total
trd
trr,total
trd
trr,total
VRO
VRO,low
1V
t
Thermal
Shutdown
Input
Voltage Dip
Undervoltage
Spike at
output
Over load
TimingDiagram_Res et.vs d
Figure 6
Timing Diagram Reset
Table 6
Electrical Characteristics Reset
Tj = -40 °C to +150 °C, VI = 13.5 V, all voltages with respect to ground (unless otherwise specified).
Typical values are given at Tj = 25 °C, VI = 13.5 V.
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit Note or
Test Condition
Number
Output Undervoltage Reset
Output Undervoltage Reset
Upper Switching Threshold
VRT,high
3.03
3.10
3.17
V
VQ increasing
P_5.5.1
Output Undervoltage Reset
Lower Switching Threshold
VRT,low
2.97
3.03
3.10
V
VQ decreasing
P_5.5.2
Reset Output RO
Data Sheet
19
Rev. 1.1 2015-11-02
TLS810C1EJV33
Block Description and Electrical Characteristics
Table 6
Electrical Characteristics Reset (cont’d)
Tj = -40 °C to +150 °C, VI = 13.5 V, all voltages with respect to ground (unless otherwise specified).
Typical values are given at Tj = 25 °C, VI = 13.5 V.
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit Note or
Test Condition
Number
P_5.5.3
Reset Output Low Voltage
VRO,low
0
0.2
0.4
V
1 V ≤ VQ ≤ VRT;
RRO > 4.7 kΩ
Reset Output
Internal Pull-Up Resistor
RRO,int
13
20
36
kΩ
Internally connected P_5.5.4
to Q
Reset Output External
Pull-up Resistor to VQ
RRO,ext
4.7
–
–
kΩ
1 V ≤ VQ ≤ VRT;
VRO ≤ 0.4 V
P_5.5.5
Power On Reset Delay Time
trd
17
25
37
ms
CD = 100 nF
Calculated vaule
P_5.5.6
Upper Delay Switching
Threshold
VDU
–
0.9
–
V
–
P_5.5.7
Lower Delay Switching
Threshold
VDL
–
0.6
–
V
–
P_5.5.8
Delay Capacitor Charge Current
ID,ch
–
3.6
–
µA
VD = 1 V
P_5.5.9
Delay Capacitor Discharge
Current
ID,dch
–
250
–
mA
VD = 1 V
P_5.5.10
Delay Capacitor Discharge Time trr,d
–
2
4
µs
CD = 100 nF
Calculated value
P_5.5.11
Internal Reset Reaction Time1)
trr,int
–
8
14
µs
CD = 0 nF
P_5.5.12
Reset Reaction Time
trr,total
–
10
18
µs
CD = 100 nF
Calculated value
P_5.5.13
Reset Delay Timing
1) Parameter not subject to production test; specified by design.
Data Sheet
20
Rev. 1.1 2015-11-02
TLS810C1EJV33
Block Description and Electrical Characteristics
5.6
Typical Performance Characteristics Reset
Typical Performance Characteristics
Undervoltage Reset Threshold VRT versus
Junction Temperature Tj
Power On Reset Delay Time trd versus
Junction Temperature Tj
3.3
40
VRT high
VRT low
35
3.2
30
3.15
25
trd [ms]
VRT [V]
3.25
3.1
20
3.05
15
3
10
2.95
5
CD = 100 nF
2.9
0
50
Tj [°C]
100
0
150
0
50
Tj [°C]
100
150
Internal Reset Reaction Time trr,int versus
Junction Temperature Tj
16
14
12
trr,int [μs]
10
8
6
4
2
0
Data Sheet
0
50
Tj [°C]
100
150
21
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TLS810C1EJV33
Application Information
6
Application Information
Note: The following information is given as a hint for the implementation of the device only and shall not be
regarded as a description or warranty of a certain functionality, condition or quality of the device.
6.1
Application Diagram
Supply DI1
Regulated
Q
I
IQ Output Voltage
(optional)
II
TLS810C1
DI2
工商网监
湘ICP备2023018690号
