XDPL8210
XDPL8210 Digital Flyback Controller IC
XDP™ Digital Power
Datasheet
Revision 1.1
Features
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Single stage flyback controller with Power Factor Correction (PFC)
Primary side regulated Constant Current (CC) output with high precision
Supports universal AC input (90 Vrms to 305 Vrms)
Supports wide LED load voltage range (up to 4 times of the minimum LED load voltage)
Excellent line and load regulation (typical within +/- 2%)
High power quality (Typical Power Factor (PF) up to 0.99 and Total Harmonic Distortion (THD) < 10%)
High efficiency with Quasi-Resonant Mode, switching in first valley (QRM1) at high output power and
frequency controlled Discontinuous Conduction Mode (DCM) at medium output power
Dim-to-off operation (with typical standby power as low as 60 mW)
Dedicated PWM input pin for dimming control by either a micro-controller or a transformer-less IEC60929compliant isolated 0 - 10 V dimming circuit (based on CDM10VD)
Dimming down to 1%
Limited Power (LP) mode
Input overvoltage and undervoltage (Brown-in/Brown-out) protection with configurable threshold for
output on/off
Brown-out maximum power reduction, to better protect primary components from overheating and
saturation
Adaptive output overvoltage protection to meet UL1310 standard (Class 2) for the 54 V LED driver design.
Output and VCC undervoltage protection
Configurable dimming parameters, e.g. dimming curve (linear/quadratic), minimum current, dim-to-off
option (enabled/disabled)
Product validation
Qualified for industrial applications according to the relevant tests of JEDEC47/20/22.
Potential applications
•
Electronic control gear for LED luminaires
Datasheet
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Please read the Important Notice and Warnings at the end of this document
Revision 1.1
2021-06-25
XDPL8210 Digital Flyback Controller IC
XDP™ Digital Power
Potential applications
Lp
Np
AC Input
voltage
Ns
Output
CDC,filter
Vout,cap,rating
Optional VCC
regulator
RZCD,1
CVCC
Na
RZCD,2
CZCD
RHV
VCC
ZCD
GD
IGD,pk
CoolMOS™
Optional VCC
HV
CS
XDPL8210
regulator
RCS
CHV
Vcc
Iout
PWM
GND UART
CDM10VD
0 – 10 V
input
Gnd
CPWM
Figure 1
Rdim+
Potential application 1 for XDPL8210
Vd
(0.7V typ.)
Lp
Np
AC Input
voltage
CDC,filter
Ns
Output
Vout,cap,rating
External
Vcc
supply
Na
RZCD,1
CVCC
CZCD
RZCD,2
RHV
VCC
ZCD
GD
HV
IGD,pk
CoolMOS™
CS
XDPL8210
RCS
CHV
GND
UART
CPWM
Figure 2
PWM
PWM
Dimming
signal
Primary side
Micro-controller
Potential application 2 for XDPL8210
Product type
Package
Marking
Firmware version
Ordering code
XDPL8210
PG-DSO-8
XDPL8210
4.2.0.0
SP001643692
Datasheet
2
Revision 1.1
2021-06-25
XDPL8210 Digital Flyback Controller IC
XDP™ Digital Power
Description
Description
The XDPL8210 is a high performance configurable single-stage flyback controller with high power factor,
primary side regulated constant current output and LP mode.
The primary side control saves external components especially an opto coupler, thus reducing cost and effort
and increasing reliability. With its integrated functionality, XDPL8210 enables an increase set of features without
external parts.
The digital core of the XDPL8210 and its advanced control algorithms provide multiple operation modes such
as QRM1, DCM or Active Burst Mode (ABM). In addition, XDPL8210 includes an enhanced PFC function which
can partially compensate the effect of the input capacitance on power factor and harmonic distortion. With
this functionality and smooth transition between the operation modes, the controller delivers high efficiency,
high power factor and low harmonic distortion over wide load range. The active burst mode control scheme
significantly extends the dimming range and is synchronized with the line frequency avoiding effects like flicker
while reducing audible noise.
Operation parameters such as the output current, dimming curve and the protection features are digitally
configurable. Infineon offers a user friendly Graphic User Interface for Personal Computers, allowing rapid
engineering changes without the need for complex component design iterations. Functionality can be defined
at the end of the production line. Multiple different Light Emitting Diode (LED) drivers can be built with the
same hardware using different XDPL8210 parameter sets.
For instance, the dimming curve shape is configurable to linear or quadratic (eye-adaptive) and can optionally
be inverted. Additionally, dim-to-off can be enabled or disabled.
Note:
By default, the configurable parameters of a new XDPL8210 chip from Infineon are empty, so it is
necessary to configure them before any application testing.
The system performance and efficiency can be optimized using Infineon CoolMOS P7 power MOSFETs.
Datasheet
3
Revision 1.1
2021-06-25
XDPL8210 Digital Flyback Controller IC
XDP™ Digital Power
Table of contents
Table of contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Product validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Potential applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
3.1
3.1.1
3.1.2
3.1.3
3.2
3.3
3.4
3.5
3.5.1
3.5.2
3.5.3
3.6
3.7
3.8
3.8.1
3.8.2
3.8.3
3.8.4
3.8.5
3.8.6
3.8.7
3.8.8
3.8.9
3.8.10
3.8.11
3.8.12
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Regulated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Constant current and limited power set-point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Multimode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Control loop initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Configurable gate voltage rising slope at GD pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Line synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Input voltage, output voltage and output current estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Input voltage estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Output voltage estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Output current estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Power factor correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Dimming control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Protection features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Primary MOSFET overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Output undervoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Output overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Transformer demagnetization time shortage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Regulated mode peak output overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Minimum input voltage startup check and input undervoltage protection . . . . . . . . . . . . . . . . . . 24
Maximum input voltage startup check and input overvoltage protection . . . . . . . . . . . . . . . . . . . 24
VCC undervoltage lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
VCC overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
IC overtemperature protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Other protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Protection reactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4
Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
5
List of Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Datasheet
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XDPL8210 Digital Flyback Controller IC
XDP™ Digital Power
Table of contents
6
6.1
6.2
6.3
6.4
Electrical Characteristics and Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
DC Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7
Package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Datasheet
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XDPL8210 Digital Flyback Controller IC
XDP™ Digital Power
Pin configuration
1
Pin configuration
Pin assignments and basic pin description information are shown below.
ZCD
1
8
GND
PWM
2
7
VCC
CS
3
6
UART
GD
4
5
HV
PG-DSO-8 (150mil)
Figure 3
Pinning of XDPL8210
Table 1
Pin definitions and functions
Name
Pin
Type
Function
ZCD
1
I
Zero-crossing detection:
The ZCD pin is connected to the auxiliary winding via external resistors
divider. It is used for zero-crossing detection, primary-side output voltage
sensing and input voltage sensing.
PWM
2
I
Pulse Width Modulation (PWM) dimming:
The PWM pin is used as a dimming input. The PWM frequency should be fixed
in the range from 500 Hz to 2 kHz.
CS
3
I
Current sensing:
The CS pin is used for Flyback MOSFET current sensing via external shunt
resistor.
GD
4
O
Gate driver:
The GD pin is used for Flyback MOSFET gate drive control via external series
resistor.
HV
5
I
High voltage:
The HV pin is connected to the rectified input voltage via external series
resistor. The HV pin is used to charge VCC pin voltage during startup and
protection, via an internal 600 V startup cell. In addition, it is also used for
line synchronization.
UART
6
I/O
Universal Asynchronous Receiver Transmitter configuration:
The UART pin is used as the digital interface for parameter configuration.
VCC
7
I
Operating voltage supply and sensing
GND
8
-
Integrated Circuit (IC) grounding
Datasheet
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2021-06-25
XDPL8210 Digital Flyback Controller IC
XDP™ Digital Power
Functional block diagram
2
Functional block diagram
The functional block diagram shows the basic data flow from input pins via signal processing to the output pins.
Flyback (with PFC)
HV
Startup
Output Voltage
Sensing
VCC
VCC
Management
Power limitation
UART
Figure 4
Datasheet
Input Voltage
Sensing
ZCD
Output Current
Calculation
CS
UART
Parametrization
FB Control Loop
GD
Temperature
Protection
PWM Dimming
Sensing
PWM
XDPL8210 functional block diagram
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XDPL8210 Digital Flyback Controller IC
XDP™ Digital Power
Functional description
3
Functional description
The functional description provides an overview about the integrated functions and features as well as
their relationship. The mentioned parameters and equations are based on typical values at TA = 25°C. The
corresponding min. and max. values are shown in the electrical characteristics.
3.1
Regulated mode
The XDPL8210 regulated mode provides a primary side control of the output current. The secondary side
feedback components are not necessary for the output current control as the primary side regulation control
loop is fully integrated.
3.1.1
Constant current and limited power set-point
Under non-dimming condition, the regulated mode CC output current set-point is based on the maximum
output current set-point Iout,full. Under dimming condition, the regulated mode CC output current set-point is
selected between Iout,full and minimum output current set-point Iout,min, depending on the dimming level. Both
Iout,min and Iout,full parameters are configurable.
If the output power produced by the regulated mode CC output current set-point and the connected LED
voltage VLED exceeds the configurable maximum output power limit set-point Pout,set, the regulated mode LP set
point based on Pout,set parameter would take over and reduce the output current set-point to Pout,set / VLED.
To achieve a full CC output dimming range between Iout,min and Iout,full, the connected LED voltage VLED should
not exceed Pout,set / Iout,full, as shown in Figure 5.
If only the CC regulation is desired, the LP regulation can be disabled by configuring Pout,set = 0.
Iout set-point
Pout,set
Iout,full
Pout,set / VLED,max
Iout,min
Output VLED,min,dimmed
UVP
Figure 5
Pout,set VLED,max Output
Iout,full
OVP
LED voltage
Operating window with constant current and limited power regulation
Note:
VLED,max refers to the desired maximum operating LED voltage when output current is Iout,full. VLED,max
should be designed well below the output overvoltage protection level.
Note:
VLED,min,dimmed refers to the desired minimum operating LED voltage when output current is Iout,min.
VLED,min,dimmed should be designed well above the output undervoltage protection level.
Datasheet
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XDPL8210 Digital Flyback Controller IC
XDP™ Digital Power
Functional description
3.1.2
Multimode operation
In regulated mode, there are three different switching modes (QRM1, DCM and ABM). The integrated primary
side control loop selects the switching mode depending on the operating condition.
Power
ton,max
Pmax
On-time controlled
QRM1
ton,min (Vin)
fsw,max or fsw,QR1, whichever is lower
Frequency controlled
DCM
ABM
VinUV
Figure 6
•
Pmin,DCM
fsw,min,DCM
fsw,min,DCM/fline/2
Pmin,ABM
Pulse number controlled
NABM,min
Input Voltage
VinOV
Multimode operation scheme
QRM1: This mode minimizes the switching loss by switching on the MOSFET at the quasi-resonant 1st valley
of the primary auxiliary winding voltage VAUX signal, to maximize the efficiency. The power is controlled by
regulating the on-time of the MOSFET.
VGD
time
ton
VAUX
tsw,QR1
Zero crossing
detection
time
0V
Valley
switching
Figure 7
Note:
•
Switching waveforms in QRM1
If the quasi-resonant 1st valley switching period tsw,QR1 is lower than the minimum switching
period of 1/fsw,max, the MOSFET can only be switched on after the quasi-resonant 1st valley.
DCM: This mode minimizes the switching loss by reducing the switching frequency when the output power
is reduced. The on-time is kept at the minimum value, while the power is controlled by regulating the
switching frequency. The minimum power transfer in DCM Pmin,DCM happens when the minimum switching
frequency fsw,min is reached.
Datasheet
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XDPL8210 Digital Flyback Controller IC
XDP™ Digital Power
Functional description
VGD
time
ton
tsw,DCM
VAUX
time
0V
•
Figure 8
Switching waveforms in DCM
ABM: This mode can be enabled with ENABM parameter to deliver a lower output power than in DCM, for
a lower minimum output current. The on-time and switching frequency are kept at the minimum value,
while the power is controlled by regulating the switching pulse number of each burst period. The burst
frequency in this mode is synchronized to the rectified AC input frequency, to ensure good light quality and
low audible noise. The minimum power transfer in ABM Pmin,ABM happens when the minimum switching
pulse number NABM,min is reached.
Minimum on-time adaptation based on estimated input voltage
In all switching modes, ton,min,V,out,sense(Vin) variable is scaled to allow a desired minimum transformer
demagnetization time based on tmin,demag parameter at the peak of input voltage Vin,peak, for output voltage
sensing.
ton, min, V, out, sense V in = tmin, demag ⋅
Equation 1
Np
Ns
⋅
V out
V in, peak
The minimum on-time of ton,min(Vin) is based on ton,min parameter or ton,min,V,out,sense(Vin) variable, whichever is
higher.
ton > ton, min V in = max ton, min, V, out, sense V in , ton, min
Equation 2
Datasheet
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XDPL8210 Digital Flyback Controller IC
XDP™ Digital Power
Functional description
ton,min(Vin)
ton,min,V,out,sense(Vin)
ton,min
0
VinUV
Note:
ton,min,V,out,sense(Vin) = tmin,demag · (Np / Ns) · (Vout / Vin,peak)
Figure 9
Minimum on-time depending on the estimated input voltage
3.1.3
Control loop initialization
VinOV Vin
When the regulated mode is entered initially after the startup phase, the control loop initialization is necessary.
To ensure a fast and smooth startup with minimal output current overshoot, XDPL8210 features an adaptive
control loop switching parameter initialization depending on the ENABM parameter and estimated input voltage
Vin:
•
If ABM is enabled with ENABM parameter, ABM is selected as the initial switching mode for the control loop.
The initial controlled ABM switching pulse number NABM,init is scaled between NABM,min and NABM,init,VinUV
parameters, depending on Vin.
• If ABM is disabled with ENABM parameter, DCM is selected as the initial switching mode for the control loop.
The initial controlled DCM switching frequency number fDCM,init is scaled between fsw,min,DCM parameter and
fDCM,init,VinUV (20 kHz typ.), depending on Vin.
fDCM,init NABM,init
fDCM,init,VinUV
(20 kHz typ.)
Initial control loop in DCM
when ENABM = “Disabled”
fsw,min,DCM
NABM,init,VinUV
Initial control loop in ABM
when ENABM = “Enabled”
NABM,min
VinUV
Figure 10
Note:
Datasheet
Vin,high
VinOV
Vin
Adaptive control loop parameter initialization
VinUV and VinOV refer to the input undervoltage protection level and input overvoltage level parameter
respectively.
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XDPL8210 Digital Flyback Controller IC
XDP™ Digital Power
Functional description
Note:
Vin,high refers to the high input voltage parameter. If the estimated input voltage Vin is Vin,high or more,
NABM,init = NABM,min or fDCM,init = fsw,min,DCM is applied.
3.2
Configurable gate voltage rising slope at GD pin
The gate drive peak voltage VGD,pk is 12 V with sufficient Vcc voltage supply. To achieve a good balance
of switching loss and Electro-Magnetic Interference (EMI), the gate voltage rising slope which determines
the MOSFET switching on speed can be controlled, by configuring the gate driver peak source current IGD,pk
parameter (Configurable range: 30 mA to 118 mA). This saves two components (see Dfastoff, Rslowon in Figure 11),
which are conventionally added for the same purpose.
VGD
Dfastoff
VGD,pk
(12V typ.)
IGD,pk
GD
=118mA
RG
Rslowon
Not needed
IGD,pk
RCS
= 30mA
t
Figure 11
Configurable gate voltage rising slope and component saving
3.3
Startup
The startup phase is entered upon checking the startup conditions (e.g. input voltage, IC temperature) are
within limits.
To estimate the input voltage level before startup, ZCD pin signal is measured during a single pulse generated
on GD pin. This single pulse has an on-time based on the pre-start CS pin maximum voltage limit of VOCP1,init or
8 times of the leading edge blanking time tCS,LEB (e.g. 8 * 480 ns = 3.84 μs typ.). If the estimated input voltage
or any other startup conditions are not within limits, startup phase is not entered and this single pulse will be
generated again after an auto-restart duration.
The startup phase consists of soft start phase, output charging phase and PWM duty cycle measuring phase.
The soft start phase is to minimize the component stress during startup. The output charging phase is to fast
charge the output voltage for fast VCC voltage self supply takeover from the primary auxiliary winding, while the
PWM duty cycle measuring phase is to determine the regulated mode output current set-point.
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Functional description
Startup phase
Voltage
Soft start phase
(based on nss = 3 configuration as example)
Output
charging
phase
Vout,dim,min
Vout,start
PWM duty
cycle
measuring
phase
VOCP1,init
Vout
Control loop
initialization
VOCP1
Pre-Startup Check
(e.g. input voltage,
IC temperature)
Regulated Mode
CS pin voltage level 1 for MOSFET
max current cycle by cycle limit
Vstart,OCP1
Startup with 1st
soft start step
0
Figure 12
tSS
2 tSS
3 tSS
tout,charge tstart,max
time
Start up phase with soft start step nss=3
During soft start phase, the switching frequency is fixed at 20 kHz. The MOSFET current is limited in the first soft
start step based on CS pin maximum voltage limit of Vstart,OCP1/(nss + 1), where Vstart,OCP1 is the parameter for the
output charging phase CS pin maximum voltage limit and nss is the parameter for the number of soft start steps.
The soft start phase CS pin maximum voltage limit is increased by Vstart,OCP1/(nss + 1) after each soft start step
until Vstart,OCP1 is reached, and the typical duration of each soft start step tss is 3.2/nss ms or 0.5 ms, whichever is
lower.
During output charging phase, the output voltage is fast charged with MOSFET switching pulses based on
either the output charging phase CS pin maximum voltage limit of Vstart,OCP1 or the maximum on time of
ton,max in QRM1. To exit the startup phase and enter the regulated mode without triggering the startup output
undervoltage protection, the ZCD pin estimated output voltage Vout has to reach the output charging voltage
set-point of Vout,start before the maximum allowable startup phase duration of tstart,max is reached (see example
in Figure 12 ). To avoid output overshoot, Vout,start should be designed below the fully dimmed minimum output
LED voltage Vout,dim,min.
tstart,max parameter can be indirectly configured with VCC capacitance parameter CVCC, based on:
tstart, max = 967 ⋅ CVCC
Equation 3
Note:
A typical leading edge blanking time tCS,LEB of 480 ns applies on VOCP1,init, Vstart,OCP1 and the CS pin
maximum voltage limit for every soft start step starting from Vstart,OCP1/(nss + 1).
During the PWM duty cycle measurement phase, the MOSFET switching pulses are based on very short on-time
and switching frequency of fsw,DIM,DCM (1 kHz typically).
After the startup phase is ended with neither protection triggering nor dim-to-off entering, the control loop is
initialized for output current regulation in the regulated mode.
3.4
Line synchronization
The XDPL8210 synchronizes most of its operation to the AC input half sine wave period or the rectified AC
input frequency, via the HV pin. For instance, based on AC input frequency of 50 Hz, the line synchronization
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Functional description
should be based on the rectified AC input frequency of 100 Hz or AC input half sine wave period of 10 ms.
Such line synchronization is used for the enhanced PFC in compensating the input current displacement caused
by the line filter and DC link filter capacitor. If the line synchronization is not established, for example during
startup, the controller would synchronize its operation based on an internally preset half sine wave period of
approximately 9.823 ms.
3.5
Input voltage, output voltage and output current estimation
As shown in Figure 13, the auxiliary winding voltage signal VAUX sensed via ZCD pin contains information of
the transformer demagnetization time tdemag, reflected output voltage and reflected input voltage, while the
primary peak current signal Ip,pk sensed via CS pin contains the secondary peak current Is,pk information. To
estimate the output current, the tdemag and Is,pk information are necessary.
VAUX
Reflected output
voltage sampling
Zero crossing detection
time
Valley switching
Reflected input
voltage sampling
Ip
Is
Vin
Itransformer
Vout
Np
Na
Is,pk
Ip,pk
Ip
VAUX
Ip
Is
Ns
time
tdemag
tsw,FB
VGD
tCS,sample
Figure 13
Datasheet
tZCD,sample
time
Flyback switching waveform example in QRM1
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Functional description
3.5.1
Input voltage estimation
The input voltage is estimated by sensing the reflected input voltage signal from the transformer primary
auxiliary winding voltage VAUX, when the MOSFET is switched on. As the reflected input voltage signal is a
negative voltage which cannot be sensed directly, the voltage at ZCD pin is clamped to a negative voltage of
VINPCLN. A resistor divider with RZCD,1 and RZCD,2 adapts -IIV which is the clamping current flowing out of ZCD pin,
based on its operational range, while a ZCD pin filter capacitor CZCD is needed for noise filtering, as shown in
Figure 14.
Based on the sampled clamping current -IIV at the timing of tCS,sample shown in Figure 13, which is at the end of
on-time, the reflected input voltage signal from VAUX is sensed. The interval of each -IIV sample is approximately
1/64 of the half sine wave period.
Note:
The half sine wave period is either 9.823 ms or the inverse of the rectified AC input frequency, based on
the operating conditions, as explained in Line synchronization.
The estimated peak input voltage Vin,peak over a half sine wave period is based on:
V in, peak = max
Equation 4
Np
Na
⋅
−I IV −
V INPCLN
RZCD, 2
⋅ RZCD, 1 − V INPCLN +
Rin
RCS
⋅ V CS, peak
Where Np is the primary main winding turns, Na is the primary auxiliary winding turns, RCS is the CS pin shunt
resistor value, VCS,peak is the peak CS pin voltage, and Rin is the fine-tuning parameter for input voltage sensing
accuracy improvement by compensating the switching frequency voltage ripple on CDC,filter.
The estimated input voltage Vin in rms value is assumed by the controller as 0.707 of Vin,peak based on a filtered
value over a few half sine wave periods. The update rate of Vin is once per half sine wave period.
V in = 0.707 ⋅ V in, peak
Equation 5
Na
ZCD
RZCD,1
IIV
CZCD
VDC,filter
Vin,peak
Vin
CDC,filter
VAUX
VINPCLN
RG
RZCD,2
GD
VCS
RCS
Figure 14
VDC,filter
Np
Input voltage estimation based on -IIV
The estimated input voltage Vin is used for input voltage protections and the enhanced PFC (EPFC). Therefore, it
is important to ensure that IC parameters RZCD,1, RZCD,2, Np, Na and RCS are configured as per the actual system
hardware dimensioning.
3.5.2
Output voltage estimation
The output voltage is estimated by sensing the reflected output voltage signal from the transformer
primary auxiliary winding voltage VAUX, when the MOSFET is switched off and near the end of transformer
demagnetization. A resistor divider with RZCD,1 and RZCD,2 adapts the voltage at ZCD pin based on its operational
range, while a ZCD pin filter capacitor CZCD is needed for noise filtering, as shown in Figure 15.
Based on the sampled ZCD pin voltage VZCD,SH at the timing of tZCD,sample shown in Figure 13, which is
approximately a quarter of oscillation period (Tosc/4) before the 1st zero crossing of VAUX, a ratio of the reflected
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Functional description
output voltage signal from VAUX is sensed. The interval of each VZCD,SH sampling is approximately 1/64 of the half
sine wave period, while the oscillation period Tosc is measured once before startup and updated every 7th half
sine wave period after entering the regulated mode.
Note:
The half sine wave period is either 9.823 ms or the inverse of the rectified AC input frequency, based on
the operating conditions, as explained in Line synchronization.
Note:
As VAUX zero crossing can only be detected by the IC via ZCD pin upon its internal analog delay plus
external delay caused by CZCD, tZCDPD parameter fine-tuning is needed to compensate such delays, to
have the proper timing of tZCD,sample for output voltage estimation.
Attention: Please note that the transformer demagnetization time tdemag has to be longer than 2.0 μs to
ensure that the reflected output voltage can be sensed properly at the ZCD pin.
The estimated output voltage Vout is based on:
V out = V ZCD, SH ⋅
RZCD, 1 + RZCD, 2
RZCD, 2
Equation 6
⋅
Ns
Na
− Vd
Where Ns is the transformer secondary main winding turns, Na is the transformer primary auxiliary winding
turns and Vd is the secondary main output diode forward voltage (assumed by the controller as 0.7 V).
Vd
Na Ns
RZCD,1
ZCD
Vout
VAUX
CZCD
Figure 15
Cout
VZCD,SH
RZCD,2
Output voltage estimation based on VZCD,SH
The estimated output voltage Vout is used for output voltage protections and the enhanced PFC (EPFC).
Therefore, it is important to ensure that IC parameters RZCD,1, RZCD,2, Ns and Na are configured as per the actual
system hardware dimensioning.
3.5.3
Output current estimation
Based on the sampled CS pin voltage VCS,SH at the timing of tCS,sample shown in Figure 13, which is at the end of
on-time, the primary peak current signal Ip,pk is sensed. The interval of each VCS,SH sample is approximately 1/64
of the half sine wave period.
Note:
The half sine wave period is either 9.823 ms or the inverse of the rectified AC input frequency, based on
the operating conditions, as explained in Line synchronization.
To compensate the propagation delay between the falling edges of GD pin voltage and Ip,pk, as shown in
Figure 16, a more accurate primary peak current Ip,pk can be estimated by optimizing the propagation delay
compensation parameter tPDC value:
I p, pk =
V CS, SH
RCS
Equation 7
Datasheet
⋅
ton + tPDC
ton
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Functional description
Ip
Ip,pk =
VCS,SH
RCS
VCS,pk
RCS
t
tPDC
VGD
t
ton
Figure 16
Propagation delay compensation for more accurate primary peak current estimation
The secondary peak current Is,pk can be estimated based on Ip,pk, transformer turns ratio Np/Ns, transformer
coupling coefficient Kcoupling, primary main winding inductance Lp and primary leakage inductance Lp,lk:
I s, pk = I p, pk ⋅
Equation 8
Note:
Np
Ns
⋅ K coupling ⋅
Lp
Lp + Lp, lk
Lp,lk is 1% of Lp by default.
The average output current per switching cycle Iout(n) can be estimated based on Is,pk, transformer
demagnetization time tdemag, switching period tsw, ABM pulse number NABM, line frequency fline, DCM minimum
switching frequency parameter fsw,min,DCM, the estimated output voltage Vout, output undervoltage protection
level VoutUV and the auxiliary loss compensation parameter Gloss which is to achieve better load regulation at
low output current.
•
Iout(n) in QRM1 and DCM:
I out, QRM1, DCM n =
1
2
⋅ I s, pk ⋅
tdemag
tsw
− Gout, loss ⋅ V out − V outUV
Equation 9
•
Iout(n) in ABM:
I out, ABM n =
1
2
⋅ I s, pk ⋅
tdemag
tsw
⋅ N ABM ⋅
2 ⋅ fline
fsw, min, DCM
− Gout, loss ⋅ V out − V outUV
Equation 10
The interval of each Iout(n) sample is approximately 1/64 of the half sine wave period. The average output
current per half sine wave period for output regulation is obtained from the moving average filter based on 64
Iout(n) samples.
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Functional description
Note:
3.6
The half sine wave period is either 9.823 ms or the inverse of the rectified AC input frequency, based on
the operating conditions, as explained in Line synchronization.
Power factor correction
For better PFC, the patented enhanced PFC (EPFC) feature can be enabled by configuring CEMI parameter value
above zero and fine-tuning the value, to compensate the input current displacement effect which is mainly
caused by the DC link filter capacitor CDC,filter. With this feature enabled, in QRM1, the regulated on-time is not
constant, but modulated with a function based on the estimated input voltage Vin, estimated output voltage
Vout, estimated output current, phase angle and modulation gain of CEMI parameter value.
The enhanced PFC (EPFC) feature can also be disabled by configuring CEMI parameter as zero.
3.7
Dimming control
The XDPL8210 senses the duty cycle of the PWM pin voltage signal, to determine the output current set-point
based on the configured dimming curve and maximum power limit setting. In regulated mode, the output
current is analogue (except for ABM) and the output ripple frequency is synchronized to the double line
frequency, to achieve flicker-free operation.
PWM pin internal pull up resistor
The PWM pin internal pull up resistor can be optionally enabled by configuring PWMR,pull,up parameter between
2.25 kohm and 30 kohm. The internal pull up voltage is 3.2 V typically.
PWM pin duty cycle sensing and frequency range
The XDPL8210 can sense the duty cycle based on either a normal PWM signal or an inverted PWM signal, by
configuring the PWMtype parameter.
VPWM
PWMtype parameter setting
Normal
Inverted
VIH
time
VPWM
PWM
duty cycle
TPWM
PWM
duty cycle
VIH
VIL
VPWM
tPWM,H
TPWM
tPWM,L
TPWM
time
PWMtype parameter setting
Normal
Inverted
VIL
time
Figure 17
0%
PWMtype parameter setting
Normal
Inverted
tPWM,L
tPWM,H
100%
PWM
duty cycle
0%
100%
Duty cycle based on the selectable PWM type
To sense a stable PWM duty cycle level for the regulation based on a stable output current set-point, a hysteresis
level for PWM duty cycle jittering suppression is configurable based on PWMDuty,hyst parameter. Any change of
the PWM duty cycle within the hysteresis will not affect the output current.
The PWM frequency should be fixed in the range of 500 Hz and 2 kHz.
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Functional description
Dimming curve
The XDPL8210 can be configured based on CDIM parameter, to use either a linear or a quadratic dimming curve
for the mapping of the PWM duty cycle to the output current set-point, as shown in Figure 18. The PWM duty
cycle levels of DDIM,min and DDIM,max ensure that the minimum current Iout,min and maximum current Iout,full can
always be achieved, thereby making the application robust against component tolerances.
Iout set-point
Iout set-point
Iout,full
Iout,full
Non power limiting
(Pout < Pout,set)
Power limiting
(Pout = Pout,set)
CDIM=”Linear”
Iout,min
DDIM,off DDIM,min
DDIM,on
100%
DDIM,max
PWM
duty cycle
Power limiting
(Pout = Pout,set)
CDIM=”Quadratic”
Iout,min
DDIM,off DDIM,min
DDIM,on
(90% typ.)
Figure 18
Non power limiting
(Pout < Pout,set)
100%
DDIM,max
PWM
duty cycle
(90% typ.)
Selectable Dimming Curves
If the DIMtype parameter is configured as "Dim (to off)", dim-to-off is entered to turn off the light output when the
measured PWM duty cycle gets below DDIM,off (see purple line in Figure 18). During dim-to-off, if the measured
PWM duty cycle gets above DDIM,on, the regulated mode is entered to turn on the light output. After hardware
reset, if the first measured PWM duty cycle is above DDIM,off, the regulated mode is entered to turn on the light
output.
During dim-to-off, the output voltage is recharged (based on Vout,start parameter) to measure the PWM
duty cycle, every fast auto-restart period tauto,restart,fast of 400 ms approximately. While the PWM duty cycle
measurement is ongoing, the controller GD pin switching frequency is based on fsw,DIM,DCM of 1 kHz typically. To
achieve low standby power during dim-to-off, the sleep mode is entered if the measured PWM duty cycle gets
below DDIM,off.
Note:
A weak passive bleeder on the output is required for proper dim-to-off operation.
If the DIMtype parameter is configured as "Dim (without off)", the light output is not turned off and the output
current set-point is based on Iout,min when the measured PWM duty cycle gets below either DDIM,min or DDIM,off
(see green line in Figure 18).
If the output power is limited by Pout,set, the output current set-point follows the cyan line in Figure 18 which
would result to extended dead travel below DDIM,max. As soon as the product of output current and output
voltage drops below Pout,set, the output current will follow the green line, as shown in Figure 18)).
3.8
Protection features
Protections ensure the operation of the controller under restricted conditions. The protection monitoring
signal(s) sampling rate, protection triggering condition(s) and protection reaction are described in this section.
Attention: The sampled protection monitoring signal accuracy is subjective to the digital quantization,
tolerances of components (including IC) and estimations with indirect sensing (e.g. input and
output voltage estimations based on ZCD, CS pin signals), while the protection level triggering
accuracy is subjective to the sampled signal accuracy, sampling delay, indirect sensing delay
(e.g. reflected output voltage signal cannot be sensed by ZCD pin near AC input phase angle of 0°
and 180°) and blanking time.
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Functional description
3.8.1
Primary MOSFET overcurrent protection
VOCP2 denotes the CS pin voltage level 2 for primary MOSFET overcurrent protection. Under the single fault
condition of shorted primary main winding, the primary MOSFET overcurrent protection is triggered when the
CS pin voltage exceeds VOCP2 for longer than a blanking time based on tCSOCP2 parameter.
Note:
tCSOCP2 parameter is 240 ns by default.
The level of VOCP2 is automatically selected based on #unique_39/unique_39_Connect_42_table_dxh_gzl_jhb.
Table 2
VOCP2 level selection depending on VOCP1 parameter value
VOCP1 (V)
VOCP2 (V)
0.40 to 0.54
0.8
0.55 to 0.72
1.2
0.73 to 1.08
1.6
The reaction of primary MOSFET overcurrent protection is fixed as auto-restart.
3.8.2
Output undervoltage protection
In case of a short or too low LED load voltage, the output voltage would drop to a low level. The output
undervoltage protection can be triggered, if the condition is met by monitoring the estimated output voltage
Vout based on the ZCD pin switching signal (see Output voltage estimation for details).
In regulated mode, if the estimated output voltage Vout is lower than the VoutUV parameter for longer than a
blanking time of tVoutUV,blank parameter, the regulated mode output undervoltage protection is triggered.
The reaction of the regulated mode output undervoltage protection is fixed as auto-restart.
Note:
By default, VoutUV is fixed as 50% of the configurable Vout,dim,min parameter. Vout,dim,min denotes the
fully dimmed minimum output LED voltage.
Vout
Output undervoltage protection
triggered after
tVoutUV,blank
VoutUV
time
Regulated Mode
(Vout > VoutUV)
Regulated Mode
(Vout < VoutUV for tVoutUV,blank)
Note: VoutUV level is fixed as 50% of Vout,dim,min parameter.
Figure 19
Regulated mode output undervoltage protection
In startup phase, if the estimated output voltage Vout is lower than Vout,start parameter over a timeout period
of tstart,max parameter, the startup output undervoltage protection is triggered. tstart,max parameter refers to the
maximum allowable duration of the soft-start phase and output charging phase. It can be indirectly configured
with VCC capacitance parameter CVCC.
The reaction of startup output undervoltage protection is fixed as auto-restart.
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Functional description
Normal startup
Voltage
Output short startup
Voltage
tstart,max
tstart,max
tout,charge
Vout
Vout,start
Vout,start
VVCCON
VVCCON
(20.5V typ.)
(20.5V typ.)
VVCC
VUVOFF
VUVOFF
(6V typ.)
(6V typ.)
time
tVCCON,charge
tVCC,holdup
VVCC
Vout
Startup output undervoltage
protection triggered
(Vout < Vout,start at tstart,max)
time
tVCCON,charge tVCC,holdup
Note:
tstart,max = 0.8 · (VVCCON - VUVOFF) / IIC,avg,est.
= 0.8 · CVCC · (20.5 V – 6 V) / 12 mA
= 967 · CVCC
Figure 20
Normal startup and startup output undervoltage (short) protection waveforms
3.8.3
Output overvoltage protection
In case of output open, the output voltage may rise to a high level. The output overvoltage protection can
be triggered, if the condition is met by monitoring the estimated output voltage Vout based on the ZCD pin
switching signal (see Output voltage estimation for details).
If the estimated output voltage Vout is higher than VoutOV for longer than a blanking time, the output overvoltage
protection is triggered.
Note:
In QRM1 and DCM, the blanking time is typically a quarter of the half sine wave period. In ABM, the
blanking time is configurable based on tVoutOV,blank,ABM parameter.
Note:
The half sine wave period is either 9.823 ms or the inverse of the rectified AC input frequency, based on
the operating conditions, as explained in Line synchronization.
The reaction of the output overvoltage protection is configurable to auto-restart or latch-mode based on
ReactionOVP,Vout parameter. Figure 21 shows an example of the output overvoltage protection and recovery
waveform, based on the auto-restart reaction.
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XDP™ Digital Power
Functional description
Max. Iout
Vout set-point
First triggering of
output OVP Subsequent triggerings of output OVP
VoutOV
Effective output
OVP level
Reconnect of LED load
tauto-restart
Removal of LED load
Iout,full
time
Regulated
Mode
Figure 21
Auto-restart protection
Regulated
Mode
Output overvoltage protection and recovery waveform
Attention: It is mandatory to ensure that VoutOV is configured well below the actual output capacitor
voltage rating Vout,cap,rating ,while the Vout,cap,rating is not exceeded in actual testing with all the
necessary test conditions. The protection level triggering accuracy is subjective to the sampled
signal accuracy, sampling delay, indirect sensing delay (e.g. reflected output voltage signal
cannot be sensed by ZCD pin near AC input phase angle of 0° and 180°) and blanking time.
Attention: If the minimum ABM switching pulses number parameter NABM,min and minimum output current
parameter Iout,min configured values are both very low, the output overvoltage protection actual
triggering level might drift up when output current set-point is Iout,min.
Adaptive output overvoltage protection level
To have lower output open load voltage during auto-restart, the adaptive output overvoltage protection can be
enabled with the ENadaptive,OVP,Vout parameter, as shown in Figure 22.
Upon triggering the enabled adaptive output overvoltage protection for the first time, the protection level is
reduced from Vout,OV to Vout,OV,red and the output current set-point maximum limit is reduced from Iout,full to
Iout,OVP,red.
For a successful output recovery, the estimated output voltage Vout upon auto-restart has to be lower than
Vout,OV,red for a number of half sine wave periods based on NVout,restore parameter, in order to restore the
protection level and the output current set-point maximum limit to Vout,OV and Iout,full, respectively.
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Functional description
Vout
Max. Iout
set-point
VoutOV
VoutOV,red
First triggering of
output OVP
Subsequent triggerings of output OVP
Effective output
OVP level
Reconnect of LED load
tauto-restart
Removal of LED load
Iout,full
Iout,OVP,red
NVout,restore
time
Regulated
Mode
Figure 22
Note:
3.8.4
Auto-restart protection
Regulated
Mode
Adaptive output overvoltage protection and recovery waveform
The half sine wave period is either 9.823 ms or the inverse of the rectified AC input frequency, based on
the operating conditions, as explained in Line synchronization.
Transformer demagnetization time shortage protection
In case of insufficient transformer demagnetization time, the reflected output voltage signal cannot be properly
sensed via the ZCD pin. If such condition presents for longer than 50% of a half sine wave period, the protection
will be triggered. The reaction of this protection is fixed as auto-restart.
Note:
3.8.5
The half sine wave period is either 9.823 ms or the inverse of the rectified AC input frequency, based on
the operating conditions, as explained in Line synchronization.
Regulated mode peak output overcurrent protection
By monitoring the estimated average output current per switching cycle based on the switching signals
(see Output current estimation for details), the regulated mode peak output overcurrent protection can be
triggered if the condition is met.
ENIout,max,peak parameter refers to the enable switch for the regulated mode peak output overcurrent protection.
Upon startup and in the regulated mode, if ENIout,max,peak parameter is enabled and the average output current
per switching cycle is higher than Iout,max,peak for longer than a blanking time, the regulated mode peak output
current protection will be triggered. The blanking time is based on Iout,max,peak,blank parameter.
The reaction of the regulated mode peak output overcurrent protection is fixed as auto-restart. The auto-restart
speed is configurable based on SpeedOCP,Iout parameter:
• If SpeedOCP,Iout is configured as "fast", the auto-restart time is approximately 0.4 second.
• If SpeedOCP,Iout is configured as "slow", the auto-restart time is based on the configurable tauto,restart
parameter.
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Functional description
3.8.6
Minimum input voltage startup check and input undervoltage
protection
By monitoring the estimated input voltage Vin based on the ZCD pin and CS pin switching signals (see Input
voltage estimation for details), the minimum input voltage startup check can be performed, and the input
undervoltage protection can be triggered if the condition is met.
ENUVP,In parameter refers to the enable switch for the minimum input voltage startup check (based on
Vin,start,min) and input undervoltage protection (based on VinUV).
Note:
Vin,start,min parameter refers to the minimum input voltage level for startup, while VinUV parameter
refers to the input undervoltage protection level.
During pre-startup check, if ENUVP,In parameter is enabled and the estimated input voltage Vin is lower than
Vin,start,min, the startup phase will not be entered and the protection reaction of auto-restart will be performed.
Upon startup and in the regulated mode, if ENUVP,In parameter is enabled and the estimated input voltage Vin
is lower than VinUV for longer than a blanking time, the input undervoltage protection will be triggered. The
blanking time of the input undervoltage protection is typically 10 half sine wave periods.
Note:
The half sine wave period is either 9.823 ms or the inverse of the rectified AC input frequency, based on
the operating conditions, as explained in Line synchronization.
The reaction of the input undervoltage protection is fixed as auto-restart.
3.8.7
Maximum input voltage startup check and input overvoltage
protection
By monitoring the estimated input voltage Vin based on the ZCD pin and CS pin switching signals (see Input
voltage estimation for details), the maximum input voltage startup check can be performed, and the input
overvoltage protection can be triggered if the condition is met.
ENOVP,In parameter refers to the enable switch for the maximum input voltage startup check (based on
Vin,start,max) and input overvoltage protection (based on VinOV).
Note:
Vin,start,max parameter refers to the maximum input voltage level for startup, while VinOV parameter
refers to the input overvoltage protection level.
During pre-startup check, if ENOVP,In parameter is enabled and the estimated input voltage Vin is higher than
Vin,start,max, the startup phase will not be entered and the protection reaction of auto-restart will be performed.
Upon startup and in the regulated mode, if ENOVP,In parameter is enabled and the estimated input voltage Vin
is higher than VinOV for longer than a blanking time, the input overvoltage protection will be triggered. The
blanking time of the input overvoltage protection is typically 1 half sine wave period.
Note:
The half sine wave period is either 9.823 ms or the inverse of the rectified AC input frequency, based on
the operating conditions, as explained in Line synchronization.
The reaction of the input overvoltage protection is fixed as auto-restart.
3.8.8
VCC undervoltage lockout
The Undervoltage Lockout (UVLO) is implemented in the hardware. It ensures the enabling and disabling of the
IC operation based on the defined thresholds of the operating supply voltage VVCC at the VCC pin.
The UVLO contains a hysteresis with the voltage thresholds VVCCon for enabling the controller and VUVOFF for
disabling the controller. Once the mains input voltage is applied, current flows through an external resistor into
the HV pin via the integrated depletion cell and diode to the VCC pin. The controller is enabled once VVCC exceeds
the VVCCon threshold and VVCC will then start to drop. For normal startup, VVCC supply should be taken over by
either external supply or the self-supply via the auxiliary winding before VVCC drops to VUVOFF.
Datasheet
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XDP™ Digital Power
Functional description
3.8.9
VCC overvoltage protection
If the sampled VCC voltage is higher than the VCC overvoltage protection level VVCC,max, the VCC overvoltage
protection will be triggered. The VCC overvoltage protection reaction is fixed as auto-restart.
The VCC voltage is sampled once per 7 half sine wave periods.
Note:
The half sine wave period is either 9.823 ms or the inverse of the rectified AC input frequency, based on
the operating conditions, as explained in Line synchronization.
3.8.10
IC overtemperature protection
If the sampled IC junction temperature Tj is higher than Tcritical parameter, the IC overtemperature protection
will be triggered. The protection reaction is fixed as auto-restart, while the maximum junction temperature for
startup and restart Tstart,max is fixed as 4°C below Tcritical.
The IC junction temperature Tj is sampled once per 7 half sine wave periods.
Note:
The half sine wave period is either 9.823 ms or the inverse of the rectified AC input frequency, based on
the operating conditions, as explained in Line synchronization.
Attention: IC lifetime is not guaranteed when operating junction temperature is above 125°C, which is
possible if Tcritical is configured above 119°C, with temperature sensing tolerance of ± 6°C.
Pout
Over-temperature
Protection triggered
TJ
4°C typ.
Tstart,max
Figure 23
IC overtemperature protection
3.8.11
Other protections
•
•
•
•
•
•
Tcritical
A hardware weak pull-up protects against an open CS pin. The reaction of this protection reaction is
auto-restart.
A firmware watchdog triggers a protection if the ADC hardware cannot provide all necessary information
within a defined time period. This may occur if timing requirements for the ADC are exceeded. The reaction
of this protection is fast auto-restart.
A hardware watchdog checks correct execution of firmware. A protection is triggered in the event that
the firmware does not service the watchdog within a defined period. The reaction of this protection is
auto-restart.
A hardware parity check triggers a protection if a bit in the memory changes unintentionally. The reaction
of this protection is auto-restart.
A firmware Cyclic Redundancy Check at each startup verifies the integrity of firmware and parameters. The
reaction of this protection is stop mode.
A firmware task execution watchdog triggers a protection if the firmware tasks are not executed as
expected. The reaction of this protection is auto-restart.
Datasheet
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XDPL8210 Digital Flyback Controller IC
XDP™ Digital Power
Debug mode
•
•
A protection is triggered if the configurable parameter values are empty at startup. The reaction of this
protection is stop mode.
A protection is triggered if no reflected input voltage signal sensed from the ZCD pin at startup. The reaction
of this protection is stop mode.
3.8.12
Protection reactions
The sequence of a protection reaction (not including hardware restart reaction) is as follows:
1.
Upon triggering a protection, the gate driver is disabled within a maximum time, which is 1/512 of the
half sine wave period.
Note:
2.
The reaction depends on the triggered protection:
•
In case of latch mode, the application will enter latch mode at this time. No further sequence is done
until VCC voltage drops below VUVOFF.
•
In case of auto-restart reaction, the controller will enter power saving mode PSMD2 with the
auto-restart time based on tauto,restart parameter.
•
In case of fast auto-restart reaction, the controller will enter power saving mode PSMD2 with the fast
auto-restart time of 0.4 sec.
Note:
For latch mode, auto-restart and fast auto-restart reactions, the internal HV startup cell is
automatically enabled and disabled during this sequence, in order to keep the VCC voltage
between the VUVLO and VOVLO thresholds.
Note:
3.
4.
5.
The half sine wave period is either 9.823 ms or the inverse of the rectified AC input frequency,
based on the operating conditions, as explained in Line synchronization.
For stop mode, if there is no external voltage supply for the VCC, the VCC voltage will drain to
VUVOFF and a hardware restart will be performed.
After the (fast) auto-restart time is expired, the controller executes a single discharge pulse of duration
tpw. This pulse partially discharges the capacitance after the bridge rectifier to improve accuracy of the
next pre-startup input voltage check.
Any auto restart may include a new VCC charging cycle. The recharging time of VCC via HV pin current
depends on the input voltage level and VCC level at the time when the (fast) auto-restart time is expired.
The power stage will enable its gate driver for pre-startup check. If the conditions for pre-startup check
are within limits, the startup phase is entered and followed by the regulated mode. During this time,
if any protection is triggered, the sequence of a protection reaction (not including hardware restart
reaction) starts again from step number 1 above.
4
Debug mode
If an unexpected system protection was triggered during testing, the DebugMode parameter can be enabled to
enter stop mode reaction upon the protection triggering (except for VCC undervoltage lockout), to read out the
firmware status code. For example in Figure 24, the firmware status code readout in the GUI shows a number of
0040H (in red color), which indicates that the input undervoltage protection has been triggered.
Note:
If there is no protection being triggered, the firmware status code should be 0000H (in black color).
Note:
Datasheet
DebugMode parameter should only be enabled for debugging purpose. For actual application running,
it has to be disabled.
26
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XDP™ Digital Power
Debug mode
Figure 24
Firmware status code readout for debugging
Please refer to the design guide for the recommended setup & procedures to read out the firmware status code
in debug mode.
Datasheet
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XDP™ Digital Power
List of Parameters
5
List of Parameters
This list provides information about the configurable and fixed parameters.
This document uses symbols to ease the readability of formulas. As some tools do not support this format,
the symbols are translated into plain text using underscores. For example, the parameter fsw,max translates to
f_sw_max.
All parameter values are typical settings. The accuracy might vary due to digital quantization and tolerances.
Note:
By default, the configurable parameters of a new XDPL8210 chip from Infineon are empty, so it is
necessary to configure them digitally via UART pin before any application testing.
List of configurable parameters
Table 3
Configurable parameters for output set-points
Symbol
Basic description
Example
Minimum
value
Maximum
value
Iout,full
Steady-state maximum output current set-point
830 mA
Refer GUI
Refer GUI
Pout,set
Steady-state maximum output power limit setpoint
34.5 W
Refer GUI
Refer GUI
Table 4
Configurable parameters for dimming
Maximum
value
Symbol
Basic description
Example
Minimum
value
DIMtype
Dimming type via PWM pin
Dim (to
off)
•
•
•
Iout,min
Minimum output current set-point
41.5 mA
Refer GUI
CDIM
Shape of the dimming curve
Linear
•
•
Linear
Quadratic
PWMtype
PWM type
Inverted
•
•
Normal
Inverted
fPWM,max
Maximum switching frequency of PWM dimming
signal
1050 Hz
fPWM,min
2000 Hz
fPWM,min
Minimum switching frequency of PWM dimming
signal
950 Hz
500 Hz
fPWM,max
DDIM,max
PWM duty cycle level for maximum output current
90%
DDIM,min
Refer GUI
DDIM,min
PWM duty cycle level for minimum output current
15%
DDIM,off
DDIM,max
DDIM,on
PWM duty cycle level for exiting dim-to-off
11%
DDIM,off
DDIM,min
DDIM,off
PWM duty cycle level for entering dim-to-off
10%
Refer GUI
DDIM,min
PWMDuty,hyst
Hysteresis level for PWM duty cycle jittering
suppression
0.1%
0%
2%
Datasheet
28
Non-dim
Dim (without off)
Dim (to off)
Iout,full
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XDPL8210 Digital Flyback Controller IC
XDP™ Digital Power
List of Parameters
Table 5
Configurable parameters for hardware configuration
Symbol
Basic description
Example
Minimum
value
Maximum
value
Np
Transformer primary main winding turns
58
1
300
Ns
Transformer secondary main winding turns
17
1
300
Na
Transformer primary auxiliary winding turns
15
1
300
Lp
Transformer primary main winding inductance
0.566 mH
Refer GUI
3 mH
RCS
Current sense resistor value
0.22 Ω
0.1 Ω
3Ω
RZCD,1
ZCD series resistor
56.2 kΩ
Refer GUI
255 kΩ
RZCD,2
ZCD shunt resistor
2.7 kΩ
Refer GUI
Refer GUI
VCCsupply
VCC voltage supply
Wide
•
•
•
CVCC
VCC capacitor value
15 µF
Refer GUI
100 µF
Vout,cap,rating
Output capacitor voltage rating
80 V
10 V
450 V
RHV
HV series resistor
100 kΩ
Refer GUI
255 kΩ
IGD,pk
Gate driver peak source current
30 mA
30 mA
118 mA
PWMR,pull,up
PWM pin internal pull up resistor
2.25 kΩ
2.25 kΩ to 30 kΩ, or Disabled
Table 6
Wide
Narrow
External
Configurable parameters for startup
Symbol
Basic description
Example
Minimum
value
Maximum
value
nss
Number of soft start steps
20
1
20
Vout,dim,min
Minimum output voltage when fully dimmed
12 V
Vout,start
VoutOV
Vout,start
Output charging phase output voltage set-point
10.5 V
50% of
Vout,dim,min
Vout,dim,min
Vstart,OCP1
Output charging phase CS pin voltage level 1 for
MOSFET max. current cycle by cycle limit
0.5 V
Refer GUI
VOCP1
VOCP1,init
Initial CS pin voltage level 1 for MOSFET max.
current limit on the input voltage measurement
pulse before startup
0.3 V
Refer GUI
VOCP1
Table 7
Configurable parameters for protections
Symbol
Basic description
Example
Minimum
value
Maximum
value
tauto,restart
Auto-restart time
1.6 s
0.4 s
4.0 s
VOCP1
Regulated mode CS pin voltage level 1 for MOSFET 0.5 V
max. current cycle by cycle limit
Refer GUI
1.08 V
Autorestart
Auto-restart
Latch-Mode
56.9 V
Vout,dim,min
Refer GUI
ReactionOVP,Vou Output overvoltage protection reaction
t
VoutOV
Output overvoltage protection level
(table continues...)
Datasheet
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XDP™ Digital Power
List of Parameters
Table 7
Symbol
(continued) Configurable parameters for protections
Example
Minimum
value
Maximum
value
tVoutOV,blank,ABM Output overvoltage protection blanking time in
ABM
0.5 ms
0.2 ms
5.0 ms
ENadaptive,OVP,Vo Enable switch for adaptive output overvoltage
protection level
ut
Enabled
Enabled
Disabled
VoutOV,red
Output overvoltage protection level applied
during auto-restart when the last triggered
protection is output overvoltage protection with
ENadaptive,OVP,Vout enabled.
51.3 V
Vout,dim,min
VoutOV
Iout,OVP,red
Output current set point max. limit applied
during auto-restart when the last triggered
protection is output overvoltage protection with
ENadaptive,OVP,Vout enabled.
41.5 mA
Iout,min
Iout,full
NVout, restore
Blanking time for output voltage below VoutOV,red
to exit output overvoltage protection with
ENadaptive,OVP,Vout enabled.
500
0
5000
tVoutUV,blank
Blanking time for regulated mode output
undervoltage protection
40 ms
40 ms
1000 ms
ENIout,max,peak
Enable switch for peak output overcurrent
protection
Enabled
Enabled
Disabled
Iout,max,peak
Peak output overcurrent protection level
2100 mA
Refer GUI
Refer GUI
tIout,max,peak,bla Blanking time for peak output overcurrent
protection
nk
1 ms
0 ms
5 ms
SpeedOCP,Iout
Auto-restart speed for peak output overcurrent
protection
Fast
Slow
Fast
ENOVP,In
Enable switch for maximum input voltage startup
check and input overvoltage protection
Enabled
Enabled
Disabled
ENUVP,In
Enable switch for minimum input voltage startup
check and input undervoltage protection
Enabled
Enabled
Disabled
VinOV
Input overvoltage protection level (rms in case of
AC input)
352 Vrms
Vin,start,max
Refer GUI
Vin,start,max
Maximum input voltage level at startup (rms in
case of AC input)
326 Vrms
Vin,start,min
VinOV
Vin,start,min
Minimum input voltage level at startup (rms in
case of AC input)
80 Vrms
VinUV
Refer GUI
VinUV
Input undervoltage protection level (rms in case of 63 Vrms
AC input)
Refer GUI
Vin,start,min
Tcritical
Temperature threshold for IC overtemperature
protection
119°C
Refer GUI
143°C
DebugMode
Enable switch for debug mode
Disabled
Enabled
Disabled
Datasheet
Basic description
30
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XDP™ Digital Power
List of Parameters
Table 8
Configurable parameters for multimode
Symbol
Basic description
Example
Minimum
value
Maximum
value
fsw,max
Maximum switching frequency for QRM1 and DCM
70 kHz
20 kHz
Refer GUI
NDCM,mod,gain
Switching period modulation attenuation
16
0 (disabled), 4, 8, 16, 32
ton,min
Minimum on-time ton,min(Vin) value when
ton,min,V,out,sense(Vin) is lower than ton,min
2 µs
Refer GUI
ton,max
tmin,demag
Minimum transformer demagnetizing time value
used for ton,min,V,out,sense(Vin) variable calculation
internally
3 µs
3 µs
Refer GUI
ton,max
Maximum on-time
11.5 µs
Refer GUI
30 µs
fsw,min,DCM
Minimum switching frequency in DCM
20 kHz
Refer GUI
20 kHz
ENABM
Enable switch for ABM
Enabled
Enabled
Disabled
NABM,min
Minimum number of pulses per burst
11
4
Refer GUI
NABM,init,VinUV
Initial number of pulses per burst when ENABM
is enabled and Vin is near to input undervoltage
protection level VinUV
132
NABM,min
Refer GUI
Vin,high
Input voltage level which when exceeded, the
initial number of pulses per burst is fixed as
NABM,min if ENABM is enabled
277 Vrms
Vin,start,min
VinOV
Table 9
Configurable parameters for control loop response
Symbol
Basic description
Example
Minimum
value
Maximum
value
KP,QRM
Proportional gain of control loop in QRM1
512
10
3000
KI,QRM
Integral gain of control loop in QRM1
32
1
1000
KP,DCM
Proportional gain of control loop in DCM
2048
100
30000
KI,DCM
Integral gain of control loop in DCM
512
10
10000
KP,ABM
Proportional gain of control loop in ABM
128
1
600
KI,ABM
Integral gain of control loop in ABM
32
1
200
3
0
10
ABMthrs,multiplie Minimum set-point error threshold multiplier to
activate control loop response in ABM
r
Table 10
Parameters for power factor correction
Symbol
Basic description
Example
Minimum
value
Maximum
value
CEMI
Input current displacement compensation gain
parameter for enhanced PFC
0.1 µF
0 µF
1 µF
Example
Minimum
value
Maximum
value
270 ns
0 ns
1000 ns
Table 11
Symbol
Configurable parameters for fine tuning
Basic description
tZCD,PD
ZCD pin propagation delay compensation
parameter
(table continues...)
Datasheet
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XDP™ Digital Power
List of Parameters
Table 11
(continued) Configurable parameters for fine tuning
Symbol
Basic description
tzcddel
Minimum
value
Maximum
value
Rising edge delay of ZCD signal after gated turn off 380 ns
0 ns
1000 ns
tPDC
CS pin propagation delay compensation parameter 200 ns
0 ns
1000 ns
Kcoupling
Transformer coupling coefficient parameter
0.96
0
2
Gout,loss
Auxiliary loss compensation parameter
11.9 Ω
0 mS
2 mS
Rin
DC link filter capacitor voltage ripple
11.0 Ω
compensation parameter to improve input voltage
estimation accuracy
0Ω
30 Ω
Table 12
Example
Configurable parameter for user ID
Symbol
Basic description
Example
Minimum
value
Maximum
value
UserID,A
User ID A
1018
0
65535
List of fixed parameters
Table 13
Fixed parameters for hardware configuration
Symbol
Basic description
Default
Minimum
value
Maximum
value
Lp,lk
Transformer primary leakage inductance
1% of Lp
-
-
Vd
Secondary main output diode forward voltage
assumption for output voltage estimation
0.7 V
-
-
VGD
GD pin peak voltage
12 V
-
-
Minimum
value
Maximum
value
Table 14
Fixed parameter for startup
Symbol
Basic description
Default
tss
Soft start time step
0.5 ms or 3.2/tss,
whichever
is lower
-
Maximum
value
Table 15
Fixed parameters for protections
Symbol
Basic description
Default
VoutUV
Regulated mode output undervoltage protection
level
Vout,dim,min /2
-
VVCC,max
VCC overvoltage protection level
24 V
-
-
Tstart,max
Maximum IC junction temperature for startup
Tcritical-4°C -
-
tblank,Vin,OV
Blanking time for input overvoltage threshold
1/(2fline)
-
-
tblank,Vin,UV
Blanking time for input undervoltage threshold
10/(2fline)
-
-
Datasheet
32
Minimum
value
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XDP™ Digital Power
List of Parameters
Table 16
Fixed parameters for multimode
Symbol
Basic description
Default
Minimum
value
Maximum
value
fsw,min,QRM
Minimum switching frequency in QRM1
20 kHz
-
-
fDCM,init,VinUV
Initial DCM switching frequency when ENABM is
disabled and Vin is near to input undervoltage
protection level VinUV
20 kHz
-
-
Table 17
Other fixed parameters
Symbol
Basic description
Default
Minimum
value
Maximum
value
tCS,LEB
CS leading edge blanking time
480 ns
-
-
tCSOCP2
MOSFET overcurrent protection blanking time
240 ns
-
-
tZCD,ring
ZCD ringing suppression
1200 ns
-
-
tblank,CCM
Blanking time for protection
10 ms
-
-
tpw
Discharge pulse duration
1.5 µs
-
-
Datasheet
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XDP™ Digital Power
Electrical Characteristics and Parameters
6
Electrical Characteristics and Parameters
All signals are measured with respect to the ground pin, GND. The voltage levels are valid provided other ratings
are not violated.
6.1
Package Characteristics
Table 18
Package Characteristics
Parameter
Symbol
Thermal resistance for PGDSO-8-58
6.2
RthJA
Limit Values
min
max
—
178
Unit
Remarks
K/W
JEDEC 1s0p for 140 mW
power dissipation
Absolute Maximum Ratings
Attention: Stresses above the values listed below may cause permanent damage to the device. Exposure
to absolute maximum rating conditions for extended periods may affect device reliability.
Maximum ratings are absolute ratings; exceeding only one of these values may cause
irreversible damage to the integrated circuit. These values are not tested during production
test.
Table 19
Absolute Maximum Ratings
Parameter
Symbol
Limit Values
min
max
Unit
Remarks
Voltage externally supplied
to pin VCC
VVCCEXT
–0.5
26
V
voltage that can be applied
to pin VCC by an external
voltage source
Voltage at pin GDx
VGDx
–0.5
VVCC + 0.3
V
if gate driver is not
configured for digital I/O
Junction temperature
TJ
–40
125
°C
max. operating frequency
66 MHz fMCLK
Junction temperature
TJ
–40
1501)
°C
fsw,max ≤ 136 kHz
Storage temperature
TS
–55
150
°C
Soldering temperature
TSOLD
—
260
°C
Wave Soldering 2)
Latch-up capability
ILU
—
150
mA
3) Pin voltages acc. to abs.
ESD capability HBM
VHBM
—
1500
V
4)5)
ESD capability CDM
(table continues...)
VCDM
—
500
V
6)
1
2
3
4
5
6
max. ratings
Auto-restart may be delayed at low input voltage condition when junction temperature is above 125°C.
The lifetime is not guaranteed when IC operating junction temperature is above 125°C.
According to JESD22-A111 Rev A.
Latch-up capability according to JEDEC JESD78D, TA= 85°C.
ESD-HBM according to ANSI/ESDA/JEDEC JS-001-2012.
product resp. package specific rating up to 2000 V
ESD-CDM according to JESD22-C101F.
Datasheet
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XDPL8210 Digital Flyback Controller IC
XDP™ Digital Power
Electrical Characteristics and Parameters
Table 19
(continued) Absolute Maximum Ratings
Parameter
Symbol
Limit Values
min
max
Unit
Remarks
Input Voltage Limit
VIN
–0.5
3.6
V
Voltage externally supplied
to pins GPIO, MFIO, CS, ZCD,
GPIO, VS, GDx (if GDx is
configured as digital I/O). (If
not stated different)
Maximum permanent
negative clamping current
for ZCD and CS
–ICLN_DC
—
2.5
mA
RMS
Maximum transient negative –ICLN_TR
clamping current for ZCD
and CS
—
10
mA
pulse < 500ns
Maximum negative transient –VIN_ZCD
input voltage for ZCD
—
1.5
V
pulse < 500ns
Maximum negative transient –VIN_CS
input voltage for CS
—
3.0
V
pulse < 500ns
Maximum permanent
ICLP_DC
positive clamping current for
CS
—
2.5
mA
RMS
Maximum transient positive
clamping current for CS
ICLP_TR
—
10
mA
pulse < 500ns
Maximum current into pin
VIN
IAC
—
10
mA
for charging operation
Maximum sum of input
ICLH_sum
clamping high currents for
digital input stages of device
—
300
µA
limits for each individual
digital input stage have to
be respected
Voltage at HV pin
-0.5
600
V
6.3
VHV
Operating conditions
The recommended operating conditions are shown for which the DC Electrical Characteristics are valid.
Table 20
Operating range
Parameter
Symbol
Limit Values
Unit
min
max
Remarks
Ambient temperature
TA
–40
85
°C
Junction Temperature
TJ
–40
125
°C
max. 66 MHz fMCLK
Lower VCC limit
VVCC
VUVOFF
—
V
device is held in reset when
VVCC < VUVOFF
Voltage externally supplied
to VCC pin
VVCCEXT
—
24
V
maximum voltage that can
be applied to pin VCC by an
external voltage source
Gate driver pin voltage
VGD
–0.5
VVCC + 0.3
V
Line frequency
fline
45
66
Hz
Datasheet
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XDP™ Digital Power
Electrical Characteristics and Parameters
6.4
DC Electrical characteristics
The electrical characteristics provide the spread of values applicable within the specified supply voltage and
junction temperature range, TJ from -40 °C to +125 °C.
Devices are tested in production at TA = 25 °C. Values have been verified either with simulation models or by
device characterization up to 125 °C.
Typical values represent the median values related to TA = 25 °C. All voltages refer to GND, and the assumed
supply voltage is VVCC = 18 V if not otherwise specified.
Note:
Not all values given in the tables are tested during production testing. Values not tested are explicitly
marked.
Table 21
Power supply characteristics
Parameter
Symbol
Values
Min.
VCC_ON threshold
VVCCon
Unit Note or Test Condition
Typ.
Max.
—
VSELF
—
V
Self-powered startup
(default)
VCC_ON_SELF threshold VSELF
19
20.5
22
V
dVVCC/dt = 0.2 V/ms
VCC_ON_SELF delay
tSELF
—
—
2.1
µs
Reaction time of VVCC
monitor
VCC_UVOFF current
IVCCUVOFF
5
20
40
µA
VVCC < VSELF(min) - 0.3 V
or VVCC < VEXT(min) 0.3 V7)
UVOFF threshold
VUVOFF
—
6.0
—
V
SYS_CFG0.SELUVTHR = 0
0B
UVOFF threshold
tolerance
ΔUVOFF
—
—
±5
%
This value defines the
tolerance of VUVOFF
UVOFF filter constant
tUVOFF
600
—
—
ns
1V overdrive
UVLO (UVWAKE)
threshold
VUVLO
—
VUVOFF ·
1.25
—
V
UVWAKE threshold
tolerance
ΔUVLO
—
—
±5
%
This value defines the
tolerance of VUVLO
UVLO (UVWAKE) filter
constant
tUVLO
0.6
—
2.2
µs
1 V overdrive
OVLO (OVWAKE)
threshold
VOVLO
—
VSELF
—
V
OVLO (OVWAKE) filter
constant
tOVLO
0.6
—
2.4
µs
1 V overdrive
VDDP voltage
VVDDP
3.04
3.20
3.36
V
At PMD0/PSMD1. Some
internal values refer
to VVDDP / VVDDA
and VVDDPPS / VVDDAPS
respectively.
(table continues...)
7
Tested at VVCC = 5.5 V
Datasheet
36
Revision 1.1
2021-06-25
XDPL8210 Digital Flyback Controller IC
XDP™ Digital Power
Electrical Characteristics and Parameters
Table 21
(continued) Power supply characteristics
Parameter
Symbol
Values
Min.
Unit Note or Test Condition
Typ.
Max.
VDDA voltage
VVDDA
3.20
3.31
3.42
V
At PMD0/PSMD1. Some
internal values refer
to VVDDP / VVDDA
and VVDDPPS / VVDDAPS
respectively.
Nominal range 0% to
100%
VADCVCC
0
—
VREF
V
VADCVCC = 0.09 · VVCC8)
Reduced VCC range for
ADC measurement
RADCVCC
8
—
92
%
9)10)
Maximum error for
ADC measurement (8-bit
result)
TET0VCC
—
—
3.8
LSB8
Maximum error for
ADC measurement (8-bit
result)
TET256VCC
—
—
5.2
LSB8
Gate driver current
consumption excl. gate
charge current
IVCCGD
—
0.26
0.35
mA
Tj ≤ 125°C
VCC quiescent current in
PMD0
IVCCPMD0
—
3.5
4.7
mA
All registers have reset
values, clock is active,
CPU is stopped
VCC quiescent current in
PSMD2
IVCCPSMD2
—
0.3
0.48
mA
Tj ≤ 85 °CWU_PWD_CFG
= 2CH
VCC quiescent current in
PSMD2
IVCCPSMD2
—
—
1.2
mA
Tj ≤ 125 °CWU_PWD_CFG
= 2CH
VCC quiescent current
in power saving mode
PSDM4 with standby
logic active
IVCCPSMD4
—
0.13
0.18
mA
Tj ≤ 125 °C
WU_PWD_CFG = 00H
Table 22
Electrical characteristics of the GD pin
Parameter
Symbol
Values
Min.
Typ.
Unit Note or Test Condition
Max.
Input clamping current,
low
–ICLL
—
—
100
µA
only digital input
Input clamping current,
high
ICLH
—
—
100
µA
only digital input
(table continues...)
8
9
10
Theoretical minimum value, real minimum value is related to VUVOFF threshold.
Operational values.
Note that the system is turned off if VVCC < VUFOFF.
Datasheet
37
Revision 1.1
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XDPL8210 Digital Flyback Controller IC
XDP™ Digital Power
Electrical Characteristics and Parameters
Table 22
(continued) Electrical characteristics of the GD pin
Parameter
Symbol
Values
Min.
Unit Note or Test Condition
Typ.
Max.
APD low voltage (active
pull-down while device
is not powered or gate
driver is not enabled)
VAPD
—
—
1.6
V
IGD = 5 mA
RPPD value
RPPD
—
600
—
kΩ
Permanent pull-down
resistor inside gate
driver
RPPD tolerance
ΔPPD
—
—
±25
%
Permanent pull-down
resistor inside gate
driver
Driver output low
impedance
RGDL
—
—
7.0
Ω
TJ ≤ 125 °C, IGD = 0.1 A
Nominal output high
voltage in PWM mode
VGDH
—
12
—
V
GDx_CFG.VOL = 2,
IGDH = –1 mA
Output voltage tolerance ΔVGDH
—
—
±5
%
Tolerance of
programming options if
VGDH > 10 V, IGDH = –1 mA
Rail-to-rail output high
voltage
VGDHRR
VVCC– 0.5
—
VVCC
V
If VVCC < programmed
VGDH and output at high
state
Output high current in
PWM mode for GD0
–IGDH
—
100
—
mA
GDx_CFG.CUR = 8
Output high current
tolerance in PWM mode
ΔIGDH
—
±15
%
Calibrated 11)
Discharge current for
GD0
IGDDIS
800
—
—
mA
VGD = 4 V and driver at
low state
Output low reverse
current
–IGDREVL
—
—
100
mA
Applies if VGD < 0 V and
driver at low state
Output high reverse
current in PWM mode
IGDREVH
—
1/6 of IGDH
—
Table 23
Applies if
VGD > VGDH + 0.5 V (typ)
and driver at high state
Electrical characteristics of the CS pin
Parameter
Symbol
Values
Min.
Input voltage operating
range
VINP
–0.5
Unit Note or Test Condition
Typ.
—
Max.
3.0
V
(table continues...)
11
referred to GDx_CFG.CUR = 16
Datasheet
38
Revision 1.1
2021-06-25
XDPL8210 Digital Flyback Controller IC
XDP™ Digital Power
Electrical Characteristics and Parameters
Table 23
(continued) Electrical characteristics of the CS pin
Parameter
Symbol
Values
Min.
Unit Note or Test Condition
Typ.
Max.
OCP2 comparator
reference voltage,
derived from VVDDA,
given values assuming
VVDDA = VVDDA,typ
VOCP2
—
1.6
—
V
SYS_CFG0.OCP2 = 00B
OCP2 comparator
reference voltage,
derived from VVDDA,
given values assuming
VVDDA = VVDDA,typ
VOCP2
—
1.2
—
V
SYS_CFG0.OCP2 = 01B
OCP2 comparator
reference voltage,
derived from VVDDA,
given values assuming
VVDDA = VVDDA,typ
VOCP2
—
0.8
—
V
SYS_CFG0.OCP2 = 10B
OCP2 comparator
reference voltage,
derived from VVDDA,
given values assuming
VVDDA = VVDDA,typ
VOCP2
—
0.6
—
V
SYS_CFG0.OCP2 = 11B
Threshold voltage
tolerance
ΔVOCP2
—
—
±5
%
Voltage divider tolerance
Comparator propagation tOCP2PD
delay
15
—
35
ns
Minimum comparator
input pulse width
tOCP2PW
—
—
30
ns
OCP2F comparator
propagation delay
tOCP2FPD
70
—
170
ns
dVCS/dt = 100 V/µs
Delay from VCS crossing
VCSOCP2 to begin of GDx
turn-off (IGD0 > 2mA)
tCSGDxOCP2
125
135
190
ns
dVCS/dt = 100 V/µs;
fMCLK = 66 MHz. GDx
driven by QR_GATE
FIL_OCP2.STABLE = 3
OCP1 operating range
VOCP1
0
—
VREF/2
V
RANGE =00B
OCP1 threshold at
full scale setting
(CS_OCP1LVL=FFH)
VOCP1FS
1187
1209
1243
mV
RANGE =00B
Delay from VCS crossing
VCSOCP1 to CS_OCP1
rising edge, 1.2 V range
tCSOCP1
90
170
250
ns
Input signal slope dVCS/
dt = 150 mV/µs. This
slope represents a use
case of a switch-mode
power supply with
minimum input voltage.
(table continues...)
Datasheet
39
Revision 1.1
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XDPL8210 Digital Flyback Controller IC
XDP™ Digital Power
Electrical Characteristics and Parameters
Table 23
(continued) Electrical characteristics of the CS pin
Parameter
Symbol
Values
Min.
Unit Note or Test Condition
Typ.
Max.
Delay from CS_OCP1
rising edge to QR_GATE
falling edge
tOCP1GATE
—
—
130
ns
Delay from QR_GATE
falling edge to start of
GDx turn-off
tGATEGDx
1
3
5
ns
GDx driven by QR_GATE.
Measured up to
IGDx > 2 mA
OCP1 comparator input
single pulse width filter
tOCP1PW
60
—
95
ns
Shorter pulses than min.
are suppressed, longer
pulses than max. are
passed
Nominal S&H operating
range 0% to 100%
VCSH
0
—
VREF/2
V
CS_ICR.RANGE =00B
Reduced S&H operating
range
RRCVSH
8
—
92
%
CS_ICR.RANGE =00B
Operational values
Maximum error of
CS0 S&H for corrected
measurement (8-bit
result)
TET0CS0S
—
—
4.7
LSB
CS_ICR.RANGE =00B
Maximum error of
CS0 S&H for corrected
measurement (8-bit
result)
TET256CS0S —
—
6.0
LSB
CS_ICR.RANGE =00B
Nominal S&H operating
range 0% to 100%
VCSH
0
—
VREF/6
V
CS_ICR.RANGE =11B
Reduced S&H operating
range
RRCVSH
20
—
80
%
CS_ICR.RANGE =11B
Operational values
Maximum error of
CS0 S&H for corrected
measurement (8-bit
result)
TET0CS0S
—
—
8.0
LSB
CS_ICR.RANGE =11B
Maximum error of
CS0 S&H for corrected
measurement (8-bit
result)
TET256CS0S —
—
8.7
LSB
CS_ICR.RANGE =11B
—
510
ns
Referring to jump in
input voltage. Limits the
minimum gate driver Ton
time.
S&H delay of input buffer tCSHST
Datasheet
—
40
Revision 1.1
2021-06-25
XDPL8210 Digital Flyback Controller IC
XDP™ Digital Power
Electrical Characteristics and Parameters
Table 24
Electrical characteristics of the ZCD pin
Parameter
Symbol
Values
Min.
Unit Note or Test Condition
Typ.
Max.
Input voltage operating
range
VINP
–0.5
—
3.3
V
Input clamping current,
high
ICLH
—
—
100
µA
Zero-crossing threshold
VZCTHR
15
40
70
mV
Comparator propagation tZCPD
delay
30
50
70
ns
dVZCD/dt = 4 V/µs
Input voltage negative
clamping level
–VINPCLN
140
180
220
mV
Analog clamp activated
Nominal I/V-conversion
operating range 0% to
100%
–IIV
0
—
0.5
mA
CRNG =11BGain = 4800
mV/mA
Nominal I/V-conversion
operating range 0% to
100%
–IIV
0
—
1
mA
CRNG =10BGain = 2400
mV/mA
Nominal I/V-conversion
operating range 0% to
100%
–IIV
0
—
2
mA
CRNG =01BGain = 1200
mV/mA
Nominal I/V-conversion
operating range 0% to
100%
–IIV
0
—
4
mA
CRNG =00B Gain = 600
mV/mA
Reduced I/V-conversion
operating range
RRIV
5
—
80
%
Maximum error
for corrected ADC
measurement (8-bit
result)
TET0IV
—
—
4.1
LSB8 CRNG =00B
Maximum error
for corrected ADC
measurement (8-bit
result)
TET256IV
—
—
9.7
LSB8 CRNG =00B
Maximum deviation
between ZCD clamp
voltage and trim result
stored in OTP
EZCDClp
—
—
±5
%
–IIV > 0.25 mA
IV-conversion delay of
input buffer
tIVST
—
—
900
ns
Refers to jump in input
current12)
(table continues...)
12
Limits the minimum gate driver Ton time.
Datasheet
41
Revision 1.1
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XDPL8210 Digital Flyback Controller IC
XDP™ Digital Power
Electrical Characteristics and Parameters
Table 24
(continued) Electrical characteristics of the ZCD pin
Parameter
Symbol
Values
Min.
Unit Note or Test Condition
Typ.
Max.
Nominal S&H input
voltage range 0% to
100%
VZSH
0
—
2/3 · VREF
V
SHRNG =0B
Nominal S&H input
voltage range 0% to
100%
VZSH
VREF /2
—
7/6 · VREF
V
SHRNG =1B
Reduced S&H input
voltage range
RRZVSH
4
—
95
%
Maximum error
for corrected ADC
measurement (8-bit
result)
TET0ZVS0
—
—
3.7
LSB8 SHRNG =0B
Maximum error
for corrected ADC
measurement (8-bit
result)
TET256ZVS0 —
—
4.9
LSB8 SHRNG =0B
Maximum error
for corrected ADC
measurement (8-bit
result)
TET0ZVS1
—
—
4.2
LSB8 SHRNG =1B
Maximum error
for corrected ADC
measurement (8-bit
result)
TET256ZVS1 —
—
5.8
LSB8 SHRNG =1B
S&H delay of input buffer tZSHST
referring to jump of input
voltage
—
—
1.0
µs
SHRNG =0BTj ≤ 125 °C
S&H delay of input buffer tZSHST
referring to jump of input
voltage
—
—
1.6
µs
SHRNG =1BTj ≤ 125 °C
Table 25
Electrical characteristics of the HV pin
Parameter
Symbol
Values
Min.
Unit Note or Test Condition
Typ.
Max.
Current for VCC cap
charging
ILD
3.0
5
7.5
mA
VHV = 30 V; VVCC < VVCCon –
0.3 V; Tj ≥ 0°C
Current for VCC cap
charging
ILD
2.4
5
7.5
mA
VHV = 30 V; VVCC < VVCCon –
0.3 V;-25°C < Tj < 0°C
Current for VCC cap
charging
ILD
2.0
5
7.5
mA
VHV = 30 V; VVCC < VVCCon –
0.3 V;Tj < -25°C
(table continues...)
Datasheet
42
Revision 1.1
2021-06-25
XDPL8210 Digital Flyback Controller IC
XDP™ Digital Power
Electrical Characteristics and Parameters
Table 25
(continued) Electrical characteristics of the HV pin
Parameter
Symbol
Values
Min.
Unit Note or Test Condition
Typ.
Max.
Nominal current for
IMEAS
measurement path 0% to
100%
0
—
9.6
mA
CURRNG = 11B
Nominal current for
IMEAS
measurement path 0% to
100%
0
—
4.8
mA
CURRNG = 10B
Nominal current for
IMEAS
measurement path 0% to
100%
0
—
1.6
mA
CURRNG = 01B
Comparator threshold (in THRCOMP
% of full range of IMEAS)
15
20
25
%
COMPTHR= 00B
Comparator threshold (in THRCOMP
% of full range of IMEAS)
25
30
35
%
COMPTHR= 01B
Comparator threshold (in THRCOMP
% of full range of IMEAS)
45
50
55
%
COMPTHR= 11B
Table 26
Electrical characteristics of the PWM pin
Parameter
Symbol
Values
Min.
Unit Note or Test Condition
Typ.
Max.
MFIO reference voltage
VMFIOREF
—
VVDDP
—
V
Input low voltage
VIL
—
—
1.0
V
Input high voltage
VIH
2.0
—
—
V
Pull-up resistor tolerance ΔRPU
—
—
±20
%
PWM frequency
500
—
2000
Hz
Table 27
fPWM
Selection = VVDDP, not
power down
Overall tolerance
Electrical characteristics of the UART pin
Parameter
Symbol
Values
Min.
Unit Note or Test Condition
Typ.
Max.
Input clamping current,
low
–ICLL
—
—
100
µA
only digital input
Input clamping current,
high
ICLH
—
—
100
µA
only digital input
Input capacitance
CINPUT
—
—
25
pF
Input low voltage
VIL
—
—
1.0
V
Input high voltage
VIH
2.1
—
—
V
30
—
90
µA
Input low current with
–ILPU
active weak pull-up WPU
(table continues...)
Datasheet
43
Measured at max. VIL
Revision 1.1
2021-06-25
XDPL8210 Digital Flyback Controller IC
XDP™ Digital Power
Electrical Characteristics and Parameters
Table 27
(continued) Electrical characteristics of the UART pin
Parameter
Symbol
Values
Min.
Unit Note or Test Condition
Typ.
Max.
Max. input frequency
fINPUT
15
—
—
MHz
Output low voltage
VOL
—
—
0.8
V
IOL = 2 mA
Output high voltage
VOH
2.4
—
—
V
IOH = –2 mA
Output sink current
IOL
—
—
2
mA
Output source current
-IOH
—
—
2
mA
Output rise time (0 → 1)
tRISE
—
—
50
ns
20 pF load, push/pull
output
Output fall time (1 → 0)
tFALL
—
—
50
ns
20 pF load, push/pull or
open-drain output
Max. output switching
frequency
fSWITCH
10
—
—
MHz
UART baudrate
fUART
-10%
57600
+10%
baud
Table 28
Electrical characteristics of the A/D converter
Parameter
Symbol
Values
Min.
Integral non-linearity
Table 29
INL
—
Unit Note or Test Condition
Typ.
—
Max.
1
LSB8
Electrical characteristics of the reference voltage
Parameter
Symbol
Values
Min.
Unit Note or Test Condition
Typ.
Max.
Reference voltage
VREF
—
2.428
—
V
VREF overall tolerance
ΔVREF
—
—
±1.5
%
Table 30
Parameter
13)
Trimmed, Tj ≤ 125 °C and
aging
Electrical characteristics of the OTP programming
Symbol
Values
Min.
Unit Note or Test Condition
Typ.
Max.
OTP programming
VPP
voltage at the VCC pin for
range C000H to CFFFH
7.35
7.5
7.65
V
Operational values
OTP programming
current
—
1.6
—
mA
Programming of 4 bits in
parallel
13
IPP
ADC capability measured via channel MFIO without errors due to switching of neighbouring pins, e.g. gate
drivers, measured with STC = 5. MFIO buffer non-linearity masked out by taking ADC output values ≥ 30
only.
Datasheet
44
Revision 1.1
2021-06-25
XDPL8210 Digital Flyback Controller IC
XDP™ Digital Power
Electrical Characteristics and Parameters
Table 31
Electrical characteristics of the clock oscillators
Parameter
Symbol
Values
Min.
Unit Note or Test Condition
Typ.
Max.
Master clock oscillation
period including all
variations
tMCLK
15.0
15.8
16.6
ns
In reference to 66 MHz
fMCLK
Main clock oscillator
frequency variation
of stored DPARAM
frequency
ΔMCLK
–3.2
—
+3.5
%
Temperature drift and
aging only, 66 MHz fMCLK
Standby clock oscillator
frequency
fSTBCLK
96
100
104
kHz
Trimming tolerance at
TA = 25 °C
Standby clock oscillator
frequency
fSTBCLK
90
100
110
kHz
Overall tolerance, Tj ≤
125 °C
Table 32
Electrical characteristics of the temperature sensor
Parameter
Symbol
Values
Min.
Unit Note or Test Condition
Typ.
Max.
Temperature sensor ADC ADCTEMP
output operating range
0
—
190
LSB
ADCTEMP = 40 +
temperature / °C)
Temperature sensor
tolerance
—
—
±6
K
Incl. ADC conversion
accuracy at 3 σ
Datasheet
ΔTEMP
45
Revision 1.1
2021-06-25
XDPL8210 Digital Flyback Controller IC
XDP™ Digital Power
Package dimensions
7
Package dimensions
The package dimensions of PG-DSO-8 are provided.
Figure 25
Datasheet
Package dimensions for PG-DSO-8
46
Revision 1.1
2021-06-25
XDPL8210 Digital Flyback Controller IC
XDP™ Digital Power
Package dimensions
Figure 26
Note:
Datasheet
Tape and reel for PG-DSO-8
You can find all of our packages, packing types and other package information on our Infineon
Internet page “Products”: http://www.infineon.com/products.
47
Revision 1.1
2021-06-25
XDPL8210 Digital Flyback Controller IC
XDP™ Digital Power
References
8
1.
2.
3.
4.
5.
6.
7.
References
Infineon Technologies AG: XDPL8210 Design Guide
Infineon Technologies AG: XDPL8210 CDM10VD 35 W reference design with IPN80R900P7
Infineon Technologies AG: CoolMOS P7 power MOSFETs, http://www.infineon.com/P7
Infineon Technologies AG: .dp Vision User Manual
Infineon Technologies AG: .dp Interface Gen2 which can be ordered at https://
www.infineon.com/cms/en/product/evaluation-boards/if-board.dp-gen2/
Infineon Technologies AG: .dp Interface Gen2 User Manual
Infineon Technologies AG: XDP Programming Manual
Revision History
Major changes since previous revision
Revision History
Revision
Description
1.1
•
•
•
•
•
•
1.0
Initial release
Remove DC input related text
Update .dp Interface Gen2 ordering link
Remove DDIM,max from list of fixed parameters
Add DDIM,max, fPWM,max and fPWM,min to list of configurable parameters
Change maximum value of configurable parameter DDIM,min
Change minimum value of configurable parameter DDIM,off
Glossary
ABM
Active Burst Mode (ABM)
Active Burst Mode is an operating mode of a switched-mode power supply for very light load conditions. The
controller switches in bursts of pulses with a pause between bursts in which no switching is done.
CC
Constant Current (CC)
Constant Current is a mode of a power supply in which the output current is kept constant regardless of the
load.
CRC
Cyclic Redundancy Check
A cyclic redundancy check is an error-detecting code commonly used to detect accidental changes to raw data.
DCM
Discontinuous Conduction Mode (DCM)
Discontinuous Conduction Mode is an operational mode of a switching power supply in which the current starts
and returns to zero.
Datasheet
48
Revision 1.1
2021-06-25
XDPL8210 Digital Flyback Controller IC
XDP™ Digital Power
Glossary
ECG
Electronic Control Gear (ECG)
An electronic control gear is a power supply which provides one or more light module(s) with the appropriate
voltage or current.
EMI
Electro-Magnetic Interference (EMI)
Also called Radio Frequency Interference (RFI), this is a (usually undesirable) disturbance that affects an
electrical circuit due to electromagnetic radiation emitted from an external source. The disturbance may
interrupt, obstruct, or otherwise degrade or limit the effective performance of the circuit.
FB
Flyback (FB)
A flyback converter is a power converter with the inductor split to form a transformer, so that the voltage ratios
are multiplied with an additional advantage of galvanic isolation between the input and any outputs.
GUI
Graphic User Interface
A graphical user interface is a type of interface that allows users to interact with electronic devices through
graphical icons and visual indicators.
IC
Integrated Circuit (IC)
A miniaturized electronic circuit that has been manufactured in the surface of a thin substrate of semiconductor
material. An IC may also be referred to as micro-circuit, microchip, silicon chip, or chip.
LED
Light Emitting Diode (LED)
A light-emitting diode is a two-lead semiconductor light source which emits light when activated.
LP
Limited Power (LP)
Limited Power is a mode of a power supply in which the output power is limited regardless of the load.
MCU
Microcontroller Unit (MCU)
A microcontroller is a small computer on a single integrated circuit containing a processor core, memory, and
programmable input/output peripherals.
PC
Personal Computer
A personal computer is a general-purpose computer whose size, capabilities, and original sale price make
it useful for individuals, and which is intended to be operated directly by an end-user with no intervening
computer time-sharing models that allowed larger, more expensive minicomputer and mainframe systems to
be used by many people, usually at the same time.
PFC
Power Factor Correction (PFC)
Power factor correction increases the power factor of an AC power circuit closer to 1 which corresponds to
minimizing the reactive power of the power circuit.
Datasheet
49
Revision 1.1
2021-06-25
XDPL8210 Digital Flyback Controller IC
XDP™ Digital Power
Glossary
PF
Power Factor (PF)
Power factor is the ratio between the real power and the apparent power.
PWM
Pulse Width Modulation (PWM)
Pulse-width modulation is a technique to encode an analog value into the duty cycle of a pulsing signal with
arbitrary amplitude.
QRM1
Quasi-Resonant Mode, switching in first valley (QRM1)
Quasi-Resonant Mode is an operating mode of a switched-mode power supply which maximizes efficiency. This
is achieved by switching at the occurrence of the first valley of a signal which corresponds to a time when
switching losses are low.
THD
Total Harmonic Distortion (THD)
The total harmonic distortion of a signal is a measurement of the harmonic distortion present and is defined as
the ratio of the sum of the powers of all harmonic components to the power of the fundamental frequency.
UART
Universal Asynchronous Receiver Transmitter
A universal asynchronous receiver transmitter is used for serial communications over a peripheral device serial
port by translating data between parallel and serial forms.
USB
Universal Serial Bus
Universal Serial Bus is an industry standard that defines cables, connectors and communications protocols
used in a bus for connection, communication, and power supply between computers and electronic devices.
UVLO
Undervoltage Lockout (UVLO)
The Undervoltage-Lockout is an electronic circuit used to turn off the power of an electronic device in the event
of the voltage dropping below the operational value.
Datasheet
50
Revision 1.1
2021-06-25
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Edition 2021-06-25
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