XDPL8220XUMA1

XDPL8220 Digital PFC+Flyback Controller IC XDP™ Digital Power Data Sheet Revision 1.0 Quality Requirement Category: Industrial Features • • • • • Universal AC input (90 - 305 VAC) or DC input (90 - 305 VDC) Applicable power range of 20 W to 150 W Small number of external parts optimizes Bill of Materials (BOM) and form factor High efficiency (> 90%) Multicontrol mode (Constant Current (CC)/Constant Voltage (CV)/Limited Power (LP)) reduces required product variety • Important parameters can be configured after manufacturing • Low harmonic distortion (Total Harmonic Distortion (THD) < 15%) • Low output ripple current • Integrated startup cell ensures fast time to light (< 250 ms) • Adaptive Temperature Protection • Ambient operating temperature -40 °C to 85 °C • Automatic switching between Quasi-Resonant Mode (QRM) and Discontinuous Conduction Mode (DCM) • Wide output voltage range • Pulse Width Modulation (PWM) dimming control • Output dimming by analog reduction of driving current down to 5% For safe operation, the XDPL8220 contains a comprehensive set of protection features: • Output overvoltage protection (open load) • Output undervoltage protection (output short) • VCC over- and undervoltage lockout • Input over- and undervoltage protection • Bus over- and undervoltage protection • Overcurrent protection for Power Factor Correction (PFC) and Flyback (FB) stage Applications • Integrated Electronic Control Gear (ECG) for Light Emitting Diode (LED) luminaires Data Sheet www.infineon.com Please read the Important Notice and Warnings at the end of this document Revision 1.0 2016-11-4 XDPL8220 Digital PFC+Flyback Controller IC XDP™ Digital Power Description L Input voltage GDPFC LED+ CSPFC GDFB N TEMP CSFB LED- XDPL8220 HV VCC VS ZCD GND UART UART Figure 1 PWM PWM GND Vsupply Typical Application for XDPL8220 Product Type Package XDPL8220 PG-DSO-16 Description XDPL8220 is a highly integrated next-generation device combining a boundary mode PFC plus a quasi-resonant FB controller with primary-side regulation. The integration of these functions enables saving of external parts and optimizes performance by harmonized operation of the two stages. XDPL8220 uses a constant on-time scheme with a THD improvement algorithm to provide a high power factor and excellent THD performance. With its unique control scheme of CV, CC and LP, the LED driver designer is provided with a large degree of flexibility and can utilize the system hardware to its limits. The on-chip One Time Programmable Memory (OTP) memory has an area for parameters that control the behavior of the circuit, e. g. the output current or the maximum output power. This enables the user of the device to create a platform concept with significantly fewer different hardware versions while still covering the same application range. The two-stage approach reduces any variation in the output current (flicker) to a non-visible level. By separating the PFC from the power conversion part (FB), both stages operate in a more stable manner and require fewer margins, which has a positive influence on the cost. Lighting requires more and more 24/7 operation, making it necessary to have a stand-by mode with short wakeup times and low power consumption. The power consumption of less than 100 mW of the XDPL8220-based systems defines the new standard for stand-by power in lighting ECGs. XDPL8220 enables adaptive temperature protection using either the internal sensor or an external Negative Temperature Coefficient Thermistor (NTC), or both. Futureproof flexibility with application-oriented programmable operating windows enables management of LED generations and portfolio complexity . Data Sheet 2 Revision 1.0 2016-11-4 XDPL8220 Digital PFC+Flyback Controller IC XDP™ Digital Power Table of contents Table of contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 3 3.1 3.1.1 3.1.2 3.1.3 3.1.4 3.1.5 3.1.5.1 3.1.6 3.1.6.1 3.1.6.2 3.1.7 3.1.8 3.1.9 3.1.10 3.1.11 3.1.12 3.2 3.2.1 3.2.1.1 3.2.1.2 3.2.1.3 3.2.1.4 3.2.1.5 3.2.1.6 3.2.2 3.2.3 3.2.3.1 3.2.3.2 3.2.3.3 3.2.3.4 3.2.3.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 PFC Controller Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Shared CS/ZCD Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Quasi-resonant Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Bus Voltage Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Input Voltage Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Control Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Multimode Control Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Frequency Law . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 THD Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Peak Current Limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Bus Undervoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Bus Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Input Undervoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Input Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Other PFC Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Flyback Controller Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Primary Side Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Primary Side Current Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Primary Side Output Voltage Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Flyback Bus Voltage Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Output Current Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Output Control Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Multimode Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Flyback Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Protection Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Primary Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Output Undervoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Output Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Output Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Output Overpower Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Data Sheet 3 Revision 1.0 2016-11-4 XDPL8220 Digital PFC+Flyback Controller IC XDP™ Digital Power Table of contents 3.2.3.6 3.3 3.3.1 3.3.2 3.3.3 3.3.4 3.3.4.1 3.3.4.2 3.3.4.3 3.3.4.4 3.3.5 3.3.5.1 3.3.5.2 3.3.5.3 3.3.5.4 Other Flyback Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 General Controller Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 External Temperature Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Adaptive Temperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 PWM Dimming Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Protection Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Overtemperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 VCC Undervoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 VCC Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Other General Controller Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Protection Reactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Auto restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Fast Auto Restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Latch Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4 4.1 4.2 4.3 Design Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Design Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 List of Configurable Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 List of Fixed Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5 5.1 5.2 5.3 5.4 Electrical Characteristics and Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 7 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Data Sheet 4 Revision 1.0 2016-11-4 XDPL8220 Digital PFC+Flyback Controller IC XDP™ Digital Power Functional Block Diagram 1 Functional Block Diagram The functional block diagram shows the basic data flow from input pins via signal processing to the output pins. Power Factor Correction HV Data Sheet Output Voltage Sensing and Zero Crossing Detection ZCD GDPFC PFC Control Loop Output Current Calculation CSFB CSPFC Current Sensing and Zero Crossing Detection FB Control Loop GDFB PWM Dimming Sensing PWM UART VS Figure 2 Flyback Input Voltage Sensing and Startup Bus Voltage Sensing Adaptive Temperature Protection VCC VCC Management UART Parametrization TEMP External Temperature Sensing Internal Temperature Sensing XDPL8220 Simplified Functional Block Diagram 5 Revision 1.0 2016-11-4 XDPL8220 Digital PFC+Flyback Controller IC XDP™ Digital Power Pin Configuration 2 Pin Configuration Pin assignments and basic pin description information are shown below. GDFB 1 16 N.C. CSFB 2 15 N.C. VCC 3 14 N.U. GND 4 13 GDPFC ZCD 5 12 UART VS 6 11 CSPFC N.U. 7 10 TEMP HV 8 9 PWM PG-DSO-16(150mil) Figure 3 Pinning of XDPL8220 Table 1 Pin Definitions and Functions Name Pin Type Function GDFB 1 O Gate driver for FB: The GDFB pin is an output for directly driving a power MOSFET of the FB stage. CSFB 2 I Current sensing for FB: The CSFB pin is connected to an external shunt resistor and the source of the power MOSFET of the FB stage. VCC 3 I Voltage supply GND 4 - Power and signal ground ZCD 5 I Zero-crossing detection of the FB: The ZCD pin is connected to an auxiliary winding of the FB stage for zerocrossing detection as well as primary-side output voltage and backup bus voltage sensing for safety. VS 6 I Bus voltage sensing N.U. 7 - Not used. Externally to be connected to GND. HV 8 I High voltage: The HV pin is connected to the rectified input voltage via an external resistor. An internal 600 V HV startup-cell is used to initially charge VCC. In addition, sampled high-voltage sensing is also used for synchronization with the input frequency. PWM 9 I PWM dimming: The PWM pin is used as a dimming input. TEMP 10 I External temperature sensor: Measurement of external temperature using an NTC. CSPFC 11 I Current sensing for PFC: The CSPFC pin is connected to an external shunt resistor and the source of the power MOSFET of the PFC stage. Data Sheet 6 Revision 1.0 2016-11-4 XDPL8220 Digital PFC+Flyback Controller IC XDP™ Digital Power Pin Configuration Table 1 Pin Definitions and Functions (continued) Name Pin Type Function UART 12 I/O Universal Asynchronous Receiver Transmitter (UART) communication: The UART pin is used for the UART interface to support parameterization. GDPFC 13 O Gate driver for PFC: The GDPFC pin is an output for directly driving a power MOSFET of the PFC stage. N.U. 14 - Not used. Externally to be connected to GND. N.C. 15 - Not connected. N.C. 16 - Not connected. Data Sheet 7 Revision 1.0 2016-11-4 XDPL8220 Digital PFC+Flyback Controller IC XDP™ Digital Power Functional Description 3 Functional Description This chapter provides a summary of the integrated functions and features, and describes the relationships between them. The parameters and equations are based on typical values at TA = 25 °C. XDPL8220 is a digital dual-stage PFC and FB controller IC supporting PWM dimming functionality. Both stages use configurable multimode operation to select the best mode of operation for every operation condition. Multimode operation automatically switches between Quasi-Resonant Mode, switching in valley n (QRMn) and DCM. XDPL8220 features a comprehensive set of configurable protection modes to detect fault conditions. XDPL8220 provides a high degree of flexibility in design-in of the application. A Graphic User Interface (GUI) tool supports users in the configuration of the operational and protection parameters. Data Sheet 8 Revision 1.0 2016-11-4 XDPL8220 Digital PFC+Flyback Controller IC XDP™ Digital Power Functional Description 3.1 PFC Controller Features The PFC stage ensures high power quality by maximizing the power factor and minimizing harmonic distortion. The PFC stage operates in Quasi-Resonant Mode, switching in valley 1 (QRM1) and QRMn, to support low load conditions and ensure efficient operation. The PFC stage is implemented as a boost converter. It drains a sinusoidal current from the single-phase line supply and provides stabilized Direct Current (DC) voltage at the internal bus voltage rail. The power factor of the single-phase line supply is almost one. Fluctuations in line voltage as well as voltage drops of short duration are compensated. 3.1.1 Shared CS/ZCD Function The PFC stage makes use of combined CS/ZCD functionality at the CSPFC pin. During the gate driver on-time the pin acts as a current sense (CS), while during the gate driver off-time the pin acts as a zero-crossing-detector (ZCD). The CS senses the on-time current and implements overcurrent limitation; the ZCD exploits the quasi-resonant function to minimize conduction losses. The CSPFC pin is connected via a resistor divider composed of RZCD,1,PFC and RZCD,2,PFC and a set of diodes to an auxiliary winding of the PFC choke inductor. It is used for detecting the valleys of the quasi-resonant oscillation to turn on the PFC MOSFET based on the desired valley computed by the multimode PFC control. The diode D1 allows positive voltage at the CSPFC pin as the valley detection is implemented by the internal hysteretic comparator with a positive reference of nominal THRHYS for falling edges. The CSPFC pin senses the drain source current of the switching MOSFET. The CS voltage is measured after a programmable blanking time after turn-on of the switch. An appropriate current sensing resistor RCS,PFC is selected on the basis of the maximum current flowing in the switching MOSFET and the dynamic voltage range of the input pin CSPFC. Vg L Vbus RZCD,1,PFC D1 GDPFC RCS,PFC CSPFC RZCD,2,PFC VCC Figure 4 3.1.2 Shared CS/ZCD Schematic Quasi-resonant Mode The quasi-resonant mode maintains a high efficiency level. For PFC operating in QRM1, the main switch is turned on with a constant on-time for a line and load condition, while the off-time/demagnetization time varies within an Alternating Current (AC) half-cycle depending on the instantaneously rectified AC input voltage Vg. Subsequently, the switching frequency varies within each AC halfcycle with the lowest switching frequency at the peak of the AC input voltage and the highest switching frequency near the zero crossings of the input voltage. A new switching cycle starts immediately when the first QR valley is reached. Data Sheet 9 Revision 1.0 2016-11-4 XDPL8220 Digital PFC+Flyback Controller IC XDP™ Digital Power Functional Description QRM1 is ideal for full-load operation, where the on-time is large. However, the on-time reduces at light loads, resulting in very high switching frequencies, particularly near the zero crossings of the input voltage. The high switching frequency will increase switching losses, resulting in poor efficiency at light loads. The PFC multimode control can lower the switching frequency by selecting further valleys to achieve QRM2 up to Nvalley,max,PFC operation. The switching frequency is limited within a defined range and the efficiency at light loads improves. tsw iL 1 iL , pk 2 0 ton vCSPFC vL,pk vL,sampled 0 Figure 5 tsw iL,pk tw iL,ave t t1stV tosc 4 ton 2 t tdisch QRM1 QRM2 QRM1 PFC QRM2 Waveforms The equations for the quasi-resonant operation are shown below, where tw is an additional delay in each switching cycle when selecting subsequent valleys after the first QR valley and n is the valley number in QRMn. V g · ton L iL, pk · L tdisch = V bus − V g iL, pk = t1stV = tdisch + tosc /2 tw = tosc · n − 1 tsw = ton + t1stV + tw tof f = t1stV + tw Equation 1 3.1.3 Bus Voltage Sensing The bus voltage is measured at the VS pin. The VS pin implements PFC bus voltage sensing for bus voltage regulation. The bus voltage is scaled down using a simple resistor divider. A capacitor could in certain cases be added at the pin to ground to filter highfrequency switching noise. The bus voltage sensing is a low leakage input and no additional measures are needed to reduce the current consumption. Data Sheet 10 Revision 1.0 2016-11-4 XDPL8220 Digital PFC+Flyback Controller IC XDP™ Digital Power Functional Description Vbus RVS,1 VS RVS,2 Figure 6 Bus Voltage Sensing Schematic The Analog-to-Digital Converter (ADC) input at the VS pin utilizes two voltage ranges. The wider voltage range from 0 to VREF results in lower resolution. The narrower voltage range from 5/6 VREF to 7/6 VREF gives better voltage resolution. Steady state operation therefore normally takes place in the high-resolution range and soft start operation in the low-resolution range. VS 7/6 VREF High resolution range VREF 5/6 VREF Low resolution range 0V Figure 7 3.1.4 t Sensing Ranges Input Voltage Sensing The input voltage is sensed using the HV pin. The input voltage is used for protection, to generate AC zero-crossing signals and to detect the AC/DC source. Data Sheet 11 Revision 1.0 2016-11-4 XDPL8220 Digital PFC+Flyback Controller IC XDP™ Digital Power Functional Description iac vac Input voltage Vin { RHV C1 Figure 8 C2 HV Input Voltage Sensing Schematic The RHV probing resistor is usually split into two, or three or more resistors for safety purposes. In fact in case of a resistor being shorted by damage, the high resistive path is maintained by the other resistors avoiding fire, shock to the user and further damage to the application. A RC filter structure making use of the split resistors filters the unwanted noise for the high voltage input voltage measurement. The filtering effect is kept high due to the usage of the high impedance split resistors and the addition of small capacitance high voltage capacitors. 3.1.5 Control Scheme The PFC bus voltage controller embeds a PIT1 controller that calculates a control output representing load and line conditions from the bus voltage error signal. The bus voltage controller implements regulation during both soft start and steady states. 3.1.5.1 Startup At system startup, the PFC initiates a soft start to minimize the switching stress for the power MOSFET, diode and inductor. The soft start is executed when the bus voltage is higher than the Vbus,start,PFC threshold. This is the brown-in condition. The soft start is aborted if the input under- or overvoltage protection fire. During soft start, the PFC stays in QRM1 operation. Once the Vbus,stdy,entr,UV threshold is reached, the steady state PFC operation starts. Data Sheet 12 Revision 1.0 2016-11-4 XDPL8220 Digital PFC+Flyback Controller IC XDP™ Digital Power Functional Description Vbus Vbus,set Vbus,stdy,entr,UV Vbus,start,PFC VCC startup passive charging charging Figure 9 3.1.6 steady state t Vbus Soft Start and Regulation Multimode Control Scheme The multimode control scheme provides a PFC option to dynamically change the operating point by switching between the MOSFET Vds voltage valleys while following a frequency law and applying THD optimization. The multimode controller uses two different modes of operation: • QRM1: This operation maximizes the efficiency by switching on the 1st valley of the PFC ZCD signal. This ensures zero current switching with a minimum of switching losses. • QRMn: The controller will extend to the next switching valley after the 1st valley to control the bus voltage following a frequency law. The multimode optimization consists of the following: • Frequency law • THD optimization 3.1.6.1 Frequency Law The output of the PFC PIT1 bus voltage controller gives the desired on-time, which is constant within each AC half cycle. A PFC is used to emulate a resistive load re to the AC input such that iac follows vac in both wave shape and phase. The output of the PFC bus voltage controller ton,des,PFC is inversely proportional to the emulated resistive load re such that a smaller re or a higher Iac,rms will give a larger ton,des,PFC. Thus, ton,des,PFC is different for the same load at different line voltages and is proportional to the RMS input current Iac,rms. The rule for selecting QRMn is based on the frequency law. A maximum switching frequency fswmax and a minimum switching frequency fswmin are defined for the complete ton,des,PFC/Iac,rms range. The frequency law ensures that the switching frequency is within the desired frequency range. The frequency law is depicted in the figure below. Data Sheet 13 Revision 1.0 2016-11-4 XDPL8220 Digital PFC+Flyback Controller IC XDP™ Digital Power Functional Description fswmax M1 QR 2 M QR 3 M QR 4 M QRM5 QR fsw fswmin sample operating point Figure 10 ton,des,PFC / Iac,rms PFC Frequency Law As long as the PFC controller operating mode fulfills the frequency law, the operating mode does not change. The QR-valley is increased when the highest frequency limit is reached. The QR-valley is decremented when the lowest frequency limit is reached. To ensure good ZCD detection before the ZCD signal becomes too small in amplitude, only the first up to Nvalley,max,PFC valleys operations are supported. 3.1.6.2 THD Optimization THD optimization reduces the THD in the case of light loads and in the case of high AC input voltages. The selection of higher valleys helps to reduce the switching frequency but it also distorts the input current waveform with constant on-time control and thus affects the PFC THD performance. The multimode PFC control also consists of a THD optimization algorithm that optimizes the applied on-time in order to ensure good input current shaping and improved PFC THD performance. 3.1.7 Peak Current Limitation The peak current through the switching MOSFET is read via the PFC shunt resistor RCS,PFC to limit the maximum current through the MOSFET, the choke, and freewheeling diode so as to avoid potential hard failure or lifetime stress. The OCP causes the current to be limited to cases in which an overcurrent condition occurs. Overcurrent Protection Level 1 (OCP1) is implemented by hardware. If the voltage VCS,PFC across the shunt resistor exceeds the overcurrent threshold VCS,OCP1, PFC for longer than the blanking time tblank,OCP1,PFC, the MOSFET is turned off. The MOSFET is turned on when ZCD occurs or the PFC maximum period time-out signal triggers the start of the next switching cycle. Overcurrent Protection Level 2 (OCP2) is a second-level overcurrent protection implemented by hardware. The OCP2 overcurrent threshold is fixed. The OCP2 blanking time is tblank,OCP2,PFC. 3.1.8 Bus Undervoltage Protection Undervoltage detection of the bus voltage Vbus is provided by measurement using the VS pin. The bus voltage is compared to a configurable undervoltage protection threshold Vbus,UV. If the threshold is exceeded for longer than the blanking time tblank,Vbus,UV, the protection will be triggered. Data Sheet 14 Revision 1.0 2016-11-4 XDPL8220 Digital PFC+Flyback Controller IC XDP™ Digital Power Functional Description 3.1.9 Bus Overvoltage Protection Overvoltage detection of the bus voltage Vbus is provided by the measurement using the VS pin. The bus voltage is compared to a configurable overvoltage protection threshold Vbus,OVP1 in Firmware (FW). If a threshold is exceeded for longer than the blanking time tblank,Vbus,OVP1, the gate driver stops. The gate driver operation is resumed when Vbus falls below Vbus,stdy,entr,OV. Vbus,OVP2 is implemented in Hardware (HW) and it is fixed at a voltage which is represented as 2.8 V at the bus voltage sensing pin (VS). The HW permits a blanking time tblank,Vbus,OVP2 to be programmed. Vbus Vbus,ovp2 Vbus,ovp1 Vbus,stdy,entr,OV Vbus,set Vbus,uv t Figure 11 3.1.10 Vbus protections Input Undervoltage Protection Undervoltage detection of the input voltage Vin is provided by measurement using the HV pin. Values of Vin,rms are compared to a configurable input undervoltage protection threshold Vin,UV. If the threshold is exceeded for longer than the blanking time tblank,Vin,UV, the protection will be triggered. XDPL8220 features a configurable startup threshold Vin,start,min to create hysteresis for flicker-free operation before the second stage starts switching. After startup checks when trms,reset,PFC expires, the comparison is restored to the threshold value Vin,UV. 3.1.11 Input Overvoltage Protection Overvoltage detection of the input voltage Vin is provided by measurement using the HV pin. Values of Vin,rms are compared to a configurable input overvoltage protection threshold Vin,OV. If the threshold is exceeded for longer than the blanking time tblank,Vin,OV, the protection will be triggered. XDPL8220 features a configurable startup threshold Vin,start,max to create hysteresis for flicker-free operation before the second stage starts switching. After startup checks when trms,reset,PFC expires, the comparison is restored to the threshold value Vin,OV. Note: Data Sheet In the csv file the input OVP shall be disabled by default. 15 Revision 1.0 2016-11-4 XDPL8220 Digital PFC+Flyback Controller IC XDP™ Digital Power Functional Description Vin Vin,OV Vin,start,max Vin,start,min Vin,UV t trms,reset,PFC Figure 12 Vin protections 3.1.12 Other PFC Protections CS Resistor Short Protection The input circuit breaker (fuse) shall be chosen appropriately in order to protect in case of current-sense resistor short. CS Resistor Open Protection The external circuitry for shared CS/ZCD pulls the CSPFC pin high in case of CS resistor missing so that the OCP2 protection is triggered. CSPFC Pin Short to GND Protection In case of CSPFC pin short to ground the lack of quasi-resonant oscillations shall trigger the CCM Protection. CCM Protection Continuous conduction mode (CCM) operation may occur during PFC startup for a limited time. It is considered as a failure in the system only if CCM operation of the PFC converter is observed over a longer period of time. The PFC converter may run into CCM operation for a longer period due to a shorted bypass diode, a heavy load step that is out of specification or very low input voltage outside the normal operating range. When CCM occurs, the magnetizing current in the PFC choke does not have the chance to decay to zero before the MOSFET turns on. No quasi-resonant oscillation will be seen at the ZCD signal before the maximum switching period time-out is reached that turns the MOSFET on. This turn-on event without ZCD oscillation is monitored to protect the PFC converter from continuous CCM operation. The CCM protection is implemented by firmware. If any quasi-resonant oscillation is seen at the ZCD signal for longer than the blanking time tblank,CCM,PFC, the protection is triggered. Soft Start Failure The soft start may take a long time, potentially never reaching steady state operation due to heavy loads or very low input voltages. If tstart,PFC reaches tstart,max,PFC before the soft start has ended, the protection is triggered. Data Sheet 16 Revision 1.0 2016-11-4 XDPL8220 Digital PFC+Flyback Controller IC XDP™ Digital Power Functional Description 3.2 Flyback Controller Features The FB stage provides primary side control that avoids secondary side control feedback loop circuitry usually needed in isolated power converters. This approach supports a low part count to reduce costs. The FB stage features multi-mode operation and it selects the best mode of operation based on operating conditions. 3.2.1 Primary Side Regulation The FB in XDPL8220 provides primary side control of output current and output voltage. No external feedback components are necessary for the current control as the primary side regulation control loop is fully integrated. Figure 13 shows typical current and voltage waveforms of the FB application operating in QRM1. In DCM, the next switching cycle will not start at the first valley of VAUX, but is instead delayed. As a consequence, the switching losses in DCM will be higher. The primary peak current Ip,pk, the period of conduction of the output diode tdemag and the switching period tsw,FB are used to calculate the average output current. The voltage signal VAUX of the auxiliary winding of the transformer contains information on the reflected output voltage Vout. The reflected output voltage is measured at the ZCD pin using a resistor divider. Data Sheet 17 Revision 1.0 2016-11-4 XDPL8220 Digital PFC+Flyback Controller IC XDP™ Digital Power Functional Description VAUX Output voltage sampling Zero crossing detection 0V Bus voltage sampling Valley switching Ip time tCS,sample Is Vbus Vout tZCD,sample Itransformer Np Na tsw,FB Ns Ip,pk Ip VAUX Ip Is time tdemag VGD time Figure 13 Typical Waveforms of a Flyback Converter 3.2.1.1 Primary Side Current Sensing The primary side peak current Ip,pk is controlled by the control loop using the VCS,OCP1 level at the CSFB pin. This control scheme ensures suppression of any variation in the bus voltage. Several delays exist from the time at which the OCP1 level VCS,OCP1 is exceeded at the CSFB pin until the gate switches off and the transformer current finally reaches its peak value. For a higher accuracy, the primary peak current VCS,SH is sampled a fixed time before turn-off of the gate. The primary side peak current is used to calculate the secondary side current and for protection. The propagation delay compensation parameter tPDC allows optimization of the accuracy of the primary side peak current: Ip, pk = V CS, SH RCS, FB ⋅ ton, FB + tPDC ton, FB − tCSFB, offset Equation 2 Data Sheet 18 Revision 1.0 2016-11-4 XDPL8220 Digital PFC+Flyback Controller IC XDP™ Digital Power Functional Description Note: If an RC low pass filter is added in front of the CSFB pin, the related low pass filter delay has to be included in tPDC. Ip Ip,pk = VCS,pk RCS,FB VCS,SH RCS,FB t tPDC VGD tCSFB,offset t ton,FB Figure 14 Propagation Delay Compensation for accurate Primary Peak Current Calculation 3.2.1.2 Primary Side Output Voltage Sensing The output voltage is determined by measuring the reflected output voltage on the auxiliary winding. A resistor divider adapts the voltage to the operating range of the ZCD pin. The output voltage is measured at the ZCD pin using the voltage VZCD,SH at the end of the demagnetization time at the time tZCD,sample. The voltage measured at the ZCD pin, the dimensioning of the resistor dividers RZCD,FB,1 and RZCD,FB,2 , transformer turns Ns and Na as well as an offset V out,offset (caused by the secondary diode, for example) are used to calculate the output voltage Vout as follows: V out = V ZCD, SH RZCD, FB, 1 + RZCD, FB, 2 Ns RZCD, FB, 2 Na + V out, offset Equation 3 Vout is used for Primary Side Regulated (PSR) control loops in CV and LP modes as well as for output over- and undervoltage protections. Vout,offset Na Ns RZCD,FB,1 VOut ZCD VZCD,SH RZCD,FB,2 Figure 15 Primary Side Output Voltage Sensing using ZCD S&H Note: Any relation between VCC and ZCD in self-supplied applications can be decoupled – e.g. by adding a linear regulator for VCC. Data Sheet 19 Revision 1.0 2016-11-4 XDPL8220 Digital PFC+Flyback Controller IC XDP™ Digital Power Functional Description Attention: Please note that the time (tdemag) has to be longer than 2.0 μs to ensure that the reflected output voltage can be sensed correctly at the ZCD pin. 3.2.1.3 Flyback Bus Voltage Sensing The FB can sense the bus voltage using the reflection of bus voltage on the auxiliary winding while the gate is turned on. A resistor divider adapts the negative voltage to the operating range of the ZCD pin. This second measurement path is required to protect against component failures in the VS measurement path (open loop protection for the PFC stage). The reflected bus voltage appears as a negative voltage at VAUX. This negative voltage is internally clamped at the ZCD pin to the negative voltage VINPCLN. The internal clamping current IZCD is measured at the end of the ontime at the time tCS,sample. The measured clamping current of the ZCD pin, the dimensioning of the resistor dividers RZCD,FB,1 and RZCD,FB,2 as well as the number of transformer turns Na and Np are used to calculate the bus voltage Vbus,FB as follows: V bus, FB = IZCD + V INPCLN RZCD, FB, 2 RZCD, FB, 1 + V INPCLN Np Na Equation 4 Vbus,FB is used for plausibility checks with the voltage Vbus as measured using the VS pin. Na RZCD,FB,1 ZCD Np Vbus,FB IZCD VINPCLN RZCD,FB,2 Figure 16 Voltage Sensing using ZCD Clamp Current 3.2.1.4 Output Current Calculation The output current is calculated based on the primary side peak current and the timing of the switching cycle. The output current Iout is calculated using the duration of conduction of the output diode tdemag, the switching period tsw,FB as well as the number of transformer turns Np, Ns and the transformer coupling Kcoupling. The following equation is valid both in QRM1 and DCM: 1 Iout = 2 Ip, pk ⋅ Np Ns ⋅ K coupling ⋅ tdemag tsw, FB Equation 5 The coupling of the transformer can be approximated using the transformer primary inductance Lp and the transformer primary leakage inductance Lp,lk as follows: K coupling ≈ Lp Lp + Lp, lk Equation 6 The calculated current Iout is used for the control loop in the modes CC and LP. The calculated current is also used for output overcurrent protection. Data Sheet 20 Revision 1.0 2016-11-4 XDPL8220 Digital PFC+Flyback Controller IC XDP™ Digital Power Functional Description 3.2.1.5 Output Control Scheme The XDPL8220 includes three different control schemes for a CC, CV or LP output. Different use cases require the controller to operate according to different operation schemes: • In the case of typical LED strings, the forward voltage of the LED string determines the output voltage of the driver. XDPL8220 operates in CC and drives a constant output current Iout,full to the load. The forward voltage of the connected LED string has to be below a configurable maximum value Vout,set. • In the case of LED loads including a power stage (e.g. Infineon BCR linear regulators or Infineon DC/DC buck ILD2111), XDPL8220 operates in CV, ensuring a constant voltage Vout,set to the load. The total output current drawn by the load has to be below a configurable maximum value Iout,full. • In the case of a high output current setpoint Iout,full and an overly long LED string which exceeds the configurable power limit Pout,set, XDPL8220 operates in LP to ensure that the power limit of the driver is not exceeded. The controller reduces the output current automatically, ensuring light output without any interruption even for overly long LED strings. The forward voltage of the connected LED string has to be below a configurable maximum value Vout,set. For every update of the control loop, the control scheme is selected on the basis of the current operation conditions (output voltage Vout and output current Iout) and their distance to the three limiting setpoints (Vout,set, Pout,set and Iout,full): • For CC schemes, the internal reference current Iout,full is weighted according to thermal management and a dimming curve to yield Iout,set. The calculated output current Iout is compared with the weighted reference current Iout,set to generate an error signal for the output current. • For CV schemes, the sensed output voltage Vout at the ZCD pin is compared to a reference voltage Vout,set to generate an error signal for the output voltage. • For LP schemes, the output current is limited to a maximum of Iout,set = Pout,set / Vout. Out of these three schemes, for each step the most critical error is selected (see Figure 17 ): 1. If any setpoint is exceeded, the largest error for power decrease is selected to bring the controller back to the desired operating point as quickly as possible. 2. If the current operating conditions are below all three setpoints, the smallest error for power increase is selected to avoid overshooting any setpoint. The selected error signal is fed into a compensator to control the gate driver switching parameters (i.e. duty cycle and frequency) for the power MOSFET of the FB. Output voltage Vout,OV Output open Pout,set Pout,OPP Vout,set Constant voltage Limited power Constant current Vout,start Vout,UV Iout,min Figure 17 Output short Iout,full Iout,OCP Output current Control Scheme for CC/CV/LP Modes (Non-Dimmed) In dimming cases, the output current setpoint Iout,set is located between Iout,min and Iout,full and varies according to the sensed PWM duty cycle DDIM. Dimming can be visualized by moving the vertical line for the output current setpoint in Figure 18 from right to left. Data Sheet 21 Revision 1.0 2016-11-4 XDPL8220 Digital PFC+Flyback Controller IC XDP™ Digital Power Functional Description Note: An operation in limited power mode can cause dimmer dead-travel until the controller enters constant current mode. Output voltage Output open Vout,OV Legend: Pout,set Operating range Constant voltage Vout,set Limited power Dimming Vout,start Vout,UV Constant current Output short Dim-to-Off Iout,min Figure 18 Iout,full Output current Control Scheme for CC/CV/LP Modes (including Dimming) One or more of the output control schemes can be deactivated by configuration of the setpoints. Some examples are given below: • The LP scheme is not active for Pout,set > Vout,set * Iout,full. For such a configuration, the controller will only select between a CC and CV scheme. • The CV scheme is not active for Vout,set = Vout,OV as the output overvoltage protection will be triggered. • The CC scheme is not active for Iout,full = Iout,OC as the output overcurrent protection will be triggered. 3.2.1.6 Multimode Scheme The control loop of XDPL8220 uses two different switching modes. QRM1 is optimized for high efficiency at high loads while DCM is used in light load conditions. Power VCS,max,FB Peak-current controlled Pmax QRM1 VCS,min,FB tsw,min,FB Frequency controlled DCM tsw,max,FB Bus Voltage Pmin Vbus,UV Figure 19 Vbus,OVP1 Flyback Multimode Operation Scheme • QRM1: This mode maximizes the efficiency by switching on the 1st valley of the VAUX signal. This ensures zero current switching with a minimum of switching losses. The power is controlled by regulating the primary peak current using VCS,OCP1. • DCM: This mode is used if VCS,OCP1has reached its minimum value VCS,min,FB. To allow lower output power, the controller extends the switching period later than the 1st valley . Data Sheet 22 Revision 1.0 2016-11-4 XDPL8220 Digital PFC+Flyback Controller IC XDP™ Digital Power Functional Description The minimum power is limited by the transformer primary inductance Lp, maximum switching period tsw,max,FB and minimum primary peak current Ip,pk,min: Pmin = 1 2 ⋅ Lp ⋅ Ip, pk, min2 ⋅ 1 tsw, max, FB Equation 7 The minimum primary peak current Ip,pk,min is restricted by: Ip, pk, min = tdemag, min ⋅ Np Ns ⋅ V out, OV Lp Equation 8 Note: 3.2.2 If the load drops below the minimum load of Pmin, the output voltage will rise up to the output overvoltage threshold Vout,OV and trigger the protection. An auto-restart can be used to keep the output voltage close to Vout,OV until the load increases again. Flyback Startup After startup, the FB of the XDPL8220 initiates a soft start to minimize the switching stress for the power MOSFET and secondary diode. The cycle-by-cycle current limit is increased in steps of VCS,step with a configurable duration tsoftstart for each step. After the final VCS,OCP1,start limit level has been reached, the output will be charged until the minimum output voltage Vout,start, which ensures self-supply has been reached. At this condition, Continuous Conduction Mode (CCM) protection as well as output undervoltage protection are activated and the control loop takes over. The starting point for the control loop is to operate in DCM at lowest switching frequency and shortest on-time. These switching parameters avoid any overshoot of output current for short LED string in dimmed conditions. Output voltage Peak current Startup Soft start phase Output charging phase Control loop active Vout Vout,start VCS,OCP1 VCS,OCP1,start Startup Check VCS,step time tsoftstart Figure 20 Data Sheet Flyback Startup Sequence 23 Revision 1.0 2016-11-4 XDPL8220 Digital PFC+Flyback Controller IC XDP™ Digital Power Functional Description 3.2.3 Protection Features Protections ensure the operation of the controller under restricted conditions. Protections are triggered if fault conditions are present longer than the blanking times configured for each protection3). The controller will react to a triggered protection as configured. Attention: The controller may continue operation after exceeding protection thresholds because of blanking times. All protection thresholds have to be set with respect to tolerances, blanking times and worst case transients. Value Value Upper Threshold Lower Threshold Time Time tblank Figure 21 3.2.3.1 tblank Blanking Times cause Excess of Threshold Primary Overcurrent Protection The primary side overcurrent protection implemented in hardware covers fault conditions like a short in the transformer primary winding or an open CS pin. The primary side current is compared to a configurable overcurrent protection threshold VCS,OCP2. If the threshold is exceeded for longer than the blanking time tOCP2,FB, the protection will be triggered. 3.2.3.2 Output Undervoltage Protection In the case of a short in the output, the output voltage may drop to a very low level. Detection of undervoltage in the output voltage Vout is enabled by measurement of the reflected voltage at the ZCD pin. During operation, the output voltage is compared to a configurable undervoltage protection threshold Vout,UV. If the threshold is exceeded for longer than the blanking time tblank,out,UV, the protection will be triggered. This protection threshold Vout,UV is disabled during startup. During startup, the protection operates differently: In case the FB cannot charge the output voltage to Vout,start during a timeout of tstart,max,FB, the protection will be triggered. This timeout starts when the FB is started. Note: 3.2.3.3 The startup threshold Vout,start has to be configured over and above the undervoltage threshold Vout,UV to allow undershoots at startup which may occur, especially for resistive loads. Output Overvoltage Protection In case of a open output, the output voltage may rise to a high level. Overvoltage detection of the output voltage Vout is provided by measurement at the ZCD pin. The output voltage is compared to a configurable overvoltage protection threshold Vout,OV. If the threshold is exceeded for longer than the blanking time tblank,out,OV, the protection will be triggered. 3 except VCC undervoltage protection Data Sheet 24 Revision 1.0 2016-11-4 XDPL8220 Digital PFC+Flyback Controller IC XDP™ Digital Power Functional Description Note: The blanking time tblank,Vout,OV should be set to the minimum value to minimize overshoots of the output voltage above the protection threshold. Note: This protection is usually triggered if the output is open or the output load drops below the minimum load Pmin. 3.2.3.4 Output Overcurrent Protection Overcurrent detection in the output current Iout is provided on the basis of the calculated output current. The calculated output current is compared to a configurable overcurrent protection threshold Iout,OC. If the threshold is exceeded for longer than the blanking time tblank,out,OC, the protection will be triggered. 3.2.3.5 Output Overpower Protection Overpower detection in the output power Pout is provided on the basis of the calculated output power. The calculated output power is compared to a configurable overpower protection threshold Pout,OP. If the threshold is exceeded for longer than the blanking time tblank,out,OP, the protection will be triggered. 3.2.3.6 Other Flyback Protections XDPL8220 includes additional protections to ensure the integrity and correct flow of the firmware. • A hardware weak pull-up protects against an open CSFB pin. • A firmware watchdog protects against the CSFB pin becoming shorted to GND. • A firmware state monitor supervises correct operation of the flyback in QRM1 or DCM. A protection is triggered if the flyback enters CCM. • A firmware check ensures that the PFC has already boosted the bus voltage sufficiently before the FB starts. • A firmware plausibility check ensures that the bus voltage measurement using the VS pin is correct. Data Sheet 25 Revision 1.0 2016-11-4 XDPL8220 Digital PFC+Flyback Controller IC XDP™ Digital Power Functional Description 3.3 General Controller Features XDPL8220 provides general features for firmware task scheduling, VCC control and temperature control which are independent of the target application. 3.3.1 External Temperature Sensing The external temperature is measured by measuring the voltage of an NTC with respect to the internal VREF voltage. Controller VREF RPU TEMP VTEMP Figure 22 RNTC External Temperature Sensing using NTC The controller calculates the resistance of the NTC based on the measured voltage VTemp, the internal reference voltage VREF and the internal pull-up resistance RPU: RNTC = V Temp ⋅ RPU V REF − V Temp Equation 9 3.3.2 Adaptive Temperature Protection XDPL8220 offers adaptive temperature protection using internal and/or external temperature sensors. This feature reduces the output current according to temperature to protect the load and driver against overtemperature. Whenever the temperature Thot is exceeded, the current is gradually reduced from the maximum current Iout,set, as shown in Figure 23 . If the temperature drops below Thot, the output current is increased again. This allows the controller to ensure operation at or below a temperature of Thot. If a reduction down to a minimum current Iout,red is not able to compensate for any continued increase in temperature, XDPL8220 will eventually trigger overtemperature protection if Tcritical is exceeded. If the controller is configured to react with auto-restart to the overtemperature protection, it will only restart after the temperature dropped below Thot. Output Current Output Current Iout,full Iout,full Iout,red Iout,red T≤Thot Thot Tcritical Figure 23 Data Sheet Temperature T>Thot T=Thot T≤Thot T=Thot Time Adaptive Temperature Protection 26 Revision 1.0 2016-11-4 XDPL8220 Digital PFC+Flyback Controller IC XDP™ Digital Power Functional Description Note: Please note that the internal temperature sensor can only protect external components which have sufficient thermal coupling to XDPL8220. The external temperature sensor can be used to protect the temperature of external components (e.g. power MOSFETs or linear regulators). 3.3.3 PWM Dimming Interface The duty cycle sensed at the PWM pin is used to determine the output current level. The XDPL8220 can be configured to use either a linear or a quadratic dimming curve. Either normal or inverted dimming curves can be selected. Figure 24 shows the relationship of the PWM duty cycle to the output current target value. Configurable levels DDIM,min and DDIM,max ensure that the minimum current Iout,min and maximum current Iout,set can always be achieved, thereby making the application robust against component tolerances. An optional hysteresis can be enabled for the sensing of the PWM signal. This hysteresis can suppress jitter in the PWM signal. Any change of the PWM duty cycle within the hysteresis will not affect the output current. Output current Output current Iout,full Iout,full Iout,min DDIM,off DDIM,on DDIM,min DDIM,max Iout,min PWM duty cycle DDIM,off PWM duty cycle Output current Output current Iout,full Iout,full Iout,min DDIM,max Figure 24 DDIM,on DDIM,max DDIM,min DDIM,min PWM duty cycle DDIM,on DDIM,off Iout,min DDIM,max DDIM,min DDIM,on PWM duty cycle DDIM,off Selectable Dimming Curves Using the optional Dim-to-Off feature, the light output can be stopped without removal of input voltage. In Dimto-Off, the controller will enter auto-restart operation to minimize power consumption. The auto-restart recharges the output voltage to a minimum output voltage of Vout,start to measure the PWM duty cycle. With this feature, the output voltage can be maintained in a specific range by configuration of the startup voltage Vout,start and auto-restart time tAR, and by dimensioning of an active or passive output bleeder. If Vout,start is configured to be low enough below the minimum forward voltage of the LED string, the LEDs will show no light in this state. Note: Data Sheet Either an active or passive output bleeder is required to allow the controller to maintain the output voltage if the Dim-to-Off feature is enabled. 27 Revision 1.0 2016-11-4 XDPL8220 Digital PFC+Flyback Controller IC XDP™ Digital Power Functional Description Dim-to-Off is entered if the PWM duty cycle exceeds the configurable threshold DDIM,off (see purple line in Figure 24 ). As soon as the duty cycle exceeds DDIM,on, the controller will start to continuously regulate output voltage or output current again. 3.3.4 Protection Features Protections ensure the operation of the controller under restricted conditions. Protections are triggered if fault conditions are present longer than the blanking times configured for each protection4). The controller will react to a triggered protection as configured. Attention: The controller may continue operation after exceeding protection thresholds because of blanking times. All protection thresholds have to be set with respect to tolerances, blanking times and worst case transients. Value Value Upper Threshold Lower Threshold Time Time tblank Figure 25 3.3.4.1 tblank Blanking Times cause Excess of Threshold Overtemperature Protection Overtemperature protection initiates a shutdown once the critical temperature level Tcritical is exceeded. Figure 26 shows the temperature hysteresis formed by the critical temperature Tcritical and maximum turn-on threshold Thot if auto-restart is enabled for temperature protection. If latch mode is selected instead, the IC will turn off and only restart after recycling of input power with a temperature below Tcritical. Output current Iout,full Thot T critical Figure 26 4 Temperature Temperature Protection except VCC undervoltage protection Data Sheet 28 Revision 1.0 2016-11-4 XDPL8220 Digital PFC+Flyback Controller IC XDP™ Digital Power Functional Description 3.3.4.2 VCC Undervoltage Protection A Undervoltage Lockout (UVLO) is implemented in hardware. It ensures defined enabling and disabling of the Integrated Circuit (IC) operation depending on the supply voltage VVCC at the VCC pin in accordance with defined thresholds. The UVLO contains a hysteresis with the voltage thresholds VVCC,on for enabling the IC and VVCC,off for disabling the IC. Once the mains input voltage is applied, current flows through an external resistor into the HV pin via the integrated depletion cell and diode to the VCC pin. The IC is enabled once VVCC exceeds the threshold VVCC,on and enters normal operation if no fault condition is detected. In this phase, VVCC will drop until either external supply or the self-supply via the auxiliary winding takes over the supply at the VCC pin. In the case of output short or strong capacitive loading, the auxiliary winding cannot provide power to VVCC. A timeout of tstart,max is available to respond to this failure condition. Note: The self-supply via the auxiliary winding must be in place before the output short timeout occurs or before VVCC falls below the VVCC,off threshold. Otherwise, the system will perform a fast restart. Note: It is possible to supply VCC externally from an auxiliary power supply. In this case, the VCC also needs initially to ramp to VVCC,on to enable the IC. 3.3.4.3 VCC Overvoltage Protection Overvoltage protection ensures that the voltage at the VCC pin is not exceeded. The VCC voltage is compared to a configurable overvoltage protection threshold VVCC,OV. If the threshold is exceeded for longer than the blanking time tblank,VCC,OV, the protection will be triggered. Note: 3.3.4.4 The reaction to this protection is fixed to stop mode to ensure a discharge of VCC. Other General Controller Protections XDPL8220 includes several protections to ensure the integrity and correct flow of the firmware. • A hardware watchdog checks correct execution of firmware. A protection is triggered in the event that the firmware does not service the watchdog within a defined period. • A hardware Random Access Memory (RAM) parity check triggers a protection if a bit in the memory changes unintentionally. • A hardware clock check watchdog checks that no clock oscillator is failing. • A firmware Cyclic Redundancy Check (CRC) at each startup verifies the integrity of firmware code and its parameters. • A firmware task execution watchdog triggers a protection if the firmware tasks are not executed as expected. 3.3.5 Protection Reactions The reaction to each protection can be separately selected. Available reactions may include auto restart, fast auto restart, latch or stop mode. Figure 27 depicts the timing of an auto-restart reaction: 1. If a protection threshold is exceeded for longer than the related blanking time tblank, the protection is triggered. 2. Within a maximum t1 = 4 * 32 µs, the gate driver of the power stage related to the protection is disabled. 3. Within a maximum t2 = 4 * 32 µs, the gate drivers of other stages are disabled. 4. The reaction depends on the configuration of the protection: • In case of latch mode, the application will enter latch mode at this time. No further steps are done, the reaction ends here. Data Sheet 29 Revision 1.0 2016-11-4 XDPL8220 Digital PFC+Flyback Controller IC XDP™ Digital Power Functional Description • In case of stop mode, the application will stop and enter UART parametrization mode which allows to read out the error code. No further steps are done, the reaction ends here. • In case of a (fast) auto-restart reaction, the controller will enter a power saving mode for the auto-restart time tAR or tAR,fast respectively. 5. The auto restart may include a new VCC charging cycle. The time t3 typically depends on the input voltage. 6. The first power stage will enable its gate driver according to its startup sequence (soft start) again. 7. The second power stage will enable its gate driver according to its startup sequence (soft start) again. The startup of a subsequent power stage may be delayed by a time t4 depending on any startup condition for the subsequent stage. Threshold is exceeded Protection is triggered Related gate driver is disabled Other gate drivers are disabled Startup, charging of VCC Restart of the first stage Restart of the second stage Value Threshold Other gate driver Related gate driver Time tblank t1 Figure 27 3.3.5.1 t2 tAR t3 t4 Protection Reaction for auto-restart Auto restart When auto restart mode is activated, XDPL8220 stops switching at the GD pins. After a configurable auto restart time tAR, XDPL8220 initiates a new startup with soft start. During the time in which the gate is not switching, the internal HV startup cell is automatically enabled and disabled to keep the VCC voltage between the VUVLO and VOVLO thresholds for the supply of XDPL8220. 3.3.5.2 Fast Auto Restart When fast auto restart mode is activated, XDPL8220 stops switching at the GD pins. After a configurable fast auto restart time tAR,fast, XDPL8220 initiates a new startup with soft start. During the time in which the gate is not switching, the internal HV startup cell is automatically enabled and disabled to keep the VCC voltage between the VUVLO and VOVLO thresholds for the supply of XDPL8220. Data Sheet 30 Revision 1.0 2016-11-4 XDPL8220 Digital PFC+Flyback Controller IC XDP™ Digital Power Functional Description 3.3.5.3 Latch Mode When latch mode is activated, XDPL8220 stops switching at the GD pins. The device stays in this state until input voltage is completely removed and the VCC voltage drops below the VUVLO threshold. Only then can XDPL8220 be restarted by applying input voltage. To maintain this state, the internal HV startup cell is automatically enabled and disabled to keep the VCC voltage between the VUVLO and VOVLO thresholds for the supply of XDPL8220. The current consumption is reduced to a minimum. 3.3.5.4 Stop Mode When stop mode is activated, XDPL8220 stops switching at the GD pins. XDPL8220 enters UART communication mode to allow debugging of the system state. Note: Data Sheet The VCC for XDPL8220 needs to be supplied by an external source. Without an external supply, VCC will drain to VUVLO and XDPL8220 performs a restart. 31 Revision 1.0 2016-11-4 XDPL8220 Digital PFC+Flyback Controller IC XDP™ Digital Power Design Support 4 Design Support XDPL8220 is a configurable digital platform product. It can be configured to meet a wide range of application requirements. 4.1 Design Procedure Infineon provides support of the design procedure for lighting applications using Infineon's digital platform ICs. A lighting application is designed in a few simple steps using Infineon's digital platform ICs as follows: 1. The Infineon XDPL8220 reference board and the XDPL8220 Reference Board Test Report demonstrate the features and performance of the XDPL8220 in a typical application. 2. Parameters of the XDPL8220 reference board can easily be fitted to any application's requirements. The isolated .dp Interface Gen2 is connected to XDPL8220 via Universal Serial Bus (USB). The GUI tool .dp Vision is included with the .dp Interface Gen2. .dp Vision allows interactive changing of parameters. The usage of .dp Vision is explained in the .dp Vision User Manual. 3. To further adapt the XDPL8220 to application requirements, customers can design their own specific boards. The steps used to design a board are explained in the XDPL8220 Design Guide. .dp Vision can be used together with the .dp Interface Gen2 to connect to customer-specific designs based on XDPL8220. This setup can be used for rapid prototyping. The tooling allows fine-tuning of parameters and development of multiple parameter sets – e.g. to reuse the same for different product variants of an application. 4. For mass production, the XDPL8220 Programming Manual documents the necessary interfacing and procedures to integrate the parameter configuration of XDPL8220 into the production line. Figure 28 shows two options to easily apply the configuration of the IC during production tests: • One option is to use the isolated .dp Interface Gen2, which can be accessed with USB commands. • Another option is to directly use the UART interface of the XDPL8220. The correct VCC voltage and UART communication have to be controlled by the production process in this case. PC with GUI tool Production process USB USB Isolated .dp Interface Gen2 VCC Isolated .dp Interface Gen2 VCC 4.2 IC GND UART IC GND VCC Production process Figure 28 UART UART IC GND Setup for Parametrization using .dp Interface Gen2 for Interactive Development (top) and Production (middle and bottom) List of Configurable Parameters This list provides information about configurable parameters, including their permitted range and granularity. Typical example values are also provided. Table 2 Parameters for Hardware Configuration Symbol Description Example Minimum Value Maximum Value Granularity Na FB auxiliary winding turns 34 1 300 1 Np FB primary winding turns 60 1 300 1 Data Sheet 32 Revision 1.0 2016-11-4 XDPL8220 Digital PFC+Flyback Controller IC XDP™ Digital Power Design Support Table 2 Parameters for Hardware Configuration (continued) Symbol Description Example Minimum Value Maximum Value Granularity Ns FB secondary winding turns 44 1 300 1 RCS,FB FB current sense resistance 410/2048 Ω 200/2048 Ω 3Ω 1/2048 Ω RZCD,FB,1 FB ZCD upper resistor 120 kΩ 50 Ω 200 kΩ 50 Ω RZCD,FB,2 FB ZCD shunt resistor 7.5 kΩ 50 Ω 100 kΩ 50 Ω RVS,1 VS upper resistor for bus voltage measurement 9.96 MΩ 500 kΩ 15 MΩ 500 Ω RVS,2 VS shunt resistor for bus voltage measurement 52.3 kΩ 22 kΩ 100 kΩ 50 Ω RHV HV resistor 100 kΩ 47 kΩ 130 kΩ 50 Ω Vout,offset Output voltage offset (e.g. voltage drop from secondary diode) -0.625 V -4.000 V 4.000 V 0.125 V VGBFB FB gate driver voltage high level 10.5 V 4.5 V 15 V1) 1.5 V IGBFB FB gate driver strength 100 mA 100 mA 500 mA Selected steps VGBPFC PFC gate driver voltage high level 10.5 V 4.5 V 15 V2) 1.5 V IGBPFC PFC gate driver strength 100 mA 30 mA 150 mA Selected steps Table 3 Parameters for PFC Protections Symbol Description Example Minimum Value Maximum Value Granularity tblank,Vbus,OVP 2 Blanking time for bus overvoltage threshold, level 2 200 ns 0s 640 ns 1 / fmclk tblank,Vbus,OVP Blanking time for bus overvoltage threshold, level 1 1 400 us 0s 1 ms tslot Vbus,OVP1 490 V Vbus,stdy,entr, 600 V3) 1/16 V 1 ms tslot Bus overvoltage threshold, level 1 OV tblank,Vbus,UV Blanking time for bus undervoltage threshold 500 us 0s Vbus,UV Bus undervoltage threshold 300 V Vbus,start,PFC Vbus,stdy,entr,U 1/16 V V tstart,max,PFC Maximum PFC soft start time to settle the bus voltage at startup 200 ms 0s 500 ms tslot tblank,Vin,OV Blanking time for input overvoltage threshold 100 ms 0s 200 ms tslot tblank,Vin,UV Blanking time for input undervoltage threshold 100 ms 0s 200 ms tslot 1 2 3 Limited by VCC - 0.5 V Limited by VCC - 0.5 V Limited by the voltage rating of the bus capacitors Data Sheet 33 Revision 1.0 2016-11-4 XDPL8220 Digital PFC+Flyback Controller IC XDP™ Digital Power Design Support Table 3 Parameters for PFC Protections (continued) Symbol Description Example Minimum Value Maximum Value Granularity Vin,OV Input overvoltage threshold 319 Vrms Vin,start,max 424 Vrms 1/16 Vrms Vin,UV Input undervoltage threshold 76 Vrms 0V Vin,start,min 1/16 Vrms Vin,start,max Maximum input voltage at startup 307 Vrms Vin,start,min Vin,OV 1/16 Vrms Vin,start,min Minimum input voltage at startup 88 Vrms Vin,UV Vin,start,max 1/16 Vrms tblank,OCP2,PFC Blanking time for the peak current limitation, level 2 200 ns 1 / fmclk 600 ns 1 / fmclk tblank,OCP1,PFC Blanking time for the peak current limitation, level 1 200 ns 1 / fmclk 600 ns 1 / fmclk VCS,OCP1, PFC Maximum peak current voltage 0.75 V 0.1 V 1.08 V 0.125 mV tblank,CCM,PFC Blanking time for CCM protection 12 ms 0s 30 ms tslot ProtectionPF Bit-coded enabling per protection: If set to 1, protection is enabled. C,EN 0 65535 One-hot coded ProtectionPF Bit-coded reaction per protection: If set to 1, auto-restart is selected. If set to 0, C,conf1 either latch mode or stop is selected. 0 65535 One-hot coded ProtectionPF Bit-coded reaction per protection: If set to 1, fast auto restart or stop is selected. C,conf2 If set to 0, normal auto-restart or latch mode is enabled. 0 65535 One-hot coded ProtectionPF Bit-coded reaction per protection: If set to 1, limited number of restarts are C,conf3 enabled. If set to zero, unlimited restarts will be done. 0 65535 One-hot coded ProtectionPF Bit-coded reaction per protection: If set to 1, VCC charging will be enabled for C,conf4 auto-restarts. 0 65535 One-hot coded Table 4 Parameters for Flyback Protections Symbol Description Example Minimum Value Maximum Value Granularity Vout,UV Output undervoltage threshold 15 V 0V Vout,start 0.125 V tblank,Vout,UV Blanking time for output undervoltage 500 us 0s 1 ms tslot tstart,max,FB Maximum FB startup time to detect an output short at startup 5 ms 0s 200 ms tslot Vout,OV Output overvoltage threshold 55 V Vout,start 200 V 0.125 V tblank,Vout,OV Blanking time for output overvoltage 500 us 0s 1 ms tslot tblank,CCM Blanking time for CCM protection 500 us 0s 1 ms tslot Iout,OC Output overcurrent threshold 3A Iout,full 10 A 0.5 mA tblank,Iout,OC Blanking time for output overcurrent 500 us 0s 1 ms tslot Pout,OP Output overpower threshold 120 W Pout,set 300 W 0.5 W tblank,Pout,OP Blanking time for output overpower 500 us 0s 1 ms tslot Data Sheet 34 Revision 1.0 2016-11-4 XDPL8220 Digital PFC+Flyback Controller IC XDP™ Digital Power Design Support Table 4 Parameters for Flyback Protections (continued) Symbol Description Example Minimum Value Maximum Value Granularity tblank,Vbus,FB Blanking time for bus voltage plausibility check 500 us 0s 1 ms tslot tblank,CSFB2GN Blanking time for the CSFB-to-GNDshort check D 100 us 0s 500 us tslot tblank,TOSC,FB 40 ms 0 ms 100 ms 20 ms ProtectionFB, Bit-coded enabling per protection: If set to 1, protection is enabled. 0 65535 One-hot coded ProtectionFB, Bit-coded reaction per protection: If set to 1, auto-restart is selected. If set to 0, conf1 either latch mode or stop is selected. 0 65535 One-hot coded ProtectionFB, Bit-coded reaction per protection: If set to 1, Fast Auto-restart or Stop is conf2 selected. If set to 0, normal Auto-restart or latch mode is enabled) 0 65535 One-hot coded ProtectionFB, Bit-coded reaction per protection: If set to 1, limited number of restarts are conf3 enabled. If set to zero, unlimited restarts are enabled. 0 65535 One-hot coded ProtectionFB, Bit-coded reaction per protection: If set to 1, VCC charging will be enabled for auto-restarts. 0 65535 One-hot coded Blanking time for the tOSC,FB being overly long check EN conf4 Table 5 Parameters for General Protections Symbol Description Example Minimum Value Maximum Value Granularity VVCC,OV VCC overvoltage threshold 24.75 V 6V 24.75 V 0.125 V tblank,VCC,OV Blanking time for VCC overvoltage 5 ms 0s 10 ms tslot Protectionge Bit-coded enabling per protection: If set to 1, protection is enabled. n,EN 0 65535 One-hot coded Protectionge Bit-coded reaction per protection: If set to 1, auto-restart is selected. If set to 0, n,conf1 either latch mode or stop is selected. 0 65535 One-hot coded Protectionge Bit-coded reaction per protection: If set to 1, fast auto-restart or stop is selected. n,conf2 If set to 0, normal auto-restart or latch mode is enabled) 0 65535 One-hot coded Protectionge Bit-coded reaction per protection: If set to 1, limited number of restarts are n,conf3 enabled. If set to zero, unlimited restarts are enabled. 0 65535 One-hot coded Protectionge Bit-coded reaction per protection: If set to 1, VCC charging will be enabled for n,conf4 auto-restarts. 0 65535 One-hot coded Data Sheet 35 Revision 1.0 2016-11-4 XDPL8220 Digital PFC+Flyback Controller IC XDP™ Digital Power Design Support Table 5 Parameters for General Protections (continued) Symbol Description Example Minimum Value Maximum Value Granularity tAR Auto-restart time 1s 250 ms 4s 250 ms tAR,fast Fast auto-restart time 40 ms 5 ms 4s 5 ms NAR,max Maximum number of restarts, afterwards latch 10 0 15 1 Table 6 Parameters for Adaptive Temperature Protection Symbol Description Example Minimum Value Maximum Value Granularity Tcritical Shutoff temperature 110°C Thot 125°C 1°C Thot Temperature for thermal management 100°C 60°C Tcritical 1°C RNTC,hot NTC resistance at Thot 1500 Ω 1Ω 30000 Ω 1Ω RNTC,critical NTC resistance at Tcritical 800 Ω 1Ω 30000 Ω 1Ω tstep Current reduction time step 2s 1s 20 s 214tslot Iout,red Lowest reduced current for thermal management 200 mA Iout,min Iout,full 0.5 mA Iout,step Output current step 5 mA 0.5 mA Iout,full Iout,red 0.5 mA Table 7 Parameters for Startup and Shutdown Symbol Description Example Minimum Value Maximum Value Granularity tsoftstart Soft start time step 0.5 ms 0.1 ms 2 ms tslot V Maximum peak current voltage during startupCS, max,start,FB 0.9 V VCS,min,FB VCS,max,FB 0.125 mV VCS,CS,step Soft start voltage limit step 0.3 V 0.1 V VCS,OCP1, start 0.125 mV Vout,start Output startup voltage 10 V Vout,UV Vout,set 0.125 V tsw,start,FB Minimum switching period during startup 1 / 20 kHz tsw,min tsw,max,FB 1 / fmclk Vbus,start,FB Bus voltage FB startup threshold 350 V 0V Vbus,set 1/16 V Vbus,start,PFC Bus voltage PFC startup threshold in case of DC input 75 V 0V Vbus,UV 1/16 V Table 8 Parameters for PFC Control Loop Symbol Description Example Minimum Value Maximum Value Granularity SVPstartup PIT1 proportional gain in soft start 4 0 15 1 SVIstartup PIT1 integral gain in soft start 7 0 15 1 SVPstdy PIT1 proportional gain in steady state 4 0 15 1 SVIstdy PIT1 integral gain in steady state 7 0 15 1 Data Sheet 36 Revision 1.0 2016-11-4 XDPL8220 Digital PFC+Flyback Controller IC XDP™ Digital Power Design Support Table 8 Parameters for PFC Control Loop (continued) Symbol Description Example Minimum Value Maximum Value Granularity SVT PIT1 gain of the T1 filter 6 0 15 1 ESAT PIT1 error limitation in soft start 16384 0 32767 1 ton,max,PFC PIT1 maximum on-time limit 35 us 15 us 40 us 1 / fmclk ton,min,PFC PIT1 minimum on-time limit 200 ns 0 us tLEB,PFC 1 / fmclk tsw,max,PFC Maximum switching period 1 / 22 kHz tsw,min,PFC 1 / 20 kHz 1 / fmclk tsw,min,PFC Minimum switching period 1 / 120 kHz 1 / 200 kHz tsw,max,PFC 1 / fmclk Nvalley,max,PFC Upper boundary for valley number 5 1 5 1 tvalley,blanking, PFC Blanking time for valley change 500 us 0s 1 ms tslot Vbus,set Bus voltage setpoint 460 V Vbus,UV Vbus,OVP1 1/16 V Vbus,stdy,entr,O Bus voltage steady state entry overvoltage threshold 472 V Vbus,set Vbus,OVP1 1/16 V Vbus,stdy,entr,U Bus voltage steady state entry undervoltage threshold V 448 V Vbus,UV Vbus,set 1/16 V V Table 9 Parameters for Flyback Control Loop Symbol Description Example Minimum Value Maximum Value Granularity b0,DCM b0 gain of control loop in DCM 5353 / fmclk/256 0 8192 / fmclk/256 1 / fmclk/256 b1,DCM b1 gain of control loop in DCM -53 / fmclk/256 -8192 / fmclk/256 0 1 / fmclk/256 b0,QRM1 b0 gain of control loop in QRM1 6060 / 65536 0 V V 16384 / 65536 V 1 / 65536 V b1,QRM1 b1 gain of control loop in QRM1 -60 / 65536 V -16384 / 65536 V 0V 1 / 65536 V KP,CV Proportional gain for CV mode 1.9 0 16 0.125 KD,CV Derivative gain for CV mode 28 128 0.125 Pout,set Output power limit 100 W 0 150 W 0.5 W Iout,full Non-dimmed output current 2.0 A Iout,min 3A 0.5 mA Vout,set Output voltage setpoint 48 V Vout,UV Vout,OV 0.125 V ton,max,FB Maximum on-time limit 15 us VCS,max,FB / RCS,FB * Lp / Vbus,UV4) 25 us 1 / fmclk tsw,max,FB Maximum switching period 1 / 20 kHz tsw,min,FB 1 / 16 kHz 1 / fmclk tsw,min,FB Minimum switching period 1 / 150 kHz 1 / 150 kHz tsw,max,FB 1 / fmclk VCS,max,FB Maximum peak current voltage 1.09 V VCS,min,FB 92% * 1.214 0.125 mV V 4 Maximum on-time occurs if maximum power is transferred at minimum bus voltage. Data Sheet 37 Revision 1.0 2016-11-4 XDPL8220 Digital PFC+Flyback Controller IC XDP™ Digital Power Design Support Table 9 Parameters for Flyback Control Loop (continued) Symbol Description Example Minimum Value VCS,min,FB Minimum peak current voltage 0.4 V tdemag,min,FB VCS,max,FB * Np / Ns * Vout,OV / Lp * RCS,FB 5) 0.125 mV Table 10 Maximum Value Granularity Parameters for Dimming Symbol Description Example Minimum Value Maximum Value Granularity DDIM,max PWM duty cycle for maximum current 90% 5% 95% 0.25% DDIM,min PWM duty cycle for minimum current 10% 5% 95% 0.25% DDIM,on PWM duty cycle to exit dim-to-off 5% 5% 95% 0.25% DDIM,off PWM duty cycle to enter dim-to-off 5% 5% 95% 0.25% tblank,DIM,off Blanking time until when the PWM input 1 ms has to be available before dim-to-off is triggered 0 ms 10 ms tslot NDIM Integer dimming curve coefficient 1 1 2 1 Iout,min Minimum output current 20 mA 20 mA Iout,full 0.5 mA n_PWM_hys PWM detection hysteresis to suppress jitter in the PWM signal 0 6 40 1 Table 11 Parameters for Fine Tuning Symbol Description Example Minimum Value Maximum Value Granularity Kcoupling FB transformer coupling coefficient 0.98 0.5 2 0.001 tLEB,FB FB Current sense leading edge blanking 200 ns 1 / fmclk 600 ns 1 / fmclk tOCP2,FB FB OCP2 blanking time 250 ns 1 / fmclk 63 / fmclk 1 / fmclk tPDC FB Propagation delay compensation 500 ns tOCP1,FB 2 us 1 / fmclk tOCP1,FB FB OCP1 spike suppression filter 100 ns 50 ns 500 ns 1 / fmclk tCSFB,offset FB sampling offset 200 ns 50 ns 500 ns 1 / fmclk tsw,hysteresis FB switching period hysteresis for QRM/DCM mode changes 600 ns 20 ns 1000 ns 1 / fmclk trsup,FB FB ZCD ringing suppression 1.2 us 1 / fmclk 2 us 1 / fmclk tZCD,PD,FB FB Delay of zero-crossing signal 200 ns 0s 1 us 1 / fmclk tZCD,PD,RE,FB FB Rising edge delay of zero-crossing signal 450 ns 0s 1 us 1 / fmclk tgate,on FB Turn-on delay of MOSFET 100 ns 0s 1 us 1 / fmclk tLEB,PFC PFC On-time leading edge blanking 200 ns 1 / fmclk 600 ns 1 / fmclk 5 The minimum peak current must ensure that tdemag,min,FB is maintained. Data Sheet 38 Revision 1.0 2016-11-4 XDPL8220 Digital PFC+Flyback Controller IC XDP™ Digital Power Design Support Table 11 Parameters for Fine Tuning (continued) Symbol Description Example Minimum Value Maximum Value Granularity tZCD,PD,PFC PFC Delay of 0.5 V crossing to real zerocrossing signal 42 ns -1 us 1 us 1 / fmclk Ntosc,upd,PFC PFC AC half cycle number to take oscillation measurement 0 0 255 1 tosc,init,PFC PFC Oscillation period initialization value 1.5 us 0s 8 us 1 / fmclk tosc,delay,PFC PFC Delay after zero-crossing to measure oscillation period 2 ms 0s 12 ms tslot ki,PFC PFC THD optimization coefficient 0.75 0 16 0.125 tsrc,blanking,PF C Blanking time for AC/DC source change 12 ms 12 ms 30 ms 1 ms trms,reset,PFC Reset time of RMS search 20 ms tsrc,blanking,PF 30 ms 1 ms C 4.3 List of Fixed Parameters This list shows the fixed parameters and their associated values – i.e. parameters whose values cannot be changed. Table 12 List of Fixed Parameters Symbol Description Value VCS,OCP2 Primary overcurrent protection 1.619 V tdemag,min,FB FB minimum demagnetizing time 2.0 us VUVOFF VCC undervoltage threshold 6.07 V fmclk Main clock frequency 50.0 MHz tslot Firmware task scheduling interval 32 us VREF Internal reference voltage 2.428 V kpktorms Constant to convert from peak to RMS values 0.707 (approx. 181/256) CIIR,PFC Coefficient of the IIR LP filter for bus voltage 4 Data Sheet 39 Revision 1.0 2016-11-4 XDPL8220 Digital PFC+Flyback Controller IC XDP™ Digital Power Electrical Characteristics and Parameters 5 Electrical Characteristics and Parameters All signals are measured with respect to the ground pin, GND. The voltage levels are valid provided other ratings are not violated. 5.1 Package Characteristics Table 13 Package Characteristics Parameter Symbol Thermal resistance for PGDSO-16 5.2 RthJA Limit Values Unit min max — 119 Remarks K/W Absolute Maximum Ratings Attention: Stresses above the values listed above may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. These values are not tested during production test. Table 14 Absolute Maximum Ratings Parameter Symbol Limit Values min max Unit Remarks Voltage externally supplied to pin VCC VVCCEXT –0.5 26 V voltage that can be applied to pin VCC by an external voltage source Voltage at pin GDx VGDx –0.5 VVCC + 0.3 V if gate driver is not configured for digital I/O Junction temperature TJ –40 125 °C max. operating frequency 66 MHz fMCLK Storage temperature TS –55 150 °C Soldering temperature TSOLD — 260 °C Wave Soldering 1) Latch-up capability ILU — 150 mA 2) Pin voltages acc. to abs. ESD capability HBM VHBM — 2000 V 3) ESD capability CDM VCDM — 500 V 4) 1 2 3 4 max. ratings According to JESD22-A111 Rev A. Latch-up capability according to JEDEC JESD78D, TA= 85°C. ESD-HBM according to ANSI/ESDA/JEDEC JS-001-2012. ESD-CDM according to JESD22-C101F. Data Sheet 40 Revision 1.0 2016-11-4 XDPL8220 Digital PFC+Flyback Controller IC XDP™ Digital Power Electrical Characteristics and Parameters Table 14 Absolute Maximum Ratings (continued) Parameter Symbol Limit Values min max Unit Remarks Input Voltage Limit VIN –0.5 3.6 V Voltage externally supplied to pins GPIO, MFIO, CS, ZCD, GPIO, VS, GDx (if GDx is configured as digital I/O). (If not stated different) Maximum permanent negative clamping current for ZCD and CS –ICLN_DC — 2.5 mA RMS Maximum transient negative –ICLN_TR clamping current for ZCD and CS — 10 mA pulse < 500ns Maximum negative transient –VIN_ZCD input voltage for ZCD — 1.5 V pulse < 500ns Maximum negative transient –VIN_CS input voltage for CS — 3.0 V pulse < 500ns Maximum permanent ICLP_DC positive clamping current for CS — 2.5 mA RMS Maximum transient positive clamping current for CS ICLP_TR — 10 mA pulse < 500ns Maximum current into pin VIN IAC — 10 mA for charging operation Maximum sum of input ICLH_sum clamping high currents for digital input stages of device — 300 µA limits for each individual digital input stage have to be respected Voltage at HV pin -0.5 600 V 5.3 VHV Operating Conditions The recommended operating conditions are shown for which the DC Electrical Characteristics are valid. Table 15 Operating Range Parameter Symbol Limit Values Unit min max Remarks Ambient temperature TA –40 85 °C Junction Temperature TJ –40 125 °C max. 66 MHz fMCLK Lower VCC limit VVCC VUVOFF — V device is held in reset when VVCC < VUVOFF Voltage externally supplied to VCC pin VVCCEXT — 24 V maximum voltage that can be applied to pin VCC by an external voltage source Gate driver pin voltage VGD –0.5 VVCC + 0.3 V Data Sheet 41 Revision 1.0 2016-11-4 XDPL8220 Digital PFC+Flyback Controller IC XDP™ Digital Power Electrical Characteristics and Parameters 5.4 DC Electrical Characteristics The electrical characteristics provide the spread of values applicable within the specified supply voltage and junction temperature range, TJ from -40 °C to +125 °C. Devices are tested in protection at TA = 25 °C. Values have been verified either with simulation models or by device characterization up to 125 °C. Typical values represent the median values related to TA = 25 °C. All voltages refer to GND, and the assumed supply voltage is VVCC = 18 V if not otherwise specified. Note: Not all values given in the tables are tested during production testing. Values not tested are explicitly marked. Attention: The Vcc pin voltage must be higher than 3.4V before the voltage of any other pins (except GND and HV pins) exceeds 1.2V. Table 16 Power Supply Characteristics Parameter Symbol Values Min. Unit Note or Test Condition Typ. Max. VCC_ON threshold VVCCon — VSELF — V Self-powered startup (default) VCC_ON_SELF threshold VSELF 19 20.5 22 V dVVCC/dt = 0.2 V/ms VCC_ON_SELF delay tSELF — — 2.1 µs Reaction time of VVCC monitor VCC_UVOFF current IVCCUVOFF 5 20 40 µA VVCC < VSELF(min) - 0.3 V or VVCC < VEXT(min) 0.3 V5) UVOFF threshold VUVOFF — 6.0 — V SYS_CFG0.SELUVTHR = 0 0B UVOFF threshold tolerance ΔUVOFF — — ±5 % This value defines the tolerance of VUVOFF UVOFF filter constant tUVOFF 600 — — ns 1V overdrive UVLO (UVWAKE) threshold VUVLO — VUVOFF · 1.25 — V UVWAKE threshold tolerance ΔUVLO — — ±5 % This value defines the tolerance of VUVLO UVLO (UVWAKE) filter constant tUVLO 0.6 — 2.2 µs 1 V overdrive OVLO (OVWAKE) threshold VOVLO — VSELF — V OVLO (OVWAKE) filter constant tOVLO 0.6 — 2.4 µs 5 1 V overdrive Tested at VVCC = 5.5 V Data Sheet 42 Revision 1.0 2016-11-4 XDPL8220 Digital PFC+Flyback Controller IC XDP™ Digital Power Electrical Characteristics and Parameters Table 16 Power Supply Characteristics (continued) Parameter Symbol Values Min. Unit Note or Test Condition Typ. Max. VDDP voltage VVDDP 3.04 3.20 3.36 V At PMD0/PSMD1. Some internal values refer to VVDDP / VVDDA and VVDDPPS / VVDDAPS respectively. VDDA voltage VVDDA 3.20 3.31 3.42 V At PMD0/PSMD1. Some internal values refer to VVDDP / VVDDA and VVDDPPS / VVDDAPS respectively. Nominal range 0% to 100% VADCVCC 0 — VREF V VADCVCC = 0.09 · VVCC6) Reduced VCC range for ADC measurement RADCVCC 8 — 92 % 7)8) Maximum error for ADC measurement (8-bit result) TET0VCC — — 3.8 LSB8 Maximum error for ADC measurement (8-bit result) TET256VCC — — 5.2 LSB8 Gate driver current consumption excl. gate charge current IVCCGD — 0.26 0.35 mA Tj ≤ 125°C VCC quiescent current in PMD0 IVCCPMD0 — 11 13 mA All registers have reset values, clock is active at 66 MHz, CPU is stopped, Tj ≤ 85 °C VCC quiescent current in PMD0 IVCCPMD0 — — 14.5 mA All registers have reset values, clock is active at 66 MHz, CPU is stopped, Tj ≤ 125 °C VCC quiescent current in power saving mode PSDM3 with standby logic active IVCCPSMD3 — 0.25 0.45 mA Tj ≤ 125 °C WU_PWD_CFG = 28H VCC quiescent current in power saving mode PSDM4 with standby logic active IVCCPSMD4 — 0.14 0.23 mA Tj ≤ 125 °C WU_PWD_CFG = 00H 6 7 8 Theoretical minimum value, real minimum value is related to VUVOFF threshold. Operational values. Note that the system is turned off if VVCC < VUFOFF. Data Sheet 43 Revision 1.0 2016-11-4 XDPL8220 Digital PFC+Flyback Controller IC XDP™ Digital Power Electrical Characteristics and Parameters Table 17 Electrical Characteristics of the GDFB Pin Parameter Symbol Values Min. Unit Note or Test Condition Typ. Max. Input clamping current, low –ICLL — — 100 µA only digital input Input clamping current, high ICLH — — 100 µA only digital input APD low voltage (active VAPD pull-down while device is not powered or gate driver is not enabled) — — 1.6 V IGD = 5 mA RPPD value RPPD — 600 — kΩ Permanent pull-down resistor inside gate driver RPPD tolerance ΔPPD — — ±25 % Permanent pull-down resistor inside gate driver Driver output low impedance for GD0 RGDL — — 4.4 Ω TJ ≤ 125 °C, IGD = 0.1 A Nominal output high voltage in PWM mode VGDH — 10.5 — V GDx_CFG.VOL = 3, IGDH = –1 mA Output voltage tolerance ΔVGDH — — ±5 % Tolerance of programming options if VGDH > 10 V, IGDH = –1 mA Rail-to-rail output high voltage VGDHRR VVCC– 0.5 — VVCC V If VVCC < programmed VGDH and output at high state Output high current in PWM mode for GD0 –IGDH — 100 — mA GDx_CFG.CUR = 8 Output high current tolerance in PWM mode ΔIGDH — ±15 % Calibrated 9) Discharge current for GD0 IGDDIS 800 — — mA VGD = 4 V and driver at low state Output low reverse current –IGDREVL — — 100 mA Applies if VGD < 0 V and driver at low state Output high reverse current in PWM mode IGDREVH — 1/6 of IGDH — 9 Applies if VGD > VGDH + 0.5 V (typ) and driver at high state referred to GDx_CFG.CUR = 16 Data Sheet 44 Revision 1.0 2016-11-4 XDPL8220 Digital PFC+Flyback Controller IC XDP™ Digital Power Electrical Characteristics and Parameters Table 18 Electrical Characteristics of the CSFB Pin Parameter Symbol Values Min. Input voltage operating range Typ. Max. –0.5 — 3.0 V OCP2 comparator VOCP2 reference voltage, derived from VVDDA, given values assuming VVDDA = VVDDA,typ — 1.6 — V SYS_CFG0.OCP2 = 00B Threshold voltage tolerance ΔVOCP2 — — ±5 % Voltage divider tolerance Comparator propagation tOCP2PD delay 15 — 35 ns Minimum comparator input pulse width tOCP2PW — — 30 ns OCP2F comparator propagation delay tOCP2FPD 70 — 170 ns dVCS/dt = 100 V/µs Delay from VCS crossing VCSOCP2 to begin of GDx turn-off (IGD0 > 2mA) tCSGDxOCP2 125 135 190 ns dVCS/dt = 100 V/µs; fMCLK = 66 MHz. GDx driven by QR_GATE FIL_OCP2.STABLE = 3 OCP1 operating range VOCP1 0 — VREF/2 V RANGE =00B OCP1 threshold at full scale setting (CS_OCP1LVL=FFH) for CS0 VOCP1FS 1192 1229 1266 mV RANGE =00B Delay from VCS crossing VCSOCP1 to CS_OCP1 rising edge, 1.2 V range tCSOCP1 90 170 250 ns Input signal slope dVCS/ dt = 150 mV/µs. This slope represents a use case of a switch-mode power supply with minimum input voltage. Delay from CS_OCP1 rising edge to QR_GATE falling edge tOCP1GATE — — 12 ns STB_RET31. OCP_ASM_SEL=0 Delay from QR_GATE falling edge to start of GDx turn-off tGATEGDx 1 3 5 ns GDx driven by QR_GATE. Measured up to IGDx > 2 mA OCP1 comparator input single pulse width filter tOCP1PW 60 — 95 ns Shorter pulses than min. are suppressed, longer pulses than max. are passed Data Sheet VINP Unit Note or Test Condition 45 Revision 1.0 2016-11-4 XDPL8220 Digital PFC+Flyback Controller IC XDP™ Digital Power Electrical Characteristics and Parameters Table 18 Electrical Characteristics of the CSFB Pin (continued) Parameter Symbol Values Min. Unit Note or Test Condition Typ. Max. Nominal S&H operating range 0% to 100% VCSH 0 — VREF/2 V CS_ICR.RANGE =00B Reduced S&H operating range RRCVSH 8 — 92 % CS_ICR.RANGE =00B Operational values Maximum error of CS0 S&H for corrected measurement (8-bit result) TET0CS0S — — 4.7 LSB CS_ICR.RANGE =00B Maximum error of CS0 S&H for corrected measurement (8-bit result) TET256CS0S — — 6.0 LSB CS_ICR.RANGE =00B Nominal S&H operating range 0% to 100% VCSH 0 — VREF/6 V CS_ICR.RANGE =11B Reduced S&H operating range RRCVSH 20 — 80 % CS_ICR.RANGE =11B Operational values Maximum error of CS0 S&H for corrected measurement (8-bit result) TET0CS0S — — 8.0 LSB CS_ICR.RANGE =11B Maximum error of CS0 S&H for corrected measurement (8-bit result) TET256CS0S — — 8.7 LSB CS_ICR.RANGE =11B — 510 ns Referring to jump in input voltage. Limits the minimum gate driver Ton time. S&H delay of input buffer tCSHST Table 19 — Electrical Characteristics of the ZCD Pin Parameter Symbol Values Min. Unit Note or Test Condition Typ. Max. Input voltage operating range VINP –0.5 — 3.3 V Input clamping current, high ICLH — — 100 µA Zero-crossing threshold VZCTHR 15 40 70 mV 30 50 70 ns Comparator propagation tZCPD delay Data Sheet 46 dVZCD/dt = 4 V/µs Revision 1.0 2016-11-4 XDPL8220 Digital PFC+Flyback Controller IC XDP™ Digital Power Electrical Characteristics and Parameters Table 19 Electrical Characteristics of the ZCD Pin (continued) Parameter Symbol Values Min. Unit Note or Test Condition Typ. Max. Input voltage negative clamping level –VINPCLN 140 180 220 mV Analog clamp activated Nominal I/V-conversion operating range 0% to 100% –IIV 0 — 4 mA CRNG =00B Gain = 600 mV/mA Reduced I/V-conversion operating range RRIV 5 — 80 % Maximum error for corrected ADC measurement (8-bit result) TET0IV — — 4.1 LSB8 CRNG =00B Maximum error for corrected ADC measurement (8-bit result) TET256IV — — 9.7 LSB8 CRNG =00B Maximum deviation between ZCD clamp voltage and trim result stored in OTP EZCDClp — — ±5 % –IIV > 0.25 mA IV-conversion delay of input buffer tIVST — — 900 ns Refers to jump in input current10) Nominal S&H input voltage range 0% to 100% VZSH 0 — 2/3 · VREF V SHRNG =0B Nominal S&H input voltage range 0% to 100% VZSH VREF /2 — 7/6 · VREF V SHRNG =1B Reduced S&H input voltage range RRZVSH 4 — 95 % Maximum error for corrected ADC measurement (8-bit result) TET0ZVS0 — — 3.7 LSB8 SHRNG =0B Maximum error for corrected ADC measurement (8-bit result) TET256ZVS0 — — 4.9 LSB8 SHRNG =0B 10 Limits the minimum gate driver Ton time. Data Sheet 47 Revision 1.0 2016-11-4 XDPL8220 Digital PFC+Flyback Controller IC XDP™ Digital Power Electrical Characteristics and Parameters Table 19 Electrical Characteristics of the ZCD Pin (continued) Parameter Symbol Values Min. Unit Note or Test Condition Typ. Max. Maximum error for corrected ADC measurement (8-bit result) TET0ZVS1 — — 4.2 LSB8 SHRNG =1B Maximum error for corrected ADC measurement (8-bit result) TET256ZVS1 — — 5.8 LSB8 SHRNG =1B S&H delay of input buffer tZSHST referring to jump of input voltage — — 1.0 µs SHRNG =0BTj ≤ 125 °C S&H delay of input buffer tZSHST referring to jump of input voltage — — 1.6 µs SHRNG =1BTj ≤ 125 °C Table 20 Electrical Characteristics of the VS Pin Parameter Symbol Values Min. Unit Note or Test Condition Typ. Max. Nominal measurement range 0% to 100% VVS 0 — VREF V Gain 1, no offset Nominal measurement range 0% to 100% VVS 5/6·VREF — 7/6·VREF V Gain 3, with offset Reduced operating range RRVVS 5 — 95 % Gain 1, no offset Reduced operating range RRVVS 10 — 90 % Gain 3, with offset Maximum error for corrected measurement (8-bit result) TET0VS — — 4.1 LSB8 Range 1, no offset Maximum error for corrected measurement (8-bit result) TET256VS — — 5.6 LSB8 Range 1, no offset Maximum error for corrected measurement (8-bit result) TET0VS — — 12.0 LSB8 Range 2, with offset Maximum error for corrected measurement (8-bit result) TET256VS — — 12.9 LSB8 Range 2, with offset Overvoltage comparator threshold THROV 2.70 2.8 2.90 V Overvoltage comparator propagation delay tPDOV — — 300 µs Data Sheet 48 Step at input Revision 1.0 2016-11-4 XDPL8220 Digital PFC+Flyback Controller IC XDP™ Digital Power Electrical Characteristics and Parameters Table 21 Electrical Characteristics of the HV Pin Parameter Symbol Values Min. Leakage current at HV pin Typ. Max. — — 10 µA VHV = 600 V HV startup cell disabled Nominal current for IMEAS measurement path 0% to 100% 0 — 4.8 mA CURRNG = 10B Reduced measurement range for current path RRIMEAS 5 — 80 % CURRNG = 10B. Operational values. Maximum error for corrected ADC measurement (8-bit result, temperature gain correction applied) TET0DP — — 3.7 LSB8 CURRNG = 10B Maximum error for corrected ADC measurement (8-bit result, temperature gain correction applied) TET256DP — — 7.9 LSB8 CURRNG = 10B Comparator threshold (in THRCOMP % of full range of IMEAS) 15 20 25 % COMPTHR= 00B Comparator threshold (in THRCOMP % of full range of IMEAS) 25 30 35 % COMPTHR= 01B Comparator threshold (in THRCOMP % of full range of IMEAS) 35 40 45 % COMPTHR= 10B Comparator threshold (in THRCOMP % of full range of IMEAS) 45 50 55 % COMPTHR= 11B Table 22 IHVleak Unit Note or Test Condition Electrical Characteristics of the PWM Pin Parameter Symbol Values Min. Unit Note or Test Condition Typ. Max. Input capacitance CINPUT — — 10 pF Input low voltage VIL — — 1.0 V Input high voltage VIH 2.0 — — V Input leakage current, no ILK pull device –5 — +1 µA VMFIO = 0 V / 3 V Input low current with –ILPU active weak pull-up WPU 30 — 90 µA Measured at max. VIL Input high current with active weak pull-down WPD 90 — 300 µA Measured at min. VIH Data Sheet IHPD 49 Revision 1.0 2016-11-4 XDPL8220 Digital PFC+Flyback Controller IC XDP™ Digital Power Electrical Characteristics and Parameters Table 22 Electrical Characteristics of the PWM Pin (continued) Parameter Symbol Values Min. Unit Note or Test Condition Typ. Max. Max. input frequency fINPUT 15 — — MHz Pull-up resistor value RPU — 2.25 — kΩ RPU=1111B Pull-up resistor tolerance ΔRPU — — ±20 % Overall tolerance PWM input frequency fPWM 500 — 2000 Hz PWM duty cycle DPWM 5 — 95 % Table 23 Electrical Characteristics of the TEMP Pin Parameter Symbol Values Min. Unit Note or Test Condition Typ. Max. MFIO reference voltage VMFIOREF — VREF — V Selection = VREF Nominal range 0% to 100% VMFIO 0 — VREF V Gain = 1 Reduced operating range RRVMFIO 4 — 96 % Gain = 1. Operational values. Maximum error for corrected measurement (8-bit result) TET0MFI0 — — 4.0 LSB8 Gain = 1 Maximum error for corrected measurement (8-bit result) TET256MFI0 — — 4.8 LSB8 Gain = 1 Offset calibration voltage VCAL — VMFIOREF/8 — V Offset calibration voltage ΔVCAL absolute tolerance — — ±3 LSB Ref. to VMFIOREF =VREF, Gain = 1 Offset calibration voltage ΔVCAL_TMP variation over temperature — — ±1 LSB Ref. to VMFIOREF =VREF, Gain = 1 Pull-up resistor value — 11 — kΩ RPU=0110B — — ±20 % Overall tolerance RPU Pull-up resistor tolerance ΔRPU Table 24 Electrical Characteristics of the CSPFC Pin Parameter Symbol Values Min. Unit Note or Test Condition Typ. Max. Input voltage operating range VINP –0.5 — 3.0 V OCP1 operating range VOCP1 0 — VREF/2 V Data Sheet 50 RANGE =00B Revision 1.0 2016-11-4 XDPL8220 Digital PFC+Flyback Controller IC XDP™ Digital Power Electrical Characteristics and Parameters Table 24 Electrical Characteristics of the CSPFC Pin (continued) Parameter Symbol Values Min. Unit Note or Test Condition Typ. Max. OCP2 comparator VOCP2 reference voltage, derived from VVDDA, given values assuming VVDDA = VVDDA,typ — 1.6 — V SYS_CFG0.OCP2 = 00B Threshold voltage tolerance ΔVOCP2 — — ±5 % Voltage divider tolerance Comparator propagation tOCP2PD delay 15 — 35 ns Minimum comparator input pulse width tOCP2PW — — 30 ns OCP2F comparator propagation delay tOCP2FPD 70 — 170 ns dVCS/dt = 100 V/µs Delay from VCS crossing VCSOCP2 to begin of GDx turn-off (IGD0 > 2mA) tCSGDxOCP2 125 135 190 ns dVCS/dt = 100 V/µs; fMCLK = 66 MHz. GDx driven by QR_GATE FIL_OCP2.STABLE = 3 Nominal S&H operating range 0% to 100% VCSH 0 — VREF/2 V CS_ICR.RANGE =00B Reduced S&H operating range RRCVSH 4 — 90 % Operational values Hysteretic comparator threshold THRHYS — 0.54 — V 1 → 0 transition Hysteretic comparator threshold THRHYS — 1.53 — V 0 → 1 transition Hysteretic comparator threshold tolerance ΔTHRHYS — — ±120 mV Hysteretic comparator propagation delay tPDHYS — 90 — ns Rising edge Hysteretic comparator propagation delay tPDHYS — 40 — ns Falling edge Hysteretic comparator minimum input pulse width tPWHYS — — 300 ns Data Sheet 51 Revision 1.0 2016-11-4 XDPL8220 Digital PFC+Flyback Controller IC XDP™ Digital Power Electrical Characteristics and Parameters Table 25 Electrical Characteristics of the UART Pin Parameter Symbol Values Min. Unit Note or Test Condition Typ. Max. Input clamping current, low –ICLL — — 100 µA only digital input Input clamping current, high ICLH — — 100 µA only digital input APD low voltage (active VAPD pull-down while device is not powered or gate driver is not enabled) — — 1.6 V IGD = 5 mA Input capacitance CINPUT — — 25 pF Input low voltage VIL — — 1.0 V Input high voltage VIH 2.1 — — V Input low current with –ILPU active weak pull-up WPU 30 — 90 µA Max. input frequency fINPUT 15 — — MHz Output low voltage VOL — — 0.8 V IOL = 2 mA Output high voltage VOH 2.4 — — V IOH = –2 mA Output sink current IOL — — 2 mA Output source current -IOH — — 2 mA Output rise time (0 → 1) tRISE — — 50 ns 20 pF load, push/pull output Output fall time (1 → 0) tFALL — — 50 ns 20 pF load, push/pull or open-drain output Max. output switching frequency fSWITCH 10 — — MHz UART baudrate fUART 9600 105000 baud Table 26 Measured at max. VIL Electrical Characteristics of the GDPFC Pin Parameter Symbol Values Min. Unit Note or Test Condition Typ. Max. Input clamping current, low –ICLL — — 100 µA only digital input Input clamping current, high ICLH — — 100 µA only digital input APD low voltage (active VAPD pull-down while device is not powered or gate driver is not enabled) — — 1.6 V IGD = 5 mA Data Sheet 52 Revision 1.0 2016-11-4 XDPL8220 Digital PFC+Flyback Controller IC XDP™ Digital Power Electrical Characteristics and Parameters Table 26 Electrical Characteristics of the GDPFC Pin (continued) Parameter Symbol Values Min. Unit Note or Test Condition Typ. Max. RPPD value RPPD — 600 — kΩ Permanent pull-down resistor inside gate driver RPPD tolerance ΔPPD — — ±25 % Permanent pull-down resistor inside gate driver Driver output low impedance for GD1/2 RGDL — — 7.0 Ω TJ ≤ 125 °C, IGD = 0.1 A Nominal output high voltage in PWM mode VGDH — 10.5 — V GDx_CFG.VOL = 3, IGDH = –1 mA Output voltage tolerance ΔVGDH — — ±5 % Tolerance of programming options if VGDH > 10 V, IGDH = –1 mA Rail-to-rail output high voltage VGDHRR VVCC– 0.5 — VVCC V If VVCC < programmed VGDH and output at high state Output high current in PWM mode for GD1/2 –IGDH — 104 — mA GDx_CFG.CUR = 24 Output high current tolerance in PWM mode ΔIGDH — ±15 % Calibrated 11) Discharge current for GD1/2 IGDDIS 500 — — mA VGD = 4 V and driver at low state Output low reverse current –IGDREVL — — 100 mA Applies if VGD < 0 V and driver at low state Output high reverse current in PWM mode IGDREVH — 1/6 of IGDH — Table 27 Electrical Characteristics of the A/D Converter Parameter Symbol Values Min. Integral non-linearity 11 12 Applies if VGD > VGDH + 0.5 V (typ) and driver at high state INL — Unit Note or Test Condition Typ. — Max. 1 LSB8 12) referred to GDx_CFG.CUR = 16 ADC capability measured via channel MFIO without errors due to switching of neighbouring pins, e.g. gate drivers, measured with STC = 5. MFIO buffer non-linearity masked out by taking ADC output values ≥ 30 only. Data Sheet 53 Revision 1.0 2016-11-4 XDPL8220 Digital PFC+Flyback Controller IC XDP™ Digital Power Electrical Characteristics and Parameters Table 28 Electrical Characteristics of the Reference Voltage Parameter Symbol Values Min. Unit Note or Test Condition Typ. Max. Reference voltage VREF — 2.428 — V VREF overall tolerance ΔVREF — — ±1.5 % Table 29 Trimmed, Tj ≤ 125 °C and aging Electrical Characteristics of the OTP Programming Parameter Symbol Values Min. Unit Note or Test Condition Typ. Max. OTP programming VPP voltage at the VCC pin for range C000H to CFFFH 7.35 7.5 7.65 V Operational values OTP programming VPP voltage at the VCC pin for range D000H to DFFFH 9.0 — VVCC V Operational values OTP programming current — 1.6 — mA Programming of 4 bits in parallel Table 30 IPP Electrical Characteristics of the Clock Oscillators Parameter Symbol Values Min. Unit Note or Test Condition Typ. Max. Master clock oscillation period including all variations tMCLK 19.2 20.0 21.1 ns In reference to 50 MHz fMCLK Main clock oscillator frequency variation of stored DPARAM frequency ΔMCLK –3.2 — +2.0 % Temperature drift and aging only, 50 MHz fMCLK Standby clock oscillator frequency fSTBCLK 96 100 104 kHz Trimming tolerance at TA = 25 °C Standby clock oscillator frequency fSTBCLK 90 100 110 kHz Overall tolerance Table 31 Electrical Characteristics of the Temperature Sensor Parameter Symbol Values Min. Unit Note or Test Condition Typ. Max. Temperature sensor ADC ADCTEMP output operating range 0 — 190 LSB ADCTEMP = 40 + temperature / °C) Temperature sensor tolerance — — ±6 K Incl. ADC conversion accuracy at 3 σ Data Sheet ΔTEMP 54 Revision 1.0 2016-11-4 XDPL8220 Digital PFC+Flyback Controller IC XDP™ Digital Power Package Dimensions 6 Package Dimensions The package dimensions of PG-DSO-16 are provided. Figure 29 Package Dimensions for PG-DSO-16 Note: Dimensions in mm. Note: You can find all of our packages, packing types and other package information on our Infineon Internet page “Products”: http://www.infineon.com/products. Data Sheet 55 Revision 1.0 2016-11-4 XDPL8220 Digital PFC+Flyback Controller IC XDP™ Digital Power References 7 References 1. Infineon Technologies AG: XDPL8220 Reference Board Test Report 2. Infineon Technologies AG: .dp Interface Gen2: Can be ordered at http://ehitex.com/programmer/486/.dpinterface-board-gen2 3. Infineon Technologies AG: .dp Vision User Manual 4. Infineon Technologies AG: .dp Interface Gen2 User Manual 5. Infineon Technologies AG: XDPL8220 Design Guide 6. Infineon Technologies AG: XDPL8220 Programming Manual Abbreviations AC Alternating Current (AC) An Alternating Current is a form of power supply in which the flow of electric charge periodically reverses direction. ADC Analog-to-Digital Converter (ADC) An analog-to-digital converter is a device that converts a continuous physical quantity (usually voltage) to a digital number that represents the quantity's amplitude. BOM Bill of Materials (BOM) A bill of materials is a list of the raw materials, sub-assemblies, intermediate assemblies, sub-components, parts and the quantities of each needed to manufacture an end product. CC Constant Current (CC) Constant Current is a mode of a power supply in which the output current is kept constant regardless of the load. CCM Continuous Conduction Mode (CCM) Continuous Conduction Mode is an operational mode of a switching power supply in which the current is continuously flowing and does not return to zero. CRC Cyclic Redundancy Check (CRC) A cyclic redundancy check is an error-detecting code commonly used to detect accidental changes to raw data. CV Constant Voltage (CV) Constant Voltage is a mode of a power supply in which the output voltage is kept constant regardless of the load. DAC Digital-to-Analog Converter (DAC) A digital-to-analog converter is a device that converts digital data into an analog signal (typically voltage). DC Direct Current (DC) A Direct Current is a form of power supply in which the flow of electric charge is only into one direction. Data Sheet 56 Revision 1.0 2016-11-4 XDPL8220 Digital PFC+Flyback Controller IC XDP™ Digital Power Abbreviations DCM Discontinuous Conduction Mode (DCM) Discontinuous Conduction Mode is an operational mode of a switching power supply in which the current starts and returns to zero. ECG Electronic Control Gear (ECG) An electronic control gear is a power supply which provides one or more light module(s) with the appropriate voltage or current. FB Flyback (FB) A flyback converter is a power converter with the inductor split to form a transformer, so that the voltage ratios are multiplied with an additional advantage of galvanic isolation between the input and any outputs. FW Firmware (FW) A proprietary software exploiting a set of functions. GUI Graphic User Interface (GUI) A graphical user interface is a type of interface that allows users to interact with electronic devices through graphical icons and visual indicators. HW Hardware (HW) The collection of physical elements that comprise a computer system. IC Integrated Circuit (IC) A miniaturized electronic circuit that has been manufactured in the surface of a thin substrate of semiconductor material. An IC may also be referred to as micro-circuit, microchip, silicon chip, or chip. IIR Infinite Impulse Response (IIR) Infinite impulse response is a property applying to many linear time-invariant systems. Common examples of linear time-invariant systems are most electronic and digital filters. Systems with this property have an impulse response which does not become exactly zero past a certain point, but continues indefinitely. LED Light Emitting Diode (LED) A light-emitting diode is a two-lead semiconductor light source which emits light when activated. LP Limited Power (LP) Limited Power is a mode of a power supply in which the output power is limited regardless of the load. NTC Negative Temperature Coefficient Thermistor (NTC) A negative temperature coefficient thermistor is a type of resistor whose resistance declines over temperature. OCP1 Overcurrent Protection Level 1 (OCP1) The Overcurrent Protection Level 1 is limiting the current in a switched-mode power supply to limit the power delivered to the output of the power supply. Data Sheet 57 Revision 1.0 2016-11-4 XDPL8220 Digital PFC+Flyback Controller IC XDP™ Digital Power Abbreviations OCP2 Overcurrent Protection Level 2 (OCP2) The Overcurrent Protection Level 2 is protecting the current in a switched-mode power supply from exceeding a maximum threshold. OTP One Time Programmable Memory (OTP) A One-Time Programmable memory is a form of memory to which data can be written once. After writing, the data is stored permanently and cannot be further changed. PF Power Factor (PF) Power factor is the ratio between the real power and the apparent power. PFC Power Factor Correction (PFC) Power factor correction increases the power factor of an AC power circuit closer to 1 which corresponds to minimizing the reactive power of the power circuit. PSR Primary Side Regulated (PSR) A Primary Side Regulated power supply is controlling its operation based on a property sensed on primary side of an isolated power supply. PWM Pulse Width Modulation (PWM) Pulse-width modulation is a technique to encode an analog value into the duty cycle of a pulsing signal with arbitrary amplitude. QRM Quasi-Resonant Mode (QRM) Quasi-Resonant Mode is an operating mode of a switched-mode power supply which maximizes efficiency. This is achieved by only switching at preferred times when switching losses are low. QRM1 Quasi-Resonant Mode, switching in valley 1 (QRM1) Quasi-Resonant Mode is an operating mode of a switched-mode power supply which maximizes efficiency. This is achieved by switching at the occurrence of the first valley of a signal which corresponds to a time when switching losses are low. QRMn Quasi-Resonant Mode, switching in valley n (QRMn) Quasi-Resonant Mode is an operating mode of a switched-mode power supply which maximizes efficiency. This is achieved by switching at the occurence of an nth valley of a signal which corresponds to a time when switching losses are low. RAM Random Access Memory (RAM) Random-access memory is a form of computer data storage which allows data items to be read and written regardless of the order in which data items are accessed. THD Total Harmonic Distortion (THD) The total harmonic distortion of a signal is a measurement of the harmonic distortion present and is defined as the ratio of the sum of the powers of all harmonic components to the power of the fundamental frequency. Data Sheet 58 Revision 1.0 2016-11-4 XDPL8220 Digital PFC+Flyback Controller IC XDP™ Digital Power Revision History UART Universal Asynchronous Receiver Transmitter (UART) A universal asynchronous receiver transmitter is used for serial communications over a peripheral device serial port by translating data between parallel and serial forms. USB Universal Serial Bus (USB) Universal Serial Bus is an industry standard that defines cables, connectors and communications protocols used in a bus for connection, communication, and power supply between computers and electronic devices. UVLO Undervoltage Lockout (UVLO) The Undervoltage-Lockout is an electronic circuit used to turn off the power of an electronic device in the event of the voltage dropping below the operational value. Revision History Major changes since previous revision Revision History Revision Description 1.0 • Added the attention that the Vcc must be higher than 3.4V before any other pins exceeds 1.2V 0.7 • Added a description of the input filter for the PWM sensing 0.6 • Corrected for English language • Minor update of the PFC and FB content • Updated electrical characteristics Data Sheet 59 Revision 1.0 2016-11-4 Trademarks of Infineon Technologies AG µHVIC™, µIPM™, µPFC™, AU-ConvertIR™, AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, CoolDP™, CoolGaN™, COOLiR™, CoolMOS™, CoolSET™, CoolSiC™, DAVE™, DI-POL™, DirectFET™, DrBlade™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPACK™, EconoPIM™, EiceDRIVER™, eupec™, FCOS™, GaNpowIR™, HEXFET™, HITFET™, HybridPACK™, iMOTION™, IRAM™, ISOFACE™, IsoPACK™, LEDrivIR™, LITIX™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OPTIGA™, OptiMOS™, ORIGA™, PowIRaudio™, PowIRStage™, PrimePACK™, PrimeSTACK™, PROFET™, PRO-SIL™, RASIC™, REAL3™, SmartLEWIS™, SOLID FLASH™, SPOC™, StrongIRFET™, SupIRBuck™, TEMPFET™, TRENCHSTOP™, TriCore™, UHVIC™, XHP™, XMC™. Trademarks Update 2015-12-22 Other Trademarks All referenced product or service names and trademarks are the property of their respective owners. Edition 2016-11-4 Published by Infineon Technologies AG 81726 Munich, Germany © 2016 Infineon Technologies AG All Rights Reserved. Do you have a question about any aspect of this document? Email: erratum@infineon.com Document reference IFX-sch1429523754663 IMPORTANT NOTICE The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics (“Beschaffenheitsgarantie”) . With respect to any examples, hints or any typical values stated herein and/or any information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. 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