XDPL8221XUMA1

XDPL822x Controller Family XDPL8221 Digital PFC+Flyback Controller IC XDP™ Digital Power Data Sheet Revision 1.1 Features • • • UART interface to control driver output and reading operating status Flicker-free output dimming by analog reduction of driving current down to 1% Integrated two stage digital controller allows a reduced number of external parts, optimizes Bill of Materials (BOM) and form factor. • Two-stage design eliminates AC ripple on output. • Supports universal AC and DC input voltage (90 V rms to 305 V rms) nominal. • High efficiency up to 90% • Multi-control output (Constant Current (CC)/Constant Voltage (CV)/Limited Power (LP)) • Performance and protection related driver parameters are configurable via UART interface allowing for design flexibility and optimization. • Low harmonic distortion (Total Harmonic Distortion (THD) < 15%) down to 30% nominal load • Integrated 600V high voltage start-up cell ensures fast time to light (< 250 ms) • Configurable Adaptive Temperature Protection • Automatic switching of the Power Factor Correction (PFC) between Quasi-Resonant Mode (QRM) and Discontinuous Conduction Mode (DCM) • Automatic switching of the Flyback (FB) between QRM, DCM and Active Burst Mode (ABM) • Pulse Width Modulation (PWM) dimming input For safe operation, the XDPL8221 contains a comprehensive set of protection features with configurable reaction like auto-restart or latch: • Output over-voltage protection (open load) • Output under-voltage protection (output short) • VCC over- and under-voltage lockout • Input over- and under-voltage protection • Bus over- and under-voltage protection • Over-current protection for both PFC and FB stages Applications • AC/DC LED Drivers for Light Emitting Diode (LED) luminaires Data Sheet www.infineon.com Please read the Important Notice and Warnings at the end of this document Revision 1.1 2018-10-31 XDPL8221 Digital PFC+Flyback Controller IC XDP™ Digital Power Description L Input voltage CoolMOS™ GDPFC LED+ CSPFC CoolMOS™ GDFB N TEMP CSFB LED- XDPL8221 HV VCC VS ZCD GND UART UART Figure 1 PWM PWM GND Vsupply Typical Application for XDPL8221 Product Type Package XDPL8221 PG-DSO-16 Description XDPL8221 is a highly integrated next-generation device combining a multimode (QRM and DCM) PFC plus a multimode (QRM, DCM and ABM) FB with primary-side regulation. The integration of PFC and FB into a single controller enables reduction of external parts and optimizes performance by harmonized operation of the two stages. The two-stage approach divides the PFC responsibilities from the output current regulations functions. This ensures low variation in the output current (flicker) to a non-visible level and allows for low THD , high power factor and a greater ability to withstand AC line perturbations. XDPL8221 PFC comprises of constant on-time scheme with a THD improvement algorithm to provide a high power factor and excellent performance down to 30% nominal load. XDPL8221 FB can be configured to operate in Constant Voltage (CV), Constant Current (CC) or Limited Power (LP) mode offering a large degree of flexibility. The on-chip One Time Programmable Memory (OTP) memory allows user to adjust electrical and performance parameters that control the behavior of the circuit. Examples of this include: output current limit or the maximum output power. This enables the user of the device to create a platform concept with significantly fewer different hardware versions while still covering the same application range. The Universal Asynchronous Receiver Transmitter (UART) command interface allows connecting XDPL8221 to any microcontroller, wireless interface or sensor for many different applications. During low power mode, the XDPL8221 power consumption is less than 100mW. Data Sheet 2 Revision 1.1 2018-10-31 XDPL8221 Digital PFC+Flyback Controller IC XDP™ Digital Power Table of contents Table of contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 2 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 3.1 3.1.1 3.1.2 3.1.3 3.1.4 3.1.5 3.1.5.1 3.1.6 3.1.6.1 3.1.6.2 3.1.6.3 3.1.7 3.1.8 3.1.8.1 3.1.8.2 3.1.8.3 3.1.8.4 3.1.8.5 3.2 3.2.1 3.2.1.1 3.2.1.2 3.2.1.3 3.2.1.4 3.2.1.5 3.2.1.6 3.2.2 3.2.3 3.2.3.1 3.2.3.2 3.2.3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 PFC Controller Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Shared CS/ZCD Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Quasi-resonant Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Bus Voltage Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Input Voltage Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Control Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Multimode Control Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Frequency Law . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 THD Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Light Load Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Peak Current Limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Protection Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Bus Under-voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Bus Over-voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Input Under-voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Input Over-voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Other PFC Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Flyback Controller Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Primary Side Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Primary Side Current Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Primary Side Output Voltage Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Output Current Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Output control scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Multimode Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Flyback Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Protection features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Primary Over-current Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Output Under-voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Output Over-voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Data Sheet 3 Revision 1.1 2018-10-31 XDPL8221 Digital PFC+Flyback Controller IC XDP™ Digital Power Table of contents 3.2.3.4 3.2.3.5 3.2.3.6 3.2.3.6.1 3.3 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.3.6 3.3.6.1 3.3.6.2 3.3.6.3 3.3.6.4 3.3.6.5 3.3.7 3.3.7.1 3.3.7.2 3.3.7.3 3.3.7.4 Output Over-current Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Output Over-power Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Other Flyback Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Flyback Bus Voltage Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 General Controller Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Configurable Gate Driver Strengths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 External Temperature Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Adaptive temperature protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 PWM Dimming Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 UART Command Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Protection features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Overtemperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 VCC Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 VCC Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 VCC Undervoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Other General Controller Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Protection Reactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Auto restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Fast Auto Restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Latch Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4 4.1 4.2 4.3 4.4 Electrical Characteristics and Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Data Sheet 4 Revision 1.1 2018-10-31 XDPL8221 Digital PFC+Flyback Controller IC XDP™ Digital Power Pin Configuration 1 Pin Configuration Pin assignments and basic pin description information are shown below. GDFB 1 16 N.C. CSFB 2 15 N.C. VCC 3 14 UART GND 4 13 GDPFC ZCD 5 12 N.U. VS 6 11 CSPFC N.U. 7 10 TEMP HV 8 9 PWM PG-DSO-16 (150mil) Figure 2 Pinning of XDPL8221 Table 1 Pin Definitions and Functions Name Pin Type Function GDFB 1 O Gate driver for FB: The GDFB pin is an output for directly driving a power MOSFET of the FB stage. CSFB 2 I Current sensing for FB: The CSFB pin is connected to an external shunt resistor and the source of the power MOSFET of the FB stage. VCC 3 I Voltage supply GND 4 - Power and signal ground ZCD 5 I Zero-crossing detection of the FB: The ZCD pin is connected to an auxiliary winding of the FB stage for zerocrossing detection as well as primary-side output voltage and additional bus voltage sensing for functional safety. VS 6 I Bus voltage sensing N.U. 7 - Not used. Externally to be connected to GND. HV 8 I High voltage: The HV pin is connected to the rectified input voltage via an external resistor. An internal 600 V HV startup-cell is used to initially charge VCC. In addition, sampled high-voltage sensing is also used for synchronization with the input frequency. PWM 9 I PWM dimming: The PWM pin is used as a dimming input. TEMP 10 I External temperature sensor: Measurement of external temperature using an Negative Temperature Coefficient Thermistor (NTC). CSPFC 11 I Current sensing for PFC: The CSPFC pin is connected to an external shunt resistor and the source of the power MOSFET of the PFC stage. Data Sheet 5 Revision 1.1 2018-10-31 XDPL8221 Digital PFC+Flyback Controller IC XDP™ Digital Power Functional Block Diagram Table 1 Pin Definitions and Functions (continued) Name Pin Type Function N.U. 12 - Not used. Externally to be connected to GND. GDPFC 13 O Gate driver for PFC: The GDPFC pin is an output for directly driving a power MOSFET of the PFC stage. UART 14 I/O UART communication: The UART pin is used for the UART interface to support parametrization and for application commands during run-time. N.U. 15 - Not used. Externally to be connected to GND. N.U. 16 - Not used. Externally to be connected to GND. 2 Functional Block Diagram The functional block diagram shows the basic data flow from input pins via signal processing to the output pins. Power Factor Correction HV Data Sheet Input Voltage Sensing and Startup Output Voltage Sensing and Zero Crossing Detection ZCD GDPFC PFC Control Loop Output Current Calculation CSFB CSPFC Current Sensing and Zero Crossing Detection FB Control Loop GDFB PWM Dimming Sensing PWM UART Command Interface UART VS Figure 3 Flyback Bus Voltage Sensing VCC VCC Management TEMP External Temperature Sensing Adaptive Temperature Protection XDPL8221 Simplified Functional Block Diagram 6 Revision 1.1 2018-10-31 XDPL8221 Digital PFC+Flyback Controller IC XDP™ Digital Power Functional Description 3 Functional Description This chapter provides a summary of the integrated functions and features, and describes the relationships between them. The parameters and equations are based on typical values at TA = 25 °C. XDPL8221 is a digital dual-stage PFC and FB controller IC supporting PWM dimming functionality. Both stages use configurable multi-mode operation to select the best mode of operation for every operation condition. Multi-mode operation automatically switches between QRM, DCM and ABM (only for FB) XDPL8221 features a comprehensive set of configurable protection modes to detect fault conditions. XDPL8221 provides a high degree of flexibility in design-in of the application. A Graphic User Interface (GUI) tool supports users in the configuration of the operational and protection parameters. Data Sheet 7 Revision 1.1 2018-10-31 XDPL8221 Digital PFC+Flyback Controller IC XDP™ Digital Power Functional Description 3.1 PFC Controller Features The PFC stage ensures high power quality by maximizing the power factor and minimizing harmonic distortion. The PFC stage operates in Quasi-Resonant Mode, switching in first valley (QRM1) and Quasi-Resonant Mode, switching in valley n (QRMn), to support light load conditions and ensure efficient operation. The PFC stage is implemented as a boost converter and provides stabilized Direct Current (DC) voltage rail. 3.1.1 Shared CS/ZCD Function The PFC stage makes use of combined Current Sense and Zero-Crossing Detection (CS/ZCD) functionality at the CSPFC pin. During the PFC MOSFET on-time, the CSPFC pin has the function of sensing the PFC inductor current ensuring inductor does not enter saturation, and the converter limits maximum switching current. The CSPFC pin is connected to an external shunt resistors, which converts the inductor current to voltage. The sensed voltage at the CSPFC pin is compared with reference voltages on internal comparators to either limit the on-time cycle by cycle or enter the protection mode when over-current happens. During the PFC MOSFET off-time, the CSPFC pin has the function of current zero crossing detection (ZCD). This detection minimizes the turn-on losses of the PFC MOSFET by ensuring the MOSFET turns-on during the resonant valley of the PFC MOSFET drain-source voltage (VDS) (QRM). The CSPFC pin is connected via an external resistor divider composed of RZCD,1,PFC and RZCD,2,PFC and a set of diodes to the auxiliary winding of the PFC inductor. Diode D1 allows positive voltage at the CSPFC pin as the valley detection is implemented by the internal hysteretic comparator with a positive reference of nominal THRHYS for falling edges. Vg L Vbus RZCD,1,PFC D1 GDPFC RCS,PFC CSPFC RZCD,2,PFC VCC Figure 4 Shared CS/ZCD Schematic 3.1.2 Quasi-resonant Mode The quasi-resonant mode maintains a high efficiency level. XDPL8221 PFC Quasi-resonant mode reduces PFC MOSFET switching losses and ensures highest possible efficiency of the system. See Multi-mode Scheme description for detailed QRM operation in section 3.1.6. Data Sheet 8 Revision 1.1 2018-10-31 XDPL8221 Digital PFC+Flyback Controller IC XDP™ Digital Power Functional Description tsw iL tsw iL,pk 0 ton tLEB vCSPFC iL,ave tw t t1stV tosc 4 vL,pk 0 t tdisch QRM1 QRM2 Figure 5 QRM1 PFC QRM2 Waveforms Equations for the quasi-resonant operation are shown below. Delay time tw is an additional delay realized in each switching cycle when PFC MOSFET turn-on beyond first resonant valley and valley n (n>1) is selected (QRMn). V g · ton L iL, pk · L tdisch = V bus − V g iL, pk = t1stV = tdisch + tosc /2 tw = tosc · n − 1 tsw = ton + t1stV + tw tof f = t1stV + tw Equation 1 3.1.3 Bus Voltage Sensing The PFC output bus voltage is scaled down using a simple resistor divider and measured at the pin VS. A capacitor shall be added at the pin to ground to filter high-frequency switching noise. Vbus RVS,1 VS RVS,2 Figure 6 PFC Bus Voltage Sensing Circuit The Analog-to-Digital Converter (ADC) input at the VS pin utilizes two voltage ranges. The wider voltage range from 0 to VREF results in lower resolution. The narrower voltage range from 5/6 VREF to 7/6 VREF gives better voltage resolution. Steady state operation therefore normally takes place in the high-resolution range and soft start operation in the low-resolution range. Data Sheet 9 Revision 1.1 2018-10-31 XDPL8221 Digital PFC+Flyback Controller IC XDP™ Digital Power Functional Description VS 7/6 VREF High resolution range VREF 5/6 VREF Low resolution range 0V Figure 7 Sensing Ranges 3.1.4 Input Voltage Sensing t The input voltage is sensed at the HV pin for Alternating Current (AC) zero-crossing detection and protection features. iac vac Input voltage Vin { RHV C1 Figure 8 C2 HV Input Voltage Sensing Schematic The RHV sense resistor is usually split into two or more resistors for redundancy and safety purposes. A RC filter structure to the HV pin is implemented as shown above to reduce the unwanted noise. Data Sheet 10 Revision 1.1 2018-10-31 XDPL8221 Digital PFC+Flyback Controller IC XDP™ Digital Power Functional Description 3.1.5 Control Scheme The PFC bus voltage controller embeds a controller that calculates a control output representing load and line conditions from the bus voltage error signal. The bus voltage controller implements regulation during both soft start and steady states. 3.1.5.1 Startup At system startup, the PFC initiates soft start to minimize the switching stress on the power MOSFET, diode and inductor. PFC soft start is executed once the PFC bus voltage is charged due to rectified AC line to a voltage threshold Vbus,start,PFC but lower than Vbus,OVP1. The PFC soft start is aborted if the input under- or over-voltage protections are triggered. During soft start, the PFC operates in QRM1mode. Once the Vbus,stdy,entr,UV threshold is reached, the steady state PFC operation starts. Vbus Vbus,set Vbus,stdy,entr,UV Vbus,start,PFC VCC startup passive charging charging steady state Figure 9 Vbus Soft Start and Regulation 3.1.6 Multimode Control Scheme t The XDPL8221 multi-mode control scheme provides an option to dynamically change the operating point by switching between the MOSFET Vds voltage valleys while following a frequency law and applying THD optimization. The multi-mode controller uses three different modes of operation: • QRM1: operation occurs during normal operation of the PFC converter at nominal to heavy loads. This operation maximizes the efficiency by switching on at the 1st valley of the PFC ZCD signal. This ensures zero current switching with a minimum switching losses. During QRM1, the PFC MOSFET is turned on with a constant on-time for a line and load condition, while the off- time varies within an AC half-cycle depending on the instantaneously rectified AC input voltage. Subsequently, the PFC switching frequency varies within each AC half-cycle with the lowest switching frequency at the peak of the AC input voltage and the highest switching frequency near the zero crossings of the input voltage. • QRMn: PFC MOSFET on-time reduces as the load decreases, this results in higher switching frequencies, particularly near the zero-crossing of the input voltage. Higher switching frequencies will increase switching losses, resulting in poor efficiency at light loads. The XDPL8221 controller extends to the next switching valley after the 1st valley to control the bus voltage following a frequency law which limits the switching frequency to minimize the switching losses. • DCM: The controller regulates the power transfer by adjusting the switching frequency with fixed minimum on-time. This enables the light load optimization. Data Sheet 11 Revision 1.1 2018-10-31 XDPL8221 Digital PFC+Flyback Controller IC XDP™ Digital Power Functional Description The multimode optimization consists of the following: • Frequency law • THD optimization • DC switching frequency dithering • Light load optimization 3.1.6.1 Frequency Law A PFC converter is used to emulate a resistive load re to the AC input such that iac follows vac in both wave shape and phase. The output of the PFC bus voltage controller ton,des,PFC is inversely proportional to the emulated resistive load re such that a smaller re or a higher Iac,rms will give a larger ton,des,PFC. Thus, ton,des,PFC varies as the AC line voltage magnitude varies and is proportional to the RMS input current Iac,rms. The rule for selecting QRMn is based on the frequency law. A maximum switching frequency fswmax and a minimum switching frequency fswmin are defined for the complete ton,des,PFC/Iac,rms range. The frequency law ensures that the switching frequency is within the desired frequency range. The frequency law is depicted in the figure below. fswmax M1 QR 2 M QR 3 M QR 4 M QRM5 QR fsw fswmin sample operating point Figure 10 ton,des,PFC / Iac,rms PFC Frequency Law As long as the PFC controller operating mode satisfies the frequency law, the operating mode does not change. The QR-valley is increased when the highest frequency limit is reached. The QR-valley is decremented when the lowest frequency limit is reached. To ensure proper ZCD detection before the ZCD signal becomes too small in amplitude, only the first up to Nvalley,max,PFC valleys operations are supported. 3.1.6.2 THD Optimization QRMn selection beyond the first valley during light load and/or AC high line reduces the switching frequency but distorts the input current waveform with constant on-time control andTHD may suffer. The multi-mode PFC control consists of a THD optimization algorithm that optimizes the applied on-time in order to ensure good input current shaping and improved PFC THD performance. Data Sheet 12 Revision 1.1 2018-10-31 XDPL8221 Digital PFC+Flyback Controller IC XDP™ Digital Power Functional Description Vin t ton QRM3 QRM2 QRM1 BCM t Figure 11 THD optimization on-time Figure 11 shows the on-time at different valley selection at the same line and load conditions. Note: 3.1.6.3 Boundary Conduction Mode (BCM) is an operating mode where the switch turns on at the first occurrence of inductor zero current . Light Load Optimization This paragraph describes how the PFC manages light load conditions. DCM PFC converter will eventually enter DCM operation as load decreases and/or AC line increases to reduce the switching frequency and switching losses. XDPL8221 PFC control enters DCM when the internal on-time is less than ton,dcm. The PFC leaves DCM when the switching period is less than tsw,min,dcm. When the PFC is operating in DCM, the bus voltage controller regulates the switching period keeping the on-time constant. Due to the ontime dependency on the input voltage, the PFC enters and exits DCM at different power levels. This has the advantage to operate in QRM for an extended power range at low line maintaining high efficiency. 3.1.7 Peak Current Limitation The peak current through the switching MOSFET is sensed via the PFC shunt resistor RCS,PFC to limit the maximum current through the MOSFET, the choke, and freewheeling diode. Overcurrent Protection Level 1 (OCP1) is implemented by hardware. If the voltage VCS,PFC across the shunt resistor exceeds the over-current threshold VCS,OCP1, PFC for longer than the blanking time tblank,OCP1,PFC, the MOSFET is turned off. The MOSFET is turned on when ZCD occurs or the PFC maximum period time-out signal triggers the start of the next switching cycle. Overcurrent Protection Level 2 (OCP2) is a second-level overcurrent protection implemented by hardware. The OCP2 overcurrent threshold is fixed. The OCP2 blanking time is tblank,OCP2,PFC. Data Sheet 13 Revision 1.1 2018-10-31 XDPL8221 Digital PFC+Flyback Controller IC XDP™ Digital Power Functional Description 3.1.8 Protection Features Protections features are triggered if fault conditions are present longer than the blanking times for each protection. Attention: The controller may continue operation after exceeding protection thresholds because of blanking times as shown in Figure 12. All protection thresholds have to be set with respect to tolerances, blanking times and worst case transients. Note: The blanking time as specified in the csv file does not include the protection notification time. Sampled voltage or sampled current Protection triggering Sampled voltage Overvoltage or Overcurrent protection threshold Undervoltage protection threshold Protection triggering Time tblank Time tblank Figure 12 Blanking Times cause Excess of Threshold 3.1.8.1 Bus Under-voltage Protection Under-voltage detection of the PFC bus voltage Vbus is sensed at the VS pin. The PFC bus voltage is sensed and compared to a configurable under-voltage protection threshold Vbus,UV. If the bus voltage is below the threshold for longer than the blanking time tblank,Vbus,UV, the protection will be triggered. 3.1.8.2 Bus Over-voltage Protection Over-voltage detection of the PFC bus voltage Vbus is sensed at the VS pin. The PFC bus voltage is sensed and compared to a configurable over-voltage protection threshold Vbus,OVP1 in Firmware (FW). If this threshold is exceeded for longer than the blanking time tblank,Vbus,OVP1, the PFC stops switching. The PFC resumes operation when Vbus falls below Vbus,stdy,entr,OV. Vbus,OVP2 is implemented in Hardware (HW) and it is fixed at a voltage which is represented as 7/6 VREF at the bus voltage sensing pin (VS). The HW permits a blanking time tblank,Vbus,OVP2 to be programmed. Data Sheet 14 Revision 1.1 2018-10-31 XDPL8221 Digital PFC+Flyback Controller IC XDP™ Digital Power Functional Description Vbus Vbus,ovp2 Vbus,ovp1 Vbus,stdy,entr,OV Vbus,set Vbus,uv t Figure 13 Vbus protections 3.1.8.3 Input Under-voltage Protection Under-voltage detection of the input voltage Vin is sensed at the HV pin. Values of Vin,rms are compared to a configurable input undervoltage protection threshold Vin,UV. If the input voltage is below the threshold for longer than the blanking time tblank,Vin,UV, the protection will be triggered. XDPL8221 features a configurable start-up threshold Vin,start,min to create hysteresis for flicker-free operation before the second stage starts switching. 3.1.8.4 Input Over-voltage Protection Over-voltage detection of the input voltage Vin is sensed at the HV pin. Values of Vin,rms are compared to a configurable input over-voltage protection threshold Vin,OV. If the threshold is exceeded for longer than the blanking time tblank,Vin,OV, the protection will be triggered. XDPL8221 features a configurable start-up threshold Vin,start,max to create hysteresis for flicker-free operation before the second stage starts switching. Vin Vin,OV Vin,start,max Vin,start,min Vin,UV t tstart,delay,FB Figure 14 Data Sheet Vin protections 15 Revision 1.1 2018-10-31 XDPL8221 Digital PFC+Flyback Controller IC XDP™ Digital Power Functional Description 3.1.8.5 Other PFC Protections Current Sense (CS) Resistor Short Protection The input fuse should be chosen appropriately to protect converter if current-sense resistor is shorted. Current Sense (CS) Resistor Open Protection CS/ZCD external circuitry pulls the CSPFC pin high when CS resistor is open, OCP2 protection is triggered. CSPFC Pin Short to GND Protection In case of CSPFC pin short to ground the missing of quasi-resonant oscillations will trigger the CCM Protection. CCM Protection Continuous conduction mode (CCM) operation may occur during PFC startup for a limited time and is allowed. In normal operation, extended CCM operation in the PFC converter is considered a failure. Circumstances where the PFC converter may experience CCM operation: • Shorted PFC bypass diode • Heavy load step which is out of specification • Low input voltage outside the normal operating range During CCM operation, the magnetizing current in the PFC choke does not decay to zero prior to MOSFET turnon. Quasi-resonant oscillation is missing in the ZCD signal before the maximum switching period time-out is reached that turns the MOSFET on. This turn-on event without ZCD oscillation is monitored to protect the PFC converter from continuous CCM operation. Extended CCM operation protection is implemented within FW. If quasi-resonant oscillation is missing in the ZCD signal for longer than the blanking time tblank,CCM,PFC, the protection is triggered. Soft Start Failure PFC start-up time maybe extended due to abnormally heavy loads or a low input voltages. PFC steady state operation may not be reached if tstart,PFC reaches tstart,max,PFC before the soft start has ended, and the protection is triggered. Data Sheet 16 Revision 1.1 2018-10-31 XDPL8221 Digital PFC+Flyback Controller IC XDP™ Digital Power Functional Description 3.2 Flyback Controller Features The Flyback converter stage provides isolation and primary side control of the output current. Primary side regulation of the output current eliminates secondary side control feedback loop circuitry usually needed in isolated power converters. This feature reduces part count to reduce costs. The Flyback stage features multi-mode operation (QRM, DCM and ABM) which ensures efficiency and performance is optimized. 3.2.1 Primary Side Regulation The XDPL8221 FB stage provides primary side control of output current and output voltage. No external feedback components are necessary for the current control. Figure 15 shows typical current and voltage waveforms of the FB application operating in QRM1. In DCM, the MOSFET will not turn on at the first valley of the resonant oscillation seen at VAUX, but instead delayed. Primary side regulation of the average output current is accomplished by sensing the primary peak current Ip,pk, the period of conduction of the output diode tdemag and the switching period tsw,FB. The voltage signal VAUX of the auxiliary winding of the transformer contains information on the reflected output voltage Vout. The reflected output voltage is measured at the ZCD pin using a resistor divider. VAUX Reflected output voltage sampling Zero crossing detection 0V Bus voltage sampling Valley switching Ip time tCS,sample Is Vbus Vout tZCD,sample Itransformer Np Na tsw,FB Ns Ip,pk Ip VAUX Ip Is time tdemag VGD time Figure 15 Data Sheet Typical Waveforms of a Flyback Converter 17 Revision 1.1 2018-10-31 XDPL8221 Digital PFC+Flyback Controller IC XDP™ Digital Power Functional Description 3.2.1.1 Primary Side Current Sensing The primary side peak current Ip,pk is controlled by the control loop using the VCS,OCP1 level at the CSFB pin. This control scheme ensures suppression of any variation in the bus voltage. Several delays exist from the time at which the OCP1 level VCS,OCP1 is exceeded at the CSFB pin until the gate switches off and the transformer current finally reaches its peak value. For a higher accuracy, the primary peak current VCS,SH is sampled a fixed time before turn-off of the gate. The primary side peak current is used to calculate the secondary side current and for protection. The propagation delay compensation parameter tPDC allows optimization of the accuracy of the primary side peak current: Ip, pk = V CS, SH RCS, FB ⋅ ton, FB + tPDC ton, FB − tCSFB, offset Equation 2 Note: If an RC low pass filter is added in front of the CSFB pin, the related low pass filter delay has to be included in tPDC. Ip Ip,pk = VCS,pk RCS,FB VCS,SH RCS,FB t tPDC VGD tCSFB,offset t ton,FB Figure 16 Propagation Delay Compensation for accurate Primary Peak Current Calculation 3.2.1.2 Primary Side Output Voltage Sensing The output voltage is determined by measuring the reflected output voltage on the auxiliary winding. A resistor divider adapts the voltage to the operating range of the ZCD pin. The output voltage is measured at the ZCD pin using the voltage VZCD,SH at the end of the demagnetization time at the time tZCD,sample. The voltage measured at the ZCD pin, the dimensioning of the resistor dividers RZCD,FB,1 and RZCD,FB,2, transformer turns Ns and Na as well as an offset Vout,offset (caused by the secondary diode, for example) are used to calculate the output voltage Vout as follows: V out = V ZCD, SH RZCD, FB, 1 + RZCD, FB, 2 Ns RZCD, FB, 2 Na + V out, offset Equation 3 Vout is used for Primary Side Regulated (PSR) control loops in CV and LP modes as well as for output over- and undervoltage protections. Data Sheet 18 Revision 1.1 2018-10-31 XDPL8221 Digital PFC+Flyback Controller IC XDP™ Digital Power Functional Description Vout,offset Na Ns RZCD,FB,1 VOut ZCD VZCD,SH Figure 17 Note: RZCD,FB,2 Primary Side Output Voltage Sensing using ZCD S&H Any relation between VCC and ZCD in self-supplied applications can be decoupled – e.g. by adding a linear regulator for VCC. Attention: Please note that the time (tdemag) has to be longer than 2.0 μs to ensure that the reflected output voltage can be sensed correctly at the ZCD pin. 3.2.1.3 Output Current Calculation The output current is calculated based on the primary side peak current and the timing of the switching cycle. The output current Iout is calculated using the duration of conduction of the output diode tdemag, the switching period tsw,FB as well as the number of transformer turns Np, Ns and the transformer coupling Kcoupling. The following equation is valid in QRM1 and DCM: 1 Iout = 2 Ip, pk ⋅ Np Ns ⋅ K coupling ⋅ tdemag tsw, FB Equation 4 In ABM the average output current depends on the number of pulses NABM,PI and the burst period tburst,FB: 1 Iout = 2 Ip, pk ⋅ Np Ns ⋅ K coupling ⋅ tdemag ⋅ NABM, PI tburst, FB Equation 5 The coupling of the transformer can be approximated using the transformer primary inductance Lp and the transformer primary leakage inductance Lp,lk as follows: K coupling ≈ Lp Lp + Lp, lk Equation 6 The calculated current Iout is used for the control loop in the modes CC and LP. The calculated current is also used for output overcurrent protection. 3.2.1.4 Output control scheme The XDPL8221 includes three different control schemes for a CC, CV or LP output. Different use cases require the controller to operate according to different operation schemes: • In the case of typical LED strings, the forward voltage of the LED string determines the output voltage of the driver. XDPL8221 operates in CC and drives a constant output current Iout,full to the load. The forward voltage of the connected LED string has to be below a configurable maximum value Vout,set. Data Sheet 19 Revision 1.1 2018-10-31 XDPL8221 Digital PFC+Flyback Controller IC XDP™ Digital Power Functional Description • In the case of LED loads including a power stage (e.g. Infineon BCR linear regulators or Infineon DC/DC buck ILD2111), XDPL8221 operates in CV, ensuring a constant voltage Vout,set to the load. The total output current drawn by the load has to be below a configurable maximum value Iout,full. • In the case of a high output current setpoint Iout,full and an overly long LED string which exceeds the configurable power limit Pout,set, XDPL8221 operates in LP to ensure that the power limit of the driver is not exceeded. The controller reduces the output current automatically, ensuring light output without any interruption even for overly long LED strings. The forward voltage of the connected LED string has to be below a configurable maximum value Vout,set. For every update of the control loop, the control scheme is selected on the basis of the current operation conditions (output voltage Vout and output current Iout) and their distance to the three limiting setpoints (Vout,set, Pout,set and Iout,full): • For CC schemes, the internal reference current Iout,full is weighted according to thermal management and a dimming curve to yield Iout,set. The calculated output current Iout is compared with the weighted reference current Iout,set to generate an error signal for the output current. • For CV schemes, the sensed output voltage Vout at the ZCD pin is compared to a reference voltage Vout,set to generate an error signal for the output voltage. • For LP schemes, the output current is limited to a maximum of Iout,set = Pout,set / Vout. Out of these three schemes, for each step the most critical error is selected (see Figure 18): 1. If any setpoint is exceeded, the largest error for power decrease is selected to bring the controller back to the desired operating point as quickly as possible. 2. If the current operating conditions are below all three setpoints, the smallest error for power increase is selected to avoid overshooting any setpoint. The selected error signal is fed into a compensator to control the gate driver switching parameters (i.e. duty cycle and frequency) for the power MOSFET of the FB. Output voltage Vout,OV Output open Pout,set Pout,OPP Vout,set Constant voltage Limited power Constant current Vout,start Vout,UV Iout,min Figure 18 Output short Iout,full Iout,OCP Output current Control scheme for CC/CV/LP modes (non-dimmed) In dimming cases, the output current setpoint Iout,set is located between Iout,min and Iout,full and varies according to the sensed PWM duty cycle DDIM. Dimming can be visualized by moving the vertical line for the output current setpoint in Figure 19 from right to left. Note: Data Sheet In the limited power mode, the maximum output current is limited to Iout,set = Pout,set / Vout. which is smaller than Iout,full. It can be selected through parameter, whether Iout,set or Iout,full should be mapped to 100% dimming level. If the Iout,full is mapped to 100% dimming level in the limited power mode, the dimmer will experience the dead-travel between Iout,set and Iout,full (no current change while the dimming level is changing). 20 Revision 1.1 2018-10-31 XDPL8221 Digital PFC+Flyback Controller IC XDP™ Digital Power Functional Description Output voltage Output open Vout,OV Legend: Pout,set Operating range Constant voltage Vout,set Limited power Dimming Vout,start Vout,UV Output short Dim-to-Off Iout,min Figure 19 Constant current Iout,full Output current Control scheme for CC/CV/LP modes (including dimming) One or more of the output control schemes can be deactivated by configuration of the setpoints. Some examples are given below: • The LP scheme is not active for Pout,set > Vout,set * Iout,full. For such a configuration, the controller will only select between a CC and CV scheme. • The CV scheme is not active for Vout,set = Vout,OV as the output overvoltage protection will be triggered. • The CC scheme is not active for Iout,full = Iout,OC as the output overcurrent protection will be triggered. Compensation of output losses In case any output of flyback windings is not only supplying a current to LEDs, but also supplying other consumers (e.g. bleeders, CDM10VD, etc.), the primary side regulation of the output current will not be accurate. Parameter Gloss allows to compensate ohmic losses on the secondary side: Iout,corrected = Iout,uncorrected + Gloss * Vout Output current slew rate limitation As the transient response of the PFC stage is rather slow (especially if the PFC is in low power mode), a fast increase of the flyback power can cause a significant undershoot of the bus voltage. To limit this undershoot, the rising slew rate of the flyback output current can be limited using parameter Iout,slew,rate,step as shown in Figure 20. Data Sheet 21 Revision 1.1 2018-10-31 XDPL8221 Digital PFC+Flyback Controller IC XDP™ Digital Power Functional Description Voltage or current Vbus,set Vbus Iout,corrected Iout,set Iout,slew,rate,step / 160 µs Time Figure 20 Output slew rate limitation 3.2.1.5 Multimode Scheme The control loop of XDPL8221 uses three different switching modes: QRM1 is optimized for high efficiency at high loads, DCM is used for medium loads and ABM is used for very light load conditions. Power VCS,max,FB Peak-current controlled QRM1 VCS,min,FB tsw,min,FB Pmax Frequency controlled DCM tsw,max,FB Pulse number controlled ABM Pmin NABM,min Vbus,UV Figure 21 • Vbus,OVP1 Bus Voltage Flyback Multimode Operation Scheme QRM1: This mode maximizes the efficiency by switching on the 1st valley of the VAUX signal. This ensures zero current switching with a minimum of switching losses. The power is controlled by regulating the primary peak current using VCS,OCP1: Pout = 1 2 ⋅ Lp ⋅ V CS, OCP1 2 RCS, FB ⋅ Lp ⋅ V CS, OCP1 R CS, FB ⋅ V bus 1+ 1 Ns V bus Np V out + tOSC, FB 2 Equation 7 Data Sheet 22 Revision 1.1 2018-10-31 XDPL8221 Digital PFC+Flyback Controller IC XDP™ Digital Power Functional Description • DCM: This mode is used if VCS,OCP1has reached its minimum value VCS,min,FB. To allow lower output power, the controller extends the switching period tsw,FB later than the 1st valley: Pout = • 1 2 ⋅ Lp ⋅ V CS, min, FB 2 RCS, FB ⋅ 1 tsw, FB Equation 8 ABM: This mode is used if VCS,OCP1 cannot be reduced and tsw,FB cannot be increased anymore. To reduce power transfer, the controller will stop switching for some time, causing bursts of pulses: Pout = 1 2 ⋅ Lp ⋅ V CS, min, FB 2 RCS, FB ⋅ NABM, PI tburst, FB Equation 9 The frequency of the bursts is defined by 1/tburst,FB. The pulses of each burst have a peak current of VCS,min,FB and a switching frequency of 1/tsw,max,FB. The number of pulses NABM,PI is regulated to control the average power transfer during one burst period tburst,FB. The minimum power in DCM is limited by the transformer primary inductance Lp, maximum switching period tsw,max,FB, minimum primary peak voltage VCS,min,FB, maximum bus voltage Vbus,OVP1 and two timing parameters: Pmin = 2 Lp 1 V bus, OVP1 V CS, min, FB 2 Lp RCS, FB V bus, OVP1 + tOCP1, FB + tPDC 2 1 tsw, max, FB Equation 10 The minimum power in ABM is limited by the transformer primary inductance Lp, burst period tburst,FB, minimum number of pulses NABM,min, minimum primary peak voltage VCS,min,FB, maximum bus voltage Vbus,OVP1 and two timing parameters: Pmin = 2 Lp 1 V bus, OVP1 V CS, min, FB 2 Lp RCS, FB V bus, OVP1 + tOCP1, FB + tPDC 2N ABM, min tburst, FB Equation 11 Note: 3.2.1.6 If the load drops below the minimum load of Pmin, the output voltage will rise up to the output overvoltage threshold Vout,OV and trigger the protection. An auto-restart can be used to keep the output voltage close to Vout,OV until the load increases again. Active Burst Mode The sense and control scheme for the active burst mode of the FB is described. The typical waveform for the gate drivers, the secondary side flyback transformer current, the output voltage and the bus voltage are shown in the figure. The bursts are repeated with a configurable burst period tburst,FB. It is advised to choose a burst frequency faster than 200 Hz to ensure a sufficient light quality and reduce output ripple. On the other hand, the burst frequency should not be too high as the human ear is more sensitive to higher frequencies. Data Sheet 23 Revision 1.1 2018-10-31 XDPL8221 Digital PFC+Flyback Controller IC XDP™ Digital Power Functional Description GDFB Vout Isec Burst Burst Pause tburst,FB Figure 22 Example Waveforms in Active Burst Mode (not drawn to scale) The FB switching pulses of each burst will boost the output voltage to a higher level. During the burst pause, the output voltage drops due to the load of the power converter. To control the average output current or the average output voltage, the FB controller calculates the average secondary current and measures the output voltage once at the beginning and once at the end of each burst. These measurements are used to calculate the average output current and average output voltage for the complete burst. Based on these average values, the control loop updates the number of pulses per burst. 3.2.2 Flyback Startup After startup, the FB of the XDPL8221 initiates a soft start to minimize the switching stress for the power MOSFET and secondary diode. The controller switches with a configurable switching frequency of fsw,start,FB and increases the cycle-by-cycle current limit in steps of VCS,step with a configurable duration tsoftstart for each step. After the final VCS,OCP1,start limit level has been reached, the output will be charged until the minimum output voltage Vout,start, which ensures self-supply has been reached. At this condition, Continuous Conduction Mode (CCM) protection as well as output undervoltage protection are activated and the control loop takes over. The starting point for the control loop is to operate in ABM at lowest number of pulses, lowest switching frequency and lowest primary peak-current. These switching parameters avoid an overshoot of output current for a LED string with low forward voltage when dimmed down to a low output current. Output voltage Peak current Soft Start Control loop active Vout Vout,start VCS,OCP1 VCS,OCP1,start VCS,step time tsoftstart Figure 23 Data Sheet Flyback Startup Sequence 24 Revision 1.1 2018-10-31 XDPL8221 Digital PFC+Flyback Controller IC XDP™ Digital Power Functional Description 3.2.3 Protection features Protections ensure the operation of the controller under restricted conditions. The protection monitoring signal(s) sampling rate, protection triggering condition(s) and protection reaction are described in this section. Attention: The sampled protection monitoring signal accuracy is subjective to the digital quantization, tolerances of components (including Integrated Circuit (IC)) and estimations with indirect sensing (e.g. input and output voltage estimations based on ZCD, CS pin signals), while the protection level triggering accuracy is subjective to the sampled signal accuracy, sampling delay, indirect sensing delay (e.g. reflected output voltage signal cannot be sensed by ZCD pin near AC input phase angle of 0° and 180°) and blanking time. 3.2.3.1 Primary Over-current Protection The primary side over-current protection implemented in hardware covers fault conditions like a short in the transformer primary winding or an open CS pin. The primary side current is compared to an over-current protection threshold VCS,OCP2. If the threshold is exceeded for longer than the blanking time tOCP2,FB, the protection will be triggered. 3.2.3.2 Output Under-voltage Protection In case of a short of the output or an overload, the output voltage may drop to a low level. Detection of undervoltage in the output voltage Vout is enabled by measurement of the reflected voltage at the ZCD pin. During operation, the output voltage is compared to a configurable under-voltage protection threshold Vout,UV. If the threshold is exceeded for longer than the blanking time tblank,out,UV, the protection will be triggered. During startup,a shorted output or a strong capacitive loading may not allow the controller charging the output voltage to Vout,UV,start within a timeout of tstart,max,FB. If this timeout expires the protection will be triggered. The timeout starts when the controller starts switching. Note: The startup under-voltage threshold Vout,UV,start has to be configured sufficiently above the undervoltage threshold Vout,UV to allow undershoots at start-up which may occur, especially for resistive loads which already consume power from the beginning. Attention: Output under-voltage protection is not available while the controller operates in ABM. 3.2.3.3 Output Over-voltage Protection In case of a open output, the output voltage may rise to a high level. Over-voltage detection of the output voltage Vout is provided by measurement at the ZCD pin. The output voltage is compared to an over-voltage protection threshold Vout,OV. If the threshold is exceeded for longer than the blanking time tblank,out,OV, the protection will be triggered. Note: The blanking time tblank,Vout,OV must be taken into account because overshoots of the output voltage above the protection threshold can occur due to this time. Note: This protection is usually triggered if the output is open or the output load drops below the minimum load Pmin. Attention: Output over-voltage protection is not available while the controller operates in ABM. Data Sheet 25 Revision 1.1 2018-10-31 XDPL8221 Digital PFC+Flyback Controller IC XDP™ Digital Power Functional Description 3.2.3.4 Output Over-current Protection Over-current detection in the output current Iout is provided on the basis of the calculated output current. The calculated output current is compared to a configurable over-current protection threshold Iout,OC. If the threshold is exceeded for longer than the blanking time tblank,out,OC, the protection will be triggered. 3.2.3.5 Output Over-power Protection Over-power detection in the output power Pout is provided on the basis of the calculated output power. The calculated output power is compared to a configurable over-power protection threshold Pout,OP. If the threshold is exceeded for longer than the blanking time tblank,out,OP, the protection will be triggered. 3.2.3.6 Other Flyback Protections XDPL8221 includes additional protections to ensure the integrity and correct flow of the firmware. • • • • • A hardware weak pull-up protects against an open CSFB pin. The CSFB OCP2 will be triggered for an open CSFB pin. A firmware watchdog protects against the CSFB pin becoming shorted to GND. The protection triggers if the sampled CSFB voltage is less than 97.6 mV for longer than the blanking time of tsoftstart. A firmware state monitor supervises correct operation of the flyback in QRM1, DCM or ABM. A protection is triggered if the flyback enters CCM. A firmware plausibility check ensures that both bus voltage measurements using the ZCD andVS pins are consistent. A firmware watchdog supervises correct data handling of the flyback. 3.2.3.6.1 Flyback Bus Voltage Sensing The FB can sense the bus voltage using the reflection of bus voltage on the auxiliary winding while the gate is turned on. A resistor divider adapts the negative voltage to the operating range of the ZCD pin. This second measurement path is required to protect against component failures in the VS measurement path (open loop protection for the PFC stage). The reflected bus voltage appears as a negative voltage at VAUX. This negative voltage is internally clamped at the ZCD pin to the negative voltage VINPCLN. The internal clamping current IZCD is measured at the end of the ontime at the time tCS,sample. The measured clamping current of the ZCD pin, the dimensioning of the resistor dividers RZCD,FB,1 and RZCD,FB,2 as well as the number of transformer turns Na and Np are used to calculate the bus voltage Vbus,FB as follows: V bus, FB = IZCD + V INPCLN RZCD, FB, 2 RZCD, FB, 1 + V INPCLN Np Na Equation 12 Vbus,FB is used for a plausibility check with the bus voltage Vbus as measured using the VS pin. Na Np RZCD,FB,1 ZCD VINPCLN Figure 24 Data Sheet Vbus,FB IZCD RZCD,FB,2 Bus Voltage Sensing using ZCD Clamp Current 26 Revision 1.1 2018-10-31 XDPL8221 Digital PFC+Flyback Controller IC XDP™ Digital Power Functional Description 3.3 General Controller Features XDPL8221 provides general features using device level measurements (DLM) for firmware task scheduling, VCC control and temperature control which are independent of the target application. 3.3.1 Configurable Gate Driver Strengths The gate driver output signals can be configured with respect to their rising slopes for switching on the power MOSFET and with respect to their high voltage levels. This feature can save BOM components (1 diode & 1 resistor per gate driver) which are conventionally added to achieve the same purpose to lower any Electro-Magnetic Interference (EMI). 3.3.2 External Temperature Sensing The external temperature is measured by measuring the voltage of an NTC with respect to the internal VREF voltage. Controller VREF RPU TEMP VTEMP Figure 25 RNTC External Temperature Sensing using NTC The controller calculates the resistance of the NTC based on the measured voltage VTemp, the internal reference voltage VREF and the internal pull-up resistance RPU: RNTC = V Temp ⋅ RPU V REF − V Temp Equation 13 3.3.3 Adaptive temperature protection XDPL8221 offers adaptive temperature protection using the external temperature sensor. This feature reduces the output current according to temperature to protect the load and/or driver against overtemperature. As long as the resistance of the NTC is lower than the temperature threshold RNTC,hot of the NTC, the current is gradually reduced from the maximum current Iout,set, as shown in Figure 26. If the resistance of the NTC is higher than threshold RNTC,hot, the output current is gradually increased again. This allows the controller to ensure operation at or below a temperature matching to RNTC,hot. If a reduction down to a minimum current Iout,red is not able to compensate for any continued increase in temperature (causing a continuing reduction of NTC resistance), XDPL8221 will trigger external overtemperature protection if the external sensor exceeds RNTC,critical. Data Sheet 27 Revision 1.1 2018-10-31 XDPL8221 Digital PFC+Flyback Controller IC XDP™ Digital Power Functional Description Temperature reduced output current Temperature reduced output current Iout,full Iout,full Iout,red Iout,red R≥ RNTC,hot R