XDPS21081
Forced Quasi Resonant ZVS Flyback controller
Based on FW: REV 1.0
Product Highlights
•
•
•
•
•
•
Integrated 600 V startup cell for fast startup and direct bus voltage sensing
Multi-mode operation with forced quasi resonant (FQR) Zero Voltage
Switching (ZVS) mode
DCM operation guaranteed
Adaptive current limitation for variable Vout
Supports low no load input power to meet stringent regulatory standard
One pin UART interface for configuration
Features
Description
• Low line QR, high line FQR ZVS
• Configurable ZVS enabled line voltage
• Low side ZVS MOSFET gate control
• ZVS optimization per variable Vout
• Built-in protection modes
• Brown-in and brownout detection via integrated HV
startup cell
• Pb-free lead plating; RoHS compliant
• Halogen-free according to IEC61249-2-21
The XDPS21081 is a digital PWM controller for high density
adapter applications based on Forced Quasi-resonant ZVS
flyback topology. It provides low line QR and high line FQR
ZVS operation. A wide feature set is provided in a DSO-12
package and requires only a minimum of external
components. An integrated ASSP digital engine provides
advanced algorithms for multi-mode operation and
protection features. A forced quasi resonant ZVS operation
support optimized high density adapter system
dimensioning. In addition a one-time-programmable (OTP)
unit is integrated to provide a selective set of configurable
parameters, which can be matched to a dedicated system
design.
Applications
•
High density adapter/charger
Product Validation
•
Qualified for industrial applications according to the
relevant tests of JEDEC47/20/22
85 ... 264 VAC
VCC
ZCD
GD1
HV
GPIO
GD0
XDPS21081 CS
MFIO
GND
Figure 1
Typical application
Marking
Package
FW Revision
SP Ordering Code
XDPS21081
PG-DSO-12
REV 1.0
SP005415076
Data Sheet
www.infineon.com
Please read the Important Notice and Warnings at the end of this document
Revision 2.0
2020-08-20
Forced Quasi Resonant ZVS flyback controller
Table of contents Description
Table of contents
Based on FW: REV 1.0 ...................................................................................................................... 1
Product Highlights .......................................................................................................................... 1
Features
1
Applications ................................................................................................................................... 1
Product Validation .......................................................................................................................... 1
Description 1
Table of contents ............................................................................................................................ 2
1
Pin Configuration and Functionality ................................................................................ 4
2
Representative Block Diagram ........................................................................................ 5
3
Introduction.................................................................................................................. 6
4
4.1
4.1.1
4.1.2
4.1.3
4.1.4
4.1.5
4.1.5.1
4.1.5.2
4.2
4.2.1
4.2.1.1
4.2.1.2
4.2.1.3
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
4.2.7
4.2.8
4.2.8.1
4.2.9
4.2.10
4.2.10.1
4.2.10.2
4.2.10.3
4.2.11
4.2.12
4.2.13
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
Functional Description ................................................................................................... 7
Power supply management .................................................................................................................... 7
VCC capacitor charge-up and startup sequence............................................................................... 7
Brown-in monitoring.......................................................................................................................... 8
Brown-out protection ........................................................................................................................ 9
During burst mode operation ............................................................................................................ 9
Bang-bang mode during latched and auto-restart operation ....................................................... 10
During latched operation............................................................................................................ 11
During auto-restart operation .................................................................................................... 11
Control features..................................................................................................................................... 12
Reflected voltage sensing and VCS offset calculation based on output voltage ............................ 14
Output voltage sensing via ZCD pin ........................................................................................... 15
Ringing suppression time ........................................................................................................... 17
Vcs offset calculation based on output voltage sensed at ZCD pin .......................................... 17
Vbulk voltage measurement via HV startup cell ............................................................................. 18
Propagation delay compensation (PDC) ......................................................................................... 18
Soft-start........................................................................................................................................... 20
Leading edge blanking (LEB) at CS pin ............................................................................................ 20
Spike blanking at CS pin for 2nd level over-current detection (OCP2) .......................................... 21
Gate driver output GD0 and GD1 ..................................................................................................... 21
Multi-mode operation ...................................................................................................................... 22
Frequency law setting for XDPS21081 ........................................................................................ 24
Peak current jittering ....................................................................................................................... 24
Burst mode operation ...................................................................................................................... 25
Burst mode entry ........................................................................................................................ 26
Burst operation ........................................................................................................................... 27
Burst mode exit ........................................................................................................................... 27
Quasi Resonant Mode ...................................................................................................................... 27
Forced quasi resonant ZVS mode operation................................................................................... 28
UART function at GPIO pin ............................................................................................................... 31
Protection features ............................................................................................................................... 31
Auto-Restart Mode (ARM) ................................................................................................................. 31
Latch Mode (LM) ............................................................................................................................... 32
VCC Under-Voltage lockout (UVOFF) ............................................................................................... 32
Brown-In Protection (BIP) ................................................................................................................ 32
Brown-Out Protection (BOP) ........................................................................................................... 32
Data Sheet
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Forced Quasi Resonant ZVS flyback controller
Table of contents
4.3.6
4.3.7
4.3.8
4.3.9
4.3.10
4.3.11
4.3.12
4.3.13
Over-Current Protection level 1 (OCP1) .......................................................................................... 32
Over-Current Protection level 2 (OCP2) .......................................................................................... 32
Vcc Over-Voltage Protection (VccOVP) ............................................................................................ 33
MFIO pin high (MFIOH) ..................................................................................................................... 33
Internal over-temperature detection (IntOTP) ............................................................................... 33
Primary side output Over-Voltage Protection (VoutOVP)............................................................... 33
Over load power protection............................................................................................................. 33
CS pin short protection .................................................................................................................... 34
5
5.1
5.2
5.2.1
Configuration ............................................................................................................... 35
Overview of configurable parameters using .dp Vision ....................................................................... 35
Overview of configurable parameters and functions .......................................................................... 35
Configurable parameters and functions ......................................................................................... 35
6
6.1
6.2
6.3
6.4
6.5
Electrical Characteristics ............................................................................................... 37
Definitions ............................................................................................................................................. 37
Absolute Maximum Ratings .................................................................................................................. 37
Package Characteristics ........................................................................................................................ 38
Operating Range.................................................................................................................................... 39
Characteristics ....................................................................................................................................... 40
7
7.1
7.2
Package Information ..................................................................................................... 49
Outline dimensions ............................................................................................................................... 49
Footprint and packing........................................................................................................................... 50
8
Marking ....................................................................................................................... 51
9
9.1
Appendix ..................................................................................................................... 52
Minimum required capacitive load at GD0 and GD1 pin ...................................................................... 52
10
References ................................................................................................................... 53
Revision history............................................................................................................................. 54
Data Sheet
3
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Forced Quasi Resonant ZVS flyback controller
Pin Configuration and Functionality
1
Pin Configuration and Functionality
The pin configuration is shown in Figure 2 and the functions are described in Table 1.
1
12
GND
MFIO
2
11
VCC
GPIO
3
10
GD0
CS
4
9
GD1
HV
5
8
HV
6
HV
HV
XDPS21081
ZCD
7
PG-DSO-12-20
Figure 2
Pin Configuration of XDPS21081
Table 1
Pin Definitions and Functions
Symbol
ZCD
Pin
Type
1
I
Function
Zero Crossing Detection
ZCD pin is connected to an auxiliary winding for zero crossing detection and positive
pin voltage measurement.
MFIO
2
I
Multi-Functional Input Output
MFIO pin is connected to an optocoupler that provides an amplified error signal for
the PWM mode operation.
GPIO
3
IO
CS
4
I
HV
5, 6, 7, 8 I
GD1
9
I
GD0
10
O
VCC
11
I
GND
12
O
Data Sheet
Digital General Purpose Input Output
GPIO pin provides an UART interface until brown-in. It is switched to weak
pull down mode and disabled UART function during normal operation.
Current Sense
CS pin is connected via a resistor in series to an external shunt resistor and
the source of the power MOSFET.
High Voltage Input
HV pin is connected to the rectified bulk voltage. An internally connected 600
V HV startup-cell is used for initial VCC charge. Furthermore brown-in and
brownout detection is provided.
FQR ZVS Signal Gate Driver Output
GD1 pin provides a gate driver pulse signal to initiate the forced quasi
resonant ZVS mode operation.
Gate Driver Output
Output for directly driving the main power MOSFET.
Positive Voltage Supply
IC power supply.
Power and Signal Ground
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Representative Block Diagram
2
Representative Block Diagram
Figure 3 shows a simplified top level block diagram of the IC functionality.
XDPS21081
HV
HV Startup-cell
Bang-Bang Ctrl
Startup-Cell
Driver
Closed/Open
VVCCBBoff = 20.5 V
VVCCBBonAR/LM = 9 V
Vbulk Brown-out
Protection
QM
IHVBO = 0.443 mA
D1
Vbulk
measurement
Vbulk Brown-in
Protection
Overtemperature
Detection
IHVBI = 1.15 mA
RM
VCC Brown-in
Protection
VCC
TJOTP = 130 °C
&
VVCCBI = 9.1 V
Protection
Modes
HW Reset
UVLO
VVCCon = 20.5 V
Power
Management
VVCCoffx = 7.2 V / 9.6 V
Vout OV
Protection
Vout reflected Voltage
Measurement
ZCD
1k
Auto Restart
Mode
Latch
Mode
VZCDOVP = 2.75 V
Soft-Start
ZVS ontime
Open Loop Timer
tMFIOH = 31.3 ms
Zero Crossing Detection
fSW
VMFIOH = 2.41 V
VCSPK
C2
FFR Mode
With ZVS Pulse
Generation
Frequency Law
PWM
Logic
Gate Driver
GD0
VMFIO
PDC
VVDDP = 3.3 V
VMFIO
Gate Driver
RMFIOPU
GD1
Vcs_offset
Burst Mode Function
MFIO
VMFIOBMEX1
VMFIOBMWK
C3
BM Exit
C5
on-phase
VMFIOBMPA
VMFIOBMEN
C6
off-phase
C7
BM 2-point
Regulation
BM Ctrl
BM Entry
Cycle by Cycle Peak Current Ctrl
OCP1
CS
1k
10k
VCSPK
1 pF
tCSLEB
2nd Level Overcurrent Detection
OCP2
Auto Restart
Input Detection
tCSOCP2BL
VCSOCP2 = 0.6 V
VVDDP = 3.3 V
IGPIOLPU
GPIO
Figure 3
Data Sheet
UART
Communication
Parameter
Configuration
Representative Block Diagram of XDPS21081
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Introduction
3
Introduction
The XDPS21081 is a digital AC/DC current-mode controller for high density adapter applications. The IC provides a
configurable multi-mode operation controlled by the feedback signal from the secondary side control loop. The multi-mode
operation supports different operation modes like Quasi-resonant (QR) mode, FQR ZVS mode, (see chapter 4.2.12) or burst
mode, frequency reduction mode depending on line and load conditions. With supporting those modes high power density
designs can be dressed in a very flexible manner.
An embedded application specific digital core provides advanced algorithms for the multi-mode operation and a variety of
protection features. Special analog and mixed-signal peripherals are integrated to support the requirements for low standby power.
The IC supports highest design flexibility in the application by means of an advanced set of configurable parameters and
state machines, which supports very dedicated system dimensioning. The configuration can be done via a single pin UART
interface at GPIO pin that supports in-circuit configuration. Chapter 5 contains the parameter default configuration setting
for XDPS21081 and the correlated specific firmware version. Furthermore, it provides a mapping table for the defined FW
symbols and the correlated data sheet parameters. Each listed parameter is specified in the electrical characteristics
Chapter 6.
The following functional description in Chapter 4 is based on the default parameter setting in the configuration Chapter 5.
Chapter 7.1 provides information about the package outline and dimensions.
An appendix Chapter 9 provides additional information about specific electrical characteristics or test conditions.
The reference Chapter 10 provides an overview about correlated documents.
Data Sheet
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Functional Description
4
Functional Description
The functional description gives an overview about the integrated functions and features and their relationship. The
mentioned parameters and equations are based on typical values at TA = 25 °C. The correlated minimal and maximal values
are shown in the electrical characteristics in Chapter 6.
The functional description is grouped in following sections:
Power supply management (Chapter 4.1)
Control features (Chapter 4.2)
Protection features (Chapter 4.3)
4.1
Power supply management
The power supply management ensures a reliable and robust IC operation. Depending on the operation mode of the control
IC, the power supply management unit runs in different ways for VCC supply and for brown-in monitoring, which are
described in the sequel:
•
•
•
•
•
•
VCC capacitor charge-up and startup sequence (see Chapter 4.1.1)
Brown-in monitoring (Chapter 4.1.2)
Brown-out protection response (Chapter 4.1.3)
During burst mode (QBM) operation (Chapter 4.1.4)
Bang-bang mode during latch mode (LM) operation (Chapter 4.1.5.1 )
Bang-bang mode during auto-restart mode (ARM) operation (Chapter 4.1.5.2)
4.1.1
VCC capacitor charge-up and startup sequence
There are two main functions supported at HV pin by a resistor RHV connected to the bulk capacitor (see Figure 5). They are
the VCC capacitor charge-up, and the bulk voltage monitoring (see Chapter 4.1.2).
At beginning of a cold startup, the depletion startup cell is on. Once the AC line voltage is applied and charging the bulk
capacitor, a current flows through the external resistor RHV into HV pin. Via the integrated diode D1, that current may charge
up the external VCC capacitor (see Figure 5). Once VCC voltage exceeds the threshold VVCCon = 20.5 V, the startup cell is turned
off, the control IC is enabled and the firmware boot sequence follows which takes about 1.2 ms. Both bulk voltage brown-in
and VCC brown-in condition (see Chapter 4.3.4) are checked continuously. Once they both are above the brown-in level,
respectively, the first GD0 pulse according to the soft-start control will be generated earliest after the 1.2 ms boot sequence
time. The voltage VVCC drops until the supply via the auxiliary winding (VVCCSS) takes over the VCC supply (see Figure 4). For a
proper system startup and operation, the supply voltage VVCC must be always above the VCC off-threshold VVCCoff=7.2 V (see
Chapter 4.3.3).
Data Sheet
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Functional Description
VVCC(t)
Initial startup and normal operation
VVCCon = 20.5 V
VCC brown-in window
VVCCSS
VVCCBI = 9.1 V
VVCCoffOP = 7.2 V
VCC self supply takes over
t
VHV(t)
ca. 1.2ms internal boot sequence
VVACpeak
VAC brown-in condition fulfilled
t
IVCC(t)
Start of GD0 switching
IVCCop
IVCCop1 = 7.5 mA
IVCCUVOFF = 30 µA
t
TYPICAL STARTUP SEQUENCE
Figure 4
Typical startup sequence
4.1.2
Brown-in monitoring
Once the IC is activated, brown-in monitoring is enabled for input brown-in protection (see Chapter 4.3.4) by measuring
the current at HV pin through the internal shunt resistor RM (see Chapter 4.2.2). If the input brown-in is not detected before
VCC falls below VVCCBI, the startup cell measurement unit remains enabled until VCC falls down to VVCCoff.
Data Sheet
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Forced Quasi Resonant ZVS flyback controller
Functional Description
VBULK
VAC = 85 ... 264
Vrms
CBulk
RHV = 100kW
CVCC
VCC
HV
HV Startupcell
Closed/Open
Startup-Cell
Driver
D1
Brown-in &
Brown-out
Protection
QM
IHVBI = 1.15 mA
IHVBO = 0.442mA
&
PWM
Logic
RM
VCC Brown-in
Protection
VVCCBI = 9.1 V
Power Supply
Management
UVLO
VVCCon = 20.5 V
HW Reset
VVCCoffx = 7.2 V / 9.6 V
Figure 5
High voltage brown-in sensing and VCC startup at HV pin
4.1.3
Brown-out protection
In case of brown-out (see Chapter 4.3.5), the IC stops gate driver switching. Brown-out detection is also performed via the
HV pin as for brown-in detection. Here an under-voltage detection of the bulk voltage VBulk is provided to support brown-out
protection. The measured current IHV is compared with the bulk under-voltage detection threshold IHVBO = 0.443 mA.
4.1.4
During burst mode operation
After the control IC enters quiet burst mode, the IC enters repeatedly a sleep mode, in which the IC current consumption is
reduced to IVCCquBM2 = 460 µA. Waking up from and entering this sleep mode (pause) is controlled by the feedback voltage at
MFIO pin VMFIO via the internal comparators C5 and C6 (see Figure 6 and Chapter 4.2.910).
Data Sheet
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Forced Quasi Resonant ZVS flyback controller
Functional Description
MFIO
C5
VMFIOBMWK
C6
burst-on
burst-off
BM 2-point
Regulation
BM Ctrl
Power
Management
VMFIOBMPA
Figure 6
Burst mode control
For the system dimensioning, it should be ensured that the voltage VVCC should be always well above the
threshold VVCCoff, including the burst-off phase. Figure 7 shows a typical burst mode operation signal for VCC and
correlated current consumption.
VVCC(t)
burst-on phase
VVCCSS
VVCCoff = 7.2 V
t
VMFIO(t)
burst-off phase
VMFIOBMWK = 0.26 V
VMFIOBMPA
t
VGD0(t)
t
IVCC(t)
IVCCop
IVCCquBM2 = 460 µA
t
Figure 7
Burst operation
4.1.5
Bang-bang mode during latched and auto-restart operation
The bang-bang mode supports an IC operation without external VCC supply during the latched and auto-restart operation.
It directly controls the HV startup cell depending on the set bang-bang mode turn-on threshold VVCCBBon of the corresponding
auto-restart and latch mode (see Figure 8). In latch mode, the HV startup cell switch-on threshold is set to VVCCBBon = 9 V (see
Chapter 4.1.5.1 and Chapter 4.1.5.2). In auto-restart mode, there is also an additional stand-by timer active that switches on
the HV startup cell in a fixed time period of 500ms scheme to keep the VCC all the time at a high level above the brown-in
threshold VVCCBI = 9.1 V. Then a restart can take place without going through an additional VCC brown-in cycle. Due to the low
current consumption during the auto-restart break time, the startup cell is always turned on by the 500 ms timer.
Data Sheet
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Functional Description
Protection Modes
HV
HV Startup-cell
Bang-Bang Ctrl
Startup-Cell
Driver
Closed/Open
Auto Restart
Mode
VVCCBBoff = 20.5 V
VVCCBBonAR/LM = 9 V
Latch
Mode
D1
Power
Management
VCC
Figure 8
Bang-bang mode control of HV startup-cell
4.1.5.1
During latched operation
If latch mode is entered (see Chapter 4.3.2), the IC stops gate switching and the VCC current consumption is reduced to
IVCCquLM = 150 µA. The enabled bang-bang mode ensures that the IC is kept alive by keeping the voltage at VCC pin above the
threshold VVCCoff = 7.2 V (see Figure 9). A reset of the latch mode takes place only after the VCC drops below the VVCCoff threshold.
VVCC(t)
Latch mode operation
VVCCBBoff = 20.5 V
VVCCSS
VVCCBBonLM = 9 V
VVCCoff = 7.2 V
Reset of latch mode due to low VAC
VHV(t)
t
VVACpeak
t
IVCC(t)
IVCCop
IVCCquLM = 150 µA
IVCCUVOFF = 30 µA
Figure 9
4.1.5.2
t
Latch mode operation
During auto-restart operation
Once auto-restart mode is entered (see Chapter 4.3.1), the IC stops GD0 switching, the VCC current consumption is reduced
to IVCCquAR = 160 µA, and a stand-by timer with 500 ms (tBBoffAR) period is activated which turns on the HV startup cell
periodically, to charge up the VCC capacitor. Once the voltage at VCC pin exceeds the switch-off threshold VVCCBBoff = 20.5 V,
the startup cell is turned off (see Figure 10). This is bang-bang mode operation for the VCC management during the autorestart break time. In this way, the VCC voltage is kept at a level well above the VCC brown-in threshold to ensure enough
energy stored in the VCC capacitor for the coming restart of the system, that is initiated after the auto-restart break time
tAR = 3 s. Then after an additional time ∆t = ε, the gate driver switching is activated with a soft-start sequence. Here the
additional time ε depends on the VCC capacitor charge-up time which is related to the VCC capacitance and the voltage at
HV pin.
Data Sheet
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Forced Quasi Resonant ZVS flyback controller
Functional Description
VVCC(t)
Auto-restart mode operation
VVCCBBoff = 20.5 V
VVCCSS
VVCCBI = 9.1 V
VVCCBBonAR = 9 V
VVCCoff = 7.2 V
t
tBBoffAR = 500 ms
VHV(t)
VVACpeak
Dt = e
t
IVCC(t)
IVCCop
IVCCop1 = 7.5 mA
IVCCquAR = 160 µA
t
VGD0(t)
tAR = 3s
VGD0H = 10.5 V
t
Figure 10
4.2
Auto-restart mode operation
Control features
The XDPS21081 provides peak current control assisted by the features listed in Table 2. A simplified block diagram
representing the controller features is shown in Figure 11.
Data Sheet
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Functional Description
CS
tCSOCP2BL
VCSOCP2
VCS
FF
Cold Start,
BM Wake-Up,
Autorestart
Soft-Start
Control
VVDDP
HV
VMFIO
frequency law,
burst mode control
IHV
VBulk
Measurment
&
SET
&
+
VCSOCP1
stop GD0
VCSSS
M
I
N
Multi-Mode
Control
MFIO
GD0
CLEAR
+
&
CLEAR
FF
tCSLEB
SET
Propagation
Delay
Compensation
tZCDRS
Vcs_offset
start GD0
Start Request
Generator
ZCD
Vout
Measurement
fSW
FFR ZVS
PWM
Generator
GD1
ZCD
MULTIMODE_OVERVIEW_DIGITAL
Figure 11
Block Diagram of PWM Control
Table 2 gives an overview about the controller features that are described in the mentioned chapters.
Table 2
Controller Features
Reflected voltage sensing and zero crossing detection at auxiliary winding
Chapter 4.2.1
Vbulk voltage measurement via HV startup cell
Chapter 4.2.2
Propagation delay compensation (PDC)
Chapter 4.2.3
Soft-start
Chapter 4.2.4
Leading edge blanking (LEB) time at CS pin
Chapter 4.2.5
Spike blanking at CS pin for 2nd level over-current detection
Chapter 4.2.6
Gate driver output GD0 and GD1
Chapter 4.2.7
Multi-mode operation
Chapter 4.2.8
Burst mode (QBM) operation
Chapter 4.2.10
Forced quasi resonant mode
Chapter 4.2.11
Forced quasi resonant ZVS mode operation
Chapter 4.2.12
UART function at GPIO pin
Chapter 4.2.13
Data Sheet
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Functional Description
4.2.1
Reflected voltage sensing and VCS offset calculation based on
output voltage
The IC provides output voltage detection by means of measuring the reflected voltage at the auxiliary winding VAux at the
primary side of the transformer via ZCD pin and an external resistive voltage divider. The voltage signal VAux contains the
information of the flyback output voltage, VOut, at the secondary side.
The ZCD pin related circuit is shown in Figure 12. Figure 13 shows a typical voltage waveform of the drain voltage VDrain and
the related auxiliary winding voltage VAux. The sensed output voltage is used for over-voltage protection (see Chapter 4.3.11).
Following topics are described in the sequel:
•
•
Output voltage sensing via ZCD pin (Chapter 4.2.1.1)
Vcs offset with sensed Vo at ZCD pin (Chapter 4.2.1.3)
vPri
vSec
VOu t
VBulk
vDrain
RZCDH
iZCD
vAux
RZCDL
ZCD
vZCD
GND
vZVS
VOLTAGE_SENSING_OVERVIEW
Figure 12
Data Sheet
Functionality at ZCD pin
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Functional Description
vDrain (t)
NPri / NSec × vSec
VBulk
0
t
Free-wheeling phase
vAux(t)
Oscillation phase
NAux / NSec × vSec
0
t
NAux / NPri × VBulk
1 1 1 1
4 4 4 4
tOn
tf
tOsc
tOff
iMag(t)
t
VOLTAGE_SENSING_SIGNALS
Figure 13
Auxiliary voltage and magnetization current waveforms for standard discontinuous
conduction mode operation
4.2.1.1
Output voltage sensing via ZCD pin
Output voltage is sensed at a fixed point of time during the free-wheeling phase. The free-wheeling phase begins when the
gate driver is switched off and ends when the secondary side demagnetization current becomes zero. During free-wheeling
phase the VCC capacitor of the IC, the output stage and the additional ZVS capacitor at ZVS winding for introducing a forced
resonant cycle (see Chapter 4.2.12) are supplied. As soon as VCC capacitor is charged, the auxiliary voltage is a function of
secondary side voltage.
𝑽𝑨𝑼𝑿 =
𝑵𝑨𝑼𝑿
𝑵𝑺𝒆𝒄
(1)
∙ 𝑽𝑺𝒆𝒄
Figure 14 shows the schematic related to secondary side voltage sensing and the equivalent network.
Data Sheet
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Functional Description
NSec :NAux
RZCDH
vSec (t)
iZCD=0
vAux(t)
RZCDL
ZCD
vZCD>0
GND
ZCD
vZCDSEC (vSec )
+
GND
VOLTAGE_SENSING_ZCDSH
Figure 14
Secondary Side Voltage Sensing
No current clamping applies during the free-wheeling time and the voltage at ZCD pin is given by
𝑽𝒁𝑪𝑫𝑺𝑬𝑪 (𝑽𝑺𝒆𝒄 ) = 𝑹𝒁𝑪𝑫∙ (
𝑽𝑨𝑼𝑿
𝑹𝒁𝑪𝑫𝑯
(2)
)
RZCD is the internal resistance of VZCDSEC (VSec) and is the equivalent parallel resistance of RZCDH and RZCDL. The related waveforms
are presented in Figure 15. After the primary side gate driver is turned off, the auxiliary voltage goes from its negative level
to positive. After a ringing phase, the positive level is given by the output voltage plus the secondary side diode voltage drop.
During the free-wheeling phase the secondary side diode operates in the linear region until the demagnetization current
becomes very small. This linear relationship can be described as a resistor RDSonSec, resulting in a falling slope according to
RDSonSec·iLSec(t). The secondary side current iLSec(t) decreases with a slope given by the output voltage and the transformer
secondary side inductance. Hence the resulting auxiliary winding voltage is more or less constant until the secondary side
current becomes zero. The reflected voltage at auxiliary winding is sampled at the end of the ringing suppression time (see
Chapter 4.2.1.2). The measured voltage VZCDSEC includes the output voltage level and a superimposed offset ∆VZCDOFFSET that is
depending on the secondary side chosen rectification approach and the associated component dimensioning.
To ensure an accurate measurement of the reflected output voltage, the system dimensioning must provide a free-wheeling
phase that only finishes after the ringing suppression time tZCDRS.
Furthermore following effects can influence the output voltage sensing if not properly considered in system dimensioning:
• VCC and ZVS capacitor charging
• Voltage drop on secondary side at the free-wheeling diode or the secondary side switch
The VCC and ZVS capacitors need to be charged up before the ringing suppression time tZCDRS ends. The superimposed
voltage offset ∆VZCDOFFSET at sample time point due to secondary side rectification approach needs to be considered either by
the dimensioning of the ZCD resistor divider or the internal overvoltage threshold setting VZCDOVP (see Chapter 4.3.11).
Data Sheet
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Functional Description
tGD0offZC
tf
vGD0(t)
tOsc/4
tZCDRS
t
vZCD(t)
Voltage sampling
DVZCDOFFSET
VZCDSEC(VSec )
VZCDVO(VOut)
VZCDTHR
t
VZCDclp
Ringing
suppression
VOLTAGE_SENSING_SIGNALS_ZCDSH
Figure 15
Output Voltage Sensing Signals
4.2.1.2
Ringing suppression time
To prevent erroneous ZCD events due to primary side gate driver turn off ringing, a ringing suppression time tZCDRS = 0.6µs
applies for the zero-crossing events. During this time no zero-crossing is considered.
4.2.1.3
Vcs offset calculation based on output voltage sensed at ZCD pin
To limit the output current at different output voltage, a linear scaled Vcs offset is inserted to the peak current command.
This offset will be minused from the current command mapping from the frequency law curve.
It is an inverse of the output voltage based on positive ZCD winding voltage. Figure 16 shows when the Vzcd is at
Vzcd_zero_point, the Vcs offset is zero. While Vzcd voltage is at minimum level, the V cs offset is maximum. The Vcs offset level
depends on the slew rate of Kvcs_offset and the starting point of Vzcd. The equation is as below:
𝑽𝒄𝒔𝒐𝒇𝒇𝒔𝒆𝒕 = 𝑲𝒗𝒄𝒔𝒐𝒇𝒇𝒔𝒆𝒕 ∗ (𝑽𝒛𝒄𝒅 − 𝑽𝒛𝒄𝒅_𝒛𝒆𝒓𝒐_𝒑𝒐𝒊𝒏𝒕)/𝟔𝟓𝟓𝟑𝟔
(3)
All the number in above equation is decimal digital value.
At ZCD pin, the sensed voltage will minus 1.2V offset first, then feed into an ADC channel to get the sense the voltage. Also
due to the ADC input voltage range is 1.2-2.8V, so any ZCD voltage out of this range is ignored by the IC and ADC converter
value will be saturated at its min(0) and max value(255).
Below is the example on how to set the value,
Vzcd_zero_point is the voltage level without compensation, here we choose Vzcd=1.69V, the digital value of Vzcd_zero_point_dig=(1.691.2)*1.5/2.4*256=79, Kvcsoffset=20000, for Vzcd=1.2V, the digital value of it will be
Vzcd_dig=(1.2-1.2)*1.5/2.4*256=0, so Vcsoffset_dig=20000*(0-79)/65536=24, its analog value will be 24/256*400=38mV.
If system parameters like transformer turns ratio, ZCD pin voltage divider is known, then the corresponding output voltage
can be calculated. E.g. Naux=2, Nsec=2, RzcdH is 39kohm, RzcdL is 5.6kohm.
𝑽𝒐 = 𝑽𝒛𝒄𝒅 ∗
Data Sheet
𝑵𝒔𝒆𝒄
𝑵𝒂𝒖𝒙
(4)
∗ (𝑹𝒛𝒄𝒅𝑳 + 𝑹𝒛𝒄𝒅𝑯 )/𝑹𝒛𝒄𝒅𝑳
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Functional Description
So for Vzcd=1.69V, Vo will be 1.69*2/2*(39+5.6)/5.6=13.46V assuming transformer coupling is 1.
For Vzcd=1.2V, Vo will be 1.2*2/2*(39+5.6)/5.6=9.56V.
This means that when output voltage is above 13.46V, there is no Vcs offset compensation, below 9.56V the compensation is
clamped at 38mV as calculated above.
Vzcd
Vzcd_zero_point
Kvcs_offset
Vzcd_LowV
Vcs offset
Vcs_offset
VCSOF F SET
Figure 16
Vcs_offset calculation
4.2.2
Vbulk voltage measurement via HV startup cell
The VBulk voltage is measured via the HV pin that is connected at the bulk capacitor node. The current IHV is sampled in the IC
and processed for the following functions:
•
•
•
Brown-in protection ( Chapter 4.3.4)
Brown-out protection (Chapter 4.3.5),
Propagation delay compensation (Chapter 4.2.3),
In all these functions, the current IHV represents the bulk voltage.
4.2.3
Propagation delay compensation (PDC)
Due to the gate driver turn-off propagation delay tPD, the level VCSOCP1 set by the OCP1 comparator will not directly control
the inductor peak current, ILPk.
Without propagation delay, the peak current would be given by ILPk = RCS-1·VCSOCP1. However, due to the propagation delay,
the OCP1 level is exceeded by
(5)
𝑹𝑪𝑺 ∙ 𝑰𝑳𝒑𝒌 = 𝑽𝑪𝑺𝑶𝑪𝑷𝟏 + 𝑽𝑪𝑺𝑷𝑫 (𝑽𝑩𝒖𝒍𝒌 )
Where the propagation delay overshoot VCSPD(VBulk) is
𝑽𝑪𝑺𝑷𝑫 (𝑽𝑩𝒖𝒍𝒌 ) =
𝑹𝑪𝑺
𝑳𝑷𝒓𝒊
(6)
∙ 𝒕𝑷𝑫 ∙ 𝑽𝑩𝒖𝒍𝒌
In Figure 17 related example waveforms are presented.
Data Sheet
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Functional Description
vGD0(t)
vGD0(t)
t
t
vDrain(t)
vDrain(t)
VBulkHL
VBulkLL
t
t
vCS(t)
vCS(t)
tPD
tPD
tCS
RCSILpk(t)
dvCS/dt
dvCS/dt
t
VCSOCP1
tCS
VCSOCP1
RCSILpk
RCSILpk(t)
t
MULTIMODE_PDC
Figure 17
Propagation Delay and Propagation Delay Compensation
On the left side, the bulk voltage is low, the slope of inductor current and of the CS voltage are low, too. When the CS voltage
reaches the OCP1 level, the gate driver turns off and the inductor current reaches its peak after the turn off propagation
delay tPD. The turn off propagation delay tPD includes the delay tCS of the filter capacitor connected to CS pin and the resistor
connected between shunt resistor and CS pin (see Typical Application Figure). The overshoot of the inductor current due to
propagation delay is small due to the small slope
𝒅𝑽𝑪𝑺
𝒅𝒕
=
𝑹𝑪𝑺 ∙𝑽𝑩𝒖𝒍𝒌
(7)
𝑳𝒑
The right side of Figure 17 shows the same operating waveforms for a higher bulk voltage. In this case, the OCP1 comparator
limit needs to be less than on the left side to reach the same inductor peak current. Although the propagation delay remains
the same, the slope as well as the overshoot due to propagation delay is larger.
The XDPS21081 controller is defined to measure the HV current IHV representing the bulk voltage VBulk. The OCP1 comparator
limit is adjusted depending on the measured bulk voltage so that the real peak current due to the propagation delay is
compensated. For this HV pin needs to be connected to VBulk.
Consequently, any CS peak parameter VCSx is specified in the electrical characteristics (Chapter 6.5) for a low-line use case
(VCSxLL) and for a high-line use case (VCSxHL).
Low-Line Use Case (LL)
•
•
IHVLL = 70 µA as for VBulk = 72 V, RHV = 100 kΩ
(dvCS /dt)LL = 49 mV/µs as for VBulk = 72 V, LPri = 200 µH, RCS = 0.135 Ω
High-Line Use Case (HL)
•
•
IHVHL = 370 µA as for VBulk = 372 V, RHV = 100 kΩ
(dvCS /dt)HL = 251 mV/µs as for VBulk = 372 V, LPri = 200 µH, RCS = 0.135 Ω
These use cases set the corners of the propagation delay compensation which operates in a linear manner so that the typical
OCP1 threshold for any IHV is given by
𝑽𝑪𝑺𝒙 (𝑰𝑯𝑽 )−𝑽𝑪𝑺𝒙𝑳𝑳
𝑰𝑯𝑽 −𝑰𝑯𝑽𝑳𝑳
Data Sheet
=
𝑽𝑪𝑺𝒙𝑯𝑳 −𝑽𝑪𝑺𝒙𝑳𝑳
(8)
𝑰𝑯𝑽𝑯𝑳 −𝑰𝑯𝑽𝑳𝑳
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Functional Description
4.2.4
Soft-start
The IC control provides a soft-start during initial startup and auto-restart cycles. The soft-start slew rate is defined by the
step ∆VCSS = 1.7 mV taking place every time step of tBase1 = 52.14 µs. Furthermore, the peak current start level is determined
by the parameter VCSSS.
The soft-start phase is latest finished after VCS has ramped up to the maximum level of VCSmax (see Figure 18).
The total soft-start time tSSmax is therefore based on the following equation:
𝒕𝑺𝑺𝒎𝒂𝒙 = 𝒕𝑩𝒂𝒔𝒆𝟏 ∙
𝑽𝑪𝑺𝒎𝒂𝒙 −𝑽𝑪𝑺𝑺𝑺
(9)
∆𝑽𝑪𝑺𝑺
The associated ramped up peak current limitation is determined by internal digital numbers, which are not depending on
the propagation delay during peak current limitation process.
VCS(t)
tSSmax
VCSmax
DVCSS
tBase1
VCSSS
t
Figure 18
Soft-start timing
The internal soft-start phase is finished once the voltage level at MFIO pin is getting lower than 2.42 V. Then the setting for
CS limitation is determined by the feedback signal at MFIO pin via the frequency law (see Chapter 4.2.8.1).
4.2.5
Leading edge blanking (LEB) at CS pin
A digital leading edge blanking filter with tCSLEB = 269 ns (see Chapter 5) is integrated in the OCP1 peak current control path
to prevent the current limitation process from distortions, caused by the leading edge spike at the switch-on of the power
MOSFET (see Figure 19). The LEB applies only for the OCP1 comparator (see Figure 3) that is used for cycle-by-cycle peak
current limitation. The LEB needs also to ensure a monotonous peak current control without being impacted by ringing
taking place directly after the leading edge spike.
VGD0(t)
t
VCS(t)
tCSLEB
VCSOCP1
t
Figure 19
Data Sheet
Leading edge blanking
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Functional Description
4.2.6
Spike blanking at CS pin for 2nd level over-current detection
(OCP2)
A further comparator OCP2 is implemented at CS pin (see Figure 3) to detect dangerous current levels (see Chapter 5), which
could occur if one or more transformer windings are shorted or if the secondary side diode is shorted. To avoid an accidental
trigger by exceeding this 2nd level over-current protection threshold VCSOCP2 = 0.6 V, a spike blanking time tCSOCP2BL = 616.2 ns
(see Chapter 5) is implemented in the output path of the OCP2 comparator.
4.2.7
Gate driver output GD0 and GD1
The gate driver GD0 and GD1 are of the same type. The GD0 is used for controlling the main MOSFET connected to the primary
main inductance of the flyback transformer. The GD1 is used for controlling the FQR ZVS mode (see Chapter 4.2.8) by driving
the dedicated MOSFET that is connected to the ZVS winding at the flyback transformer.
The gate driver output stages consist of a regulated current source connected to VCC pin and a MOSFET switch connected
to GND (see Figure 20 and Figure 21). The peak source current at GDx is set to IGDxHPKSRC = -35 mA. The MOSFET switch provides
a discharge path for the main power MOSFET with a sink capability of RGDxLSNK ≤ 6.5 Ω.
The controlled source current determines together with the gate-source capacitance CGS and the gate-drain capacitance CGD
of the external power MOSFET the rising slope during turn-on phase (see Figure 22). The gate driver state control ensures
that the charged gate driver output voltage is clamped at the level VGDxH = 10.5 V.
The external gate resistor RGDx is therefore only meant for adjusting the peak sink current and the corresponding gate voltage
falling slope during the turn-off phase. Here the turn-on behavior is mainly dominated by the controlled limited current
source IGDxHPKSRC as the size of the external gate resistor is mainly limiting the higher peak sink current at GDx pin. When
dimensioning the serial gate resistor RGDx, also a minimum load capacitance needs to be considered after RGDx (see Chapter
9.1), which needs to be provided by the corresponding gate-source capacitance CGS of the external power MOSFET. This
ensures a smooth and stable settling of the voltage level VGDxH at the end of the turn-on phase.
Primary main
inductance
VCC
VCC
Source current
control
Flyback
ctrl
Power
MOSFET VD
IGD0HPKSRC
Q1
CGD
Gate driver
state control
RGD0
GD0
CGS
VGD0H
RGD0LSNK
CS
RCS
GND
Figure 20
Data Sheet
GD0 output stage structure
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Functional Description
ZVS-winding
VCC
VCC
Source current
control
Power
MOSFET VD
IGD1HPKSRC
CGD
Gate driver
state control
FFR mode
pulse control
Q2
RGD1
GD1
CGS
VGD1H
RGD1LSNK
GND
Figure 21
GD1 output stage structure
VGDx(t)
turn-on phase
VGDxH = 10.5 V
dVGDx/dt is determined
by IGDxHPKSRC and CGS
The turn-off phase is determined by
RGDx, RGDxLSNK, CGS, CGD and VD
Miller plateau is determined by
IGDxHPKSRC, CGD and VD
t
tGDxon
Figure 22
Gate drive output
4.2.8
Multi-mode operation
The multi-mode operation consists of two different operation modes that are controlled by the feedback voltage signal at
MFIO pin (see Table 3).
Table 3
Overview multi-modes
Symbol
Operation Mode
Description
BM
Burst mode
Chapter 4.2.10
QRM
Quasi resonant mode at low line
Chapter 4.2.11
FQRZVSM
Forced quasi resonant ZVS mode during BM and DCMx operation at high line
Chapter 4.2.12
The configurable multi-mode operation depends on the inductance design, switching frequency, load condition and the
bulk voltage VBulk. It is characterized by the frequency scheme and peak current correlation shown in Figure 23. The peak
current limit VCSPK (y-axis) and the frequency limits are set according to the input signal at MFIO pin. The peak current limits
for VCSPK are shown for the low and high-line use case (see Chapter 4.2.3), which consider the propagation delay
Data Sheet
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Functional Description
compensation (PDC). The border for entering the burst mode (BM) is determined by the setpoint D. The actual peak
current and the actual switching frequency areas follow:
•
•
•
•
•
In DCM1 and DCM2 operation, the peak current and the switching frequency are directly given by the curve F-E-D.
In DCM1 the peak current changes with the voltage VMFIO and the switching frequency is fixed.
In DCM2 the peak current is fixed, and the switching frequency changes with VMFIO.
During QRM, the peak current changes with the voltage VMFIO and the switching frequency limited by the curve A-B-C-D.
the multi-mode controller selects the operating mode (BM, DCM1, DCM2, QRM / FQRZVS )
The following Figure 23 shows an example of using all possible multi-mode operation phases that are determined by the
corresponding setpoints A, B, C, D, E and F. The specific frequency law setting for XDPS21081 based on the FW: REV 1.0 is
shown in Chapter 4.2.8.1.
fSW(VMFIO)
fSWmax
B
A
QRM
f sw_
C
mi n
D
fSWmin
F
ABM
E
DCM1
DCM2
VMFIO
VMFIOBMEN
VMFIOD VMFIOC
VMFIOB
VMFIOmax
VCSPK(VMFIO)
VCSmax
A
B
VCSC
VCSmin
E
D
F
VMFIO
MULTIMODE_FREQLAW
Figure 23
Data Sheet
Configurable frequency law and peak current schemes depending on signal at MFIO pin
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4.2.8.1
Frequency law setting for XDPS21081
The frequency law setting for XDPS21081 based on the is defined by the set point A, B, C ,D,E and F as shown in Table 4.
Table 4
Corner points for frequency limitation curve and peak current setting for XDPS21081
Assuming LL (low line) =72V, HL (high line) =372V, LPRI=200uH, RCS=0.135 Ω
Setpoint
A
Corner point for maximum current
VMFIOA = 2.30V
fSWmax = 145 kHz
VCSmaxLL = 402mV
VCSmaxHL = 368mV
B
Corner point for border between DCM3 and DCM2 for frequency reduction
VMFIOB = 1.61V
fSWB = 145 kHz
VCSBLL = 336 mV
VCSBHL = 303mV
C
Corner point for border between DCM2 and DCM1 for fixed frequency and peak current reduction
VMFIOC = 2.30V
fSWC = 120 kHz
VCSCLL = 402mV
VCSCHL = 368mV
D
Corner point at minimum frequency setting
VMFIOD = 1.23V
fSWD = 83.7 kHz
VCSDLL = 260mV
VCSminHL = 227mV
E
Corner point at minimum frequency setting
VMFIOE = 0.86 V
fSWE = 23 kHz
VCSELL = 260mV
VCSminHL = 227mV
F
Corner point at minimum frequency setting
VMFIOF = 0.21V
fSWmin = 23 kHz
VCSminLL = 67mV
VCSminHL = 33mV
4.2.9
Peak current jittering
In order to improve the EMI performance, the XDPS21081 enables peak current jittering at middle to heavy load
when Vmfio is larger than 1.0V and Input bulk voltage above 175Vdc (assuming RHV=100K), and disable once
Data Sheet
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Functional Description
Vmfio is lower than 0.9V or input bulk voltage is lower than 150V (assuming RHV=100K). The jitter of current will
cause frequency jittering which improves the EMI spectrum signature.
Both the peak current amplitude and peak current period will jitter over time as shown in Figure24. The default
jittering magnitude is ± 15.625mV and the jittering period is 1ms.
IPK + Ajitter_Max
Ajitter_Max / 10 points
Ipk
IPK - AjitterMax
t
100µs
Jitter Period = 10 points * 100µs = 1000µs
Figure 24
Table 5
Jittering magnitude and period
Peak current jitter parameters
Parameter Name
Physical value
Enable jitter condition
Disable jitter condition
A_Jitter_max
15.625mV
A_Jitter_period_val
1ms
Vbulk>=175Vdc and
Vmfio>=1.0V,
Assuming RHV=100K
Vbulk
