XMC1200 AB-Step
Microcontroller Series
for Industrial Applications
XMC1000 Family
ARM® Cortex®-M0
32-bit processor core
Data Sheet
V1.8 2016-09
Microcontrollers
Edition 2016-09
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2016 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
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characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
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and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
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be endangered.
XMC1200 AB-Step
Microcontroller Series
for Industrial Applications
XMC1000 Family
ARM® Cortex®-M0
32-bit processor core
Data Sheet
V1.8 2016-09
Microcontrollers
XMC1200 AB-Step
XMC1000 Family
XMC1200 Data Sheet
Revision History: V1.8 2016-09
Previous Version: V1.7 2016-09
Page
Subjects
Page 32,
Page 33
In Absolute Maximum Ratings renamed parameter VCM to VINP2, as the
limitation is related to most P2 pins, also if no ACMP is available.
Clarified limit to pins P2.[1,2,6:9,11] in Overload specification.
Trademarks
C166™, TriCore™, XMC™ and DAVE™ are trademarks of Infineon Technologies AG.
ARM®, ARM Powered® and AMBA® are registered trademarks of ARM, Limited.
Cortex™, CoreSight™, ETM™, Embedded Trace Macrocell™ and Embedded Trace
Buffer™ are trademarks of ARM, Limited.
We Listen to Your Comments
Is there any information in this document that you feel is wrong, unclear or missing?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
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Data Sheet
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1200 AB-Step
XMC1000 Family
Table of Contents
Table of Contents
1
1.1
1.2
1.3
1.4
Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Device Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Device Type Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Chip Identification Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2
2.1
2.2
2.2.1
2.2.2
2.2.3
General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Configuration and Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port I/O Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Controlled I/O Function Description . . . . . . . . . . . . . . . . . . .
14
14
16
20
24
25
3
3.1
3.1.1
3.1.2
3.1.3
3.1.4
3.2
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.2.6
3.2.7
3.3
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
3.3.6
3.3.6.1
3.3.6.2
3.3.6.3
Electrical Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Reliability in Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input/Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog to Digital Converters (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . .
Out of Range Comparator (ORC) Characteristics . . . . . . . . . . . . . . . . .
Analog Comparator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .
Temperature Sensor Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-Up and Supply Monitoring Characteristics . . . . . . . . . . . . . . . .
On-Chip Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Wire Debug Port (SW-DP) Timing . . . . . . . . . . . . . . . . . . . . . . .
SPD Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peripheral Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synchronous Serial Interface (USIC SSC) Timing . . . . . . . . . . . . . .
Inter-IC (IIC) Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Inter-IC Sound (IIS) Interface Timing . . . . . . . . . . . . . . . . . . . . . . . .
31
31
31
32
33
35
36
36
40
44
46
47
48
53
54
54
55
57
59
60
61
61
64
66
4
4.1
4.1.1
4.2
Package and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
68
68
68
70
Data Sheet
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XMC1200 AB-Step
XMC1000 Family
Table of Contents
5
Data Sheet
Quality Declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1200 AB-Step
XMC1000 Family
About this Document
About this Document
This Data Sheet is addressed to embedded hardware and software developers. It
provides the reader with detailed descriptions about the ordering designations, available
features, electrical and physical characteristics of the XMC1200 series devices.
The document describes the characteristics of a superset of the XMC1200 series
devices. For simplicity, the various device types are referred to by the collective term
XMC1200 throughout this document.
XMC1000 Family User Documentation
The set of user documentation includes:
•
•
•
Reference Manual
– decribes the functionality of the superset of devices.
Data Sheets
– list the complete ordering designations, available features and electrical
characteristics of derivative devices.
Errata Sheets
– list deviations from the specifications given in the related Reference Manual or
Data Sheets. Errata Sheets are provided for the superset of devices.
Attention: Please consult all parts of the documentation set to attain consolidated
knowledge about your device.
Application related guidance is provided by Users Guides and Application Notes.
Please refer to http://www.infineon.com/xmc1000 to get access to the latest versions
of those documents.
Data Sheet
7
V1.8, 2016-09
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XMC1200 AB-Step
XMC1000 Family
Summary of Features
1
Summary of Features
The XMC1200 devices are members of the XMC1000 Family of microcontrollers based
on the ARM Cortex-M0 processor core. The XMC1200 series devices are optimized for
LED Lighting and Human-Machine interface (HMI) applications.
Cortex-M0
CPU
Analog system
EVR
2 x DCO
Debug
system
NVIC
SWD
SPD
ANACTRL SFRs
PRNG
16-bit APB Bus
Temperature sensor
AHB to APB
Bridge
PAU
AHB-Lite Bus
Flash SFRs
200k + 0.5k1)
Flash
PORTS
CCU40
ACMP &
ORC
16k
SRAM
WDT
USIC0
BCCU0
8k ROM
SCU
VADC
LEDTS0
ERU0
LEDTS1
RTC
Memories
1) 0.5kbytes of sector 0 (readable only).
Figure 1
System Block Diagram
CPU Subsystem
•
CPU Core
– High-performance 32-bit ARM Cortex-M0 CPU
– Most 16-bit Thumb and subset of 32-bit Thumb2 instruction set
– Single cycle 32-bit hardware multiplier
Data Sheet
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XMC1200 AB-Step
XMC1000 Family
Summary of Features
•
•
– System timer (SysTick) for Operating System support
– Ultra low power consumption
Nested Vectored Interrupt Controller (NVIC)
Event Request Unit (ERU) for processing of external and internal service requests
On-Chip Memories
•
•
•
8 kbytes on-chip ROM
16 kbytes on-chip high-speed SRAM
up to 200 kbytes on-chip Flash program and data memory
Communication Peripherals
•
•
Two Universal Serial Interface Channels (USIC), usable as UART, double-SPI,
quad-SPI, IIC, IIS and LIN interfaces
LED and Touch-Sense Controller (LEDTS) for Human-Machine interface
Analog Frontend Peripherals
•
•
•
•
A/D Converters
– up to 12 analog input pins
– 2 sample and hold stages with 8 analog input channels each
– fast 12-bit analog to digital converter with adjustable gain
Up to 8 channels of out of range comparators (ORC)
Up to 3 fast analog comparators (ACMP)
Temperature Sensor (TSE)
Industrial Control Peripherals
•
•
Capture/Compare Units 4 (CCU4) as general purpose timers
Brightness and Colour Control Unit (BCCU), for LED color and dimming application
System Control
•
•
•
•
Window Watchdog Timer (WDT) for safety sensitive applications
Real Time Clock module with alarm support (RTC)
System Control Unit (SCU) for system configuration and control
Pseudo random number generator (PRNG) for fast random data generation
Input/Output Lines
•
•
•
•
•
Programmable port driver control module (PORTS)
Individual bit addressability
Tri-stated in input mode
Push/pull or open drain output mode
Configurable pad hysteresis
Data Sheet
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XMC1200 AB-Step
XMC1000 Family
Summary of Features
On-Chip Debug Support
•
•
Support for debug features: 4 breakpoints, 2 watchpoints
Various interfaces: ARM serial wire debug (SWD), single pin debug (SPD)
1.1
Ordering Information
The ordering code for an Infineon microcontroller provides an exact reference to a
specific product. The code “XMC1-” identifies:
•
•
•
•
•
the derivatives function set
the package variant
– T: TSSOP
– Q: VQFN
package pin count
the temperature range:
– F: -40°C to 85°C
– X: -40°C to 105°C
the Flash memory size.
For ordering codes for the XMC1200 please contact your sales representative or local
distributor.
This document describes several derivatives of the XMC1200 series, some descriptions
may not apply to a specific product. Please see Table 1.
For simplicity the term XMC1200 is used for all derivatives throughout this document.
1.2
Device Types
These device types are available and can be ordered through Infineon’s direct and/or
distribution channels.
Table 1
Synopsis of XMC1200 Device Types
Derivative
Package
Flash
Kbytes
SRAM
Kbytes
XMC1201-T028F0016
PG-TSSOP-28-16
16
16
XMC1201-T028F0032
PG-TSSOP-28-16
32
16
XMC1201-T038F0016
PG-TSSOP-38-9
16
16
XMC1201-T038F0032
PG-TSSOP-38-9
32
16
XMC1201-T038F0064
PG-TSSOP-38-9
64
16
XMC1201-T038F0128
PG-TSSOP-38-9
128
16
XMC1201-T038F0200
PG-TSSOP-38-9
200
16
XMC1200-T038F0200
PG-TSSOP-38-9
200
16
Data Sheet
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V1.8, 2016-09
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XMC1200 AB-Step
XMC1000 Family
Summary of Features
Table 1
Synopsis of XMC1200 Device Types (cont’d)
Derivative
Package
Flash
Kbytes
SRAM
Kbytes
XMC1202-T028X0016
PG-TSSOP-28-16
16
16
XMC1202-T028X0032
PG-TSSOP-28-16
32
16
XMC1202-T028X0064
PG-TSSOP-28-16
64
16
XMC1202-T016X0016
PG-TSSOP-16-8
16
16
XMC1202-T016X0032
PG-TSSOP-16-8
32
16
XMC1202-T016X0064
PG-TSSOP-16-8
64
16
XMC1202-Q024X0016
PG-VQFN-24-19
16
16
XMC1202-Q024X0032
PG-VQFN-24-19
32
16
XMC1201-Q040F0016
PG-VQFN-40-13
16
16
XMC1201-Q040F0032
PG-VQFN-40-13
32
16
XMC1201-Q040F0064
PG-VQFN-40-13
64
16
XMC1201-Q040F0128
PG-VQFN-40-13
128
16
XMC1201-Q040F0200
PG-VQFN-40-13
200
16
XMC1202-Q040X0016
PG-VQFN-40-13
16
16
XMC1202-Q040X0032
PG-VQFN-40-13
32
16
1.3
Device Type Features
The following table lists the available features per device type.
Table 2
Features of XMC1200 Device Types1)
Derivative
ADC channel
ACMP
BCCU
LEDTS
XMC1200-T038
16
3
1
2
XMC1201-T028
14
-
-
2
XMC1201-T038
16
-
-
2
XMC1202-T028
14
3
1
-
XMC1202-T016
11
2
1
-
XMC1202-Q024
13
3
1
-
XMC1201-Q040
16
-
-
2
XMC1202-Q040
16
3
1
-
1) Features that are not included in this table are available in all the derivatives
Data Sheet
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XMC1200 AB-Step
XMC1000 Family
Summary of Features
ADC Channels 1)
Table 3
Package
VADC0 G0
VADC0 G1
PG-TSSOP-16
CH0..CH5
CH0..CH4
PG-TSSOP-28
CH0..CH7
CH0 .. CH4, CH7
PG-TSSOP-38
CH0..CH7
CH0..CH7
PG-VQFN-24
CH0..CH7
CH0..CH4
PG-VQFN-40
CH0..CH7
CH1, CH5 .. CH7
1) Some pins in a package may be connected to more than one channel. For the detailed mapping see the Port
I/O Function table.
1.4
Chip Identification Number
The Chip Identification Number allows software to identify the marking. It is a 8 words
value with the most significant 7 words stored in Flash configuration sector 0 (CS0) at
address location : 1000 0F00H (MSB) - 1000 0F1BH (LSB). The least significant word and
most significant word of the Chip Identification Number are the value of registers
DBGROMID and IDCHIP, respectively.
Table 4
XMC1200 Chip Identification Number
Derivative
Value
Marking
XMC1201-T028F0016
00012022 01CF00FF 00001FF7 00006000
00000C00 00001000 00005000 201ED083H
AB
XMC1201-T028F0032
00012022 01CF00FF 00001FF7 00006000
00000C00 00001000 00009000 201ED083H
AB
XMC1201-T038F0016
00012012 01CF00FF 00001FF7 00006000
00000C00 00001000 00005000 201ED083H
AB
XMC1201-T038F0032
00012012 01CF00FF 00001FF7 00006000
00000C00 00001000 00009000 201ED083H
AB
XMC1201-T038F0064
00012012 01CF00FF 00001FF7 00006000
00000C00 00001000 00011000 201ED083H
AB
XMC1201-T038F0128
00012012 01CF00FF 00001FF7 00006000
00000C00 00001000 00021000 201ED083H
AB
XMC1201-T038F0200
00012012 01CF00FF 00001FF7 00006000
00000C00 00001000 00033000 201ED083H
AB
XMC1200-T038F0200
00012012 01CF00FF 00001FF7 0000E000
00000C00 00001000 00033000 201ED083H
AB
Data Sheet
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XMC1200 AB-Step
XMC1000 Family
Summary of Features
Table 4
XMC1200 Chip Identification Number (cont’d)
Derivative
Value
Marking
XMC1202-T028X0016
00012023 01CF00FF 00001FF7 00008000
00000C00 00001000 00005000 201ED083H
AB
XMC1202-T028X0032
00012023 01CF00FF 00001FF7 00008000
00000C00 00001000 00009000 201ED083H
AB
XMC1202-T028X0064
00012023 01CF00FF 00001FF7 00008000
00000C00 00001000 00011000 201ED083H
AB
XMC1202-T016X0016
00012033 01CF00FF 00001FF7 00008000
00000C00 00001000 00005000 201ED083H
AB
XMC1202-T016X0032
00012033 01CF00FF 00001FF7 00008000
00000C00 00001000 00009000 201ED083H
AB
XMC1202-T016X0064
00012033 01CF00FF 00001FF7 00008000
00000C00 00001000 00011000 201ED083H
AB
XMC1202-Q024X0016
00012063 01CF00FF 00001FF7 00008000
00000C00 00001000 00005000 201ED083H
AB
XMC1202-Q024X0032
00012063 01CF00FF 00001FF7 00008000
00000C00 00001000 00009000 201ED083H
AB
XMC1201-Q040F0016
00012042 01CF00FF 00001FF7 00006000
00000C00 00001000 00005000 201ED083H
AB
XMC1201-Q040F0032
00012042 01CF00FF 00001FF7 00006000
00000C00 00001000 00009000 201ED083H
AB
XMC1201-Q040F0064
00012042 01CF00FF 00001FF7 00006000
00000C00 00001000 00011000 201ED083H
AB
XMC1201-Q040F0128
00012042 01CF00FF 00001FF7 00006000
00000C00 00001000 00021000 201ED083H
AB
XMC1201-Q040F0200
00012042 01CF00FF 00001FF7 00006000
00000C00 00001000 00033000 201ED083H
AB
XMC1202-Q040X0016
00012043 01CF00FF 00001FF7 00008000
00000C00 00001000 00005000 201ED083H
AB
XMC1202-Q040X0032
00012043 01CF00FF 00001FF7 00008000
00000C00 00001000 00009000 201ED083H
AB
Data Sheet
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XMC1200 AB-Step
XMC1000 Family
General Device Information
2
General Device Information
This section summarizes the logic symbols and package pin configurations with a
detailed list of the functional I/O mapping.
2.1
Logic Symbols
V DDP
VSSP
VDDP
VSSP
(2)
(2)
(1)
(1)
XMC1200
TSSOP -38
Port 0
16 bit
Port 0
12 bit
Port 1
6 bit
Port 1
4 bit
XMC1200
Port 2
4 bit
TSSOP -28
Port 2
8 bit
Port 2
4 bit
Port 2
6 bit
VDDP
V SSP
(1)
(1)
Port 0
8 bit
XMC1200
Port 2
3 bit
TSSOP-16
Port 2
3 bit
Figure 2
Data Sheet
XMC1200 Logic Symbol for TSSOP-38, TSSOP-28 and TSSOP-16
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XMC1200 AB-Step
XMC1000 Family
General Device Information
V DD VSS VDDP VSSP
(1)
(1)
(2)
(1)
V DDP
VSSP
(1)
(1)
Port 0
10 bit
Port 0
16 bit
XMC1200
VQFN-40
Port 1
7 bit
XMC1200
VQFN-24
Port 2
4 bit
Data Sheet
Port 2
4 bit
Port 2
4 bit
Port 2
8 bit
Figure 3
Port 1
4 bit
XMC1200 Logic Symbol for VQFN-24 and VQFN-40
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XMC1200 AB-Step
XMC1000 Family
General Device Information
2.2
Pin Configuration and Definition
The following figures summarize all pins, showing their locations on the different
packages.
P2.4
1
38
P2.3
Top View
Figure 4
Data Sheet
P2.5
2
37
P2.2
P2.6
3
36
P2.1
P2.7
4
35
P2.0
P2.8
5
34
P0.15
P2.9
6
33
P0.14
P2.10
7
32
P0.13
P2.11
8
31
P0.12
VSSP /VSS
9
30
P0.11
VDDP/VDD
10
29
P0.10
P1.5
11
28
P0.9
P1.4
12
27
P0.8
P1.3
13
26
VDDP
P1.2
14
25
VSSP
P1.1
15
24
P0.7
P1.0
16
23
P0.6
P0.0
17
22
P0.5
P0.1
18
21
P0.4
P0.2
19
20
P0.3
XMC1200 PG-TSSOP-38 Pin Configuration (top view)
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XMC1200 AB-Step
XMC1000 Family
General Device Information
P2.6
1
28
P2.5
Top View
Figure 5
P2.7
2
27
P2.2
P2.8
3
26
P2.1
P2.9
4
25
P2.0
P2.10
5
24
P0.15
P2.11
6
23
P0.14
VSSP /VSS
7
22
P0.13
VDDP/VDD
8
21
P0.12
P1.3
9
20
P0.10
P1.2
10
19
P0.9
P1.1
11
18
P0.8
P1.0
12
17
P0.7
P0.0
13
16
P0.6
P0.4
14
15
P0.5
XMC1200 PG-TSSOP-28 Pin Configuration (top view)
P2.7/P2.8
1
16
P2.6
Top View
Figure 6
Data Sheet
P2.9
2
15
P2.0
P2.10
3
14
P0.15
P2.11
4
13
P0.14
VSSP/VSS
5
12
P0.9
VDDP/VDD
6
11
P0.8
P0.0
7
10
P0.7
P0.5
8
9
P0.6
XMC1200 PG-TSSOP-16 Pin Configuration (top view)
17
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1200 AB-Step
XMC1000 Family
P1.1
P1.0
P0.0
P0.5
P0.6
P0.7
General Device Information
18 17 16 15 14 13
12
P1.2
P0.9
20
11
P1.3
P0.12
21
10
VDDP /V DD
P0.13
22
9
VSSP /V SS
P0.14
23
8
P2.11
P0.15
24
7
P2.10
P2.2
4 5
6
P2.9
3
P2.7/P2.8
2
P2.6
1
P2.1
Data Sheet
19
P2.0
Figure 7
P0.8
XMC1200 PG-VQFN-24 Pin Configuration (top view)
18
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1200 AB-Step
XMC1000 Family
P1.1
P1.0
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
General Device Information
30 29 28 27 26 25 24 23 22 21
V SSP
31
20
P1.2
VDDP
32
19
P1.3
P0.8
33
18
P1.4
P0.9
34
17
P1.5
P0.10
35
16
P1.6
P0.11
36
15
VDDP
P0.12
37
14
V DD
P0.13
38
13
V SS
P0.14
39
12
P2.11
P0.15
40
11
P2.10
7
8
9
10
P2.6
P2.7
P2.8
P2.9
6
P2.5
P2.4
P2.2
4 5
P2.3
3
P2.1
Data Sheet
2
P2.0
Figure 8
1
XMC1200 PG-VQFN-40 Pin Configuration (top view)
19
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1200 AB-Step
XMC1000 Family
General Device Information
2.2.1
Package Pin Summary
The following general building block is used to describe each pin:
Table 5
Package Pin Mapping Description
Function
Package A
Package B
Px.y
N
N
...
Pad Type
Pad Class
The table is sorted by the “Function” column, starting with the regular Port pins (Px.y),
followed by the supply pins.
The following columns, titled with the supported package variants, lists the package pin
number to which the respective function is mapped in that package.
The “Pad Type” indicates the employed pad type:
•
•
•
•
•
STD_INOUT (standard bi-directional pads)
STD_INOUT/AN (standard bi-directional pads with analog input)
High Current (high current bi-directional pads)
STD_IN/AN (standard input pads with analog input)
Power (power supply)
Details about the pad properties are defined in the Electrical Parameters.
Table 6
Package Pin Mapping
Function VQFN
40
TSSOP TSSOP VQFN
38
28
24
TSSOP Pad Type Notes
16
P0.0
23
17
13
15
7
STD_INO
UT
P0.1
24
18
-
-
-
STD_INO
UT
P0.2
25
19
-
-
-
STD_INO
UT
P0.3
26
20
-
-
-
STD_INO
UT
P0.4
27
21
14
-
-
STD_INO
UT
P0.5
28
22
15
16
8
STD_INO
UT
P0.6
29
23
16
17
9
STD_INO
UT
Data Sheet
20
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1200 AB-Step
XMC1000 Family
General Device Information
Table 6
Package Pin Mapping (cont’d)
Function VQFN
40
TSSOP TSSOP VQFN
38
28
24
TSSOP Pad Type Notes
16
P0.7
30
24
17
18
10
STD_INO
UT
P0.8
33
27
18
19
11
STD_INO
UT
P0.9
34
28
19
20
12
STD_INO
UT
P0.10
35
29
20
-
-
STD_INO
UT
P0.11
36
30
-
-
-
STD_INO
UT
P0.12
37
31
21
21
-
STD_INO
UT
P0.13
38
32
22
22
-
STD_INO
UT
P0.14
39
33
23
23
13
STD_INO
UT
P0.15
40
34
24
24
14
STD_INO
UT
P1.0
22
16
12
14
-
High
Current
P1.1
21
15
11
13
-
High
Current
P1.2
20
14
10
12
-
High
Current
P1.3
19
13
9
11
-
High
Current
P1.4
18
12
-
-
-
High
Current
P1.5
17
11
-
-
-
High
Current
P1.6
16
-
-
-
-
STD_INO
UT
P2.0
1
35
25
1
15
STD_INO
UT/AN
Data Sheet
21
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1200 AB-Step
XMC1000 Family
General Device Information
Table 6
Package Pin Mapping (cont’d)
Function VQFN
40
TSSOP TSSOP VQFN
38
28
24
TSSOP Pad Type Notes
16
P2.1
2
36
26
2
-
STD_INO
UT/AN
P2.2
3
37
27
3
-
STD_IN/A
N
P2.3
4
38
-
-
-
STD_IN/A
N
P2.4
5
1
-
-
-
STD_IN/A
N
P2.5
6
2
28
-
-
STD_IN/A
N
P2.6
7
3
1
4
16
STD_IN/A
N
P2.7
8
4
2
5
1
STD_IN/A
N
P2.8
9
5
3
5
1
STD_IN/A
N
P2.9
10
6
4
6
2
STD_IN/A
N
P2.10
11
7
5
7
3
STD_INO
UT/AN
P2.11
12
8
6
8
4
STD_INO
UT/AN
VSS
13
9
7
9
5
Power
Supply GND,
ADC reference
GND
VDD
14
10
8
10
6
Power
Supply VDD,
ADC reference
voltage/ ORC
reference
voltage
VDDP
15
10
8
10
6
Power
When VDD is
supplied, VDDP
has to be
supplied with the
same voltage.
Data Sheet
22
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1200 AB-Step
XMC1000 Family
General Device Information
Table 6
Package Pin Mapping (cont’d)
Function VQFN
40
TSSOP TSSOP VQFN
38
28
24
TSSOP Pad Type Notes
16
VSSP
31
25
-
-
-
Power
I/O port ground
VDDP
32
26
-
-
-
Power
I/O port supply
VSSP
Exp.
Pad
-
-
Exp.
Pad
-
Power
Exposed Die
Pad
The exposed die
pad is
connected
internally to
VSSP. For
proper
operation, it is
mandatory to
connect the
exposed pad to
the board
ground. For
thermal aspects,
please refer to
the Package
and Reliability
chapter.
Data Sheet
23
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1200 AB-Step
XMC1000 Family
General Device Information
2.2.2
Port I/O Functions
The following general building block is used to describe each PORT pin:
Table 7
Function
Port I/O Function Description
Outputs
Inputs
ALT1
ALTn
P0.0
Pn.y
Input
MODA.OUT
MODA.OUT
Input
MODC.INA
MODA.INA
MODC.INB
Pn.y
XMC1000
Control Logic
PAD
Input 0
MODA
MODB
MODB.OUT
Input n
HWI0
HWI1
SW
Pn.y
ALT1
...
ALTn
HWO0
HWO1
Figure 9
VDDP
...
MODA.INA
GND
Simplified Port Structure
Pn.y is the port pin name, defining the control and data bits/registers associated with it.
As GPIO, the port is under software control. Its input value is read via Pn_IN.y, Pn_OUT
defines the output value.
Up to seven alternate output functions (ALT1/2/3/4/5/6/7) can be mapped to a single port
pin, selected by Pn_IOCR.PC. The output value is directly driven by the respective
module, with the pin characteristics controlled by the port registers (within the limits of
the connected pad).
The port pin input can be connected to multiple peripherals. Most peripherals have an
input multiplexer to select between different possible input sources.
The input path is also active while the pin is configured as output. This allows to feedback
an output to on-chip resources without wasting an additional external pin.
Please refer to the Port I/O Functions table for the complete Port I/O function mapping.
Data Sheet
24
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1200 AB-Step
XMC1000 Family
General Device Information
2.2.3
Hardware Controlled I/O Function Description
The following general building block is used to describe the hardware I/O and pull control
functions of each PORT pin:
Table 8
Hardware Controlled I/O Function Description
Function
Outputs
Inputs
Pull Control
P0.0
HWO0
HWI0
HW0_PD
HW0_PU
MODB.OUT
MODB.INA
MODC.OUT
MODC.OUT
Pn.y
By Pn_HWSEL, it is possible to select between different hardware “masters”
(HWO0/HWI0, HWO1/HWI1). The selected peripheral can take control of the pin(s).
Hardware control overrules settings in the respective port pin registers. Additional
hardware signals HW0_PD/HW1_PD and HW0_PU/HW1_PU controlled by the
peripherals can be used to control the pull devices of the pin.
Please refer to the Hardware Controlled I/O Functions table for the complete hardware
I/O and pull control function mapping.
Data Sheet
25
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
Data Sheet
Table 9
Port I/O Functions
Function
Outputs
Inputs
26
ALT2
ALT3
ALT4
P0.0
ERU0.
PDOUT0
LEDTS0.
LINE7
ERU0.
GOUT0
CCU40.
OUT0
USIC0_CH USIC0_CH BCCU0.
0.SELO0
1.SELO0
TRAPINB
CCU40.IN0
C
P0.1
ERU0.
PDOUT1
LEDTS0.
LINE6
ERU0.
GOUT1
CCU40.
OUT1
BCCU0.
OUT8
CCU40.IN1
C
P0.2
ERU0.
PDOUT2
LEDTS0.
LINE5
ERU0.
GOUT2
CCU40.
OUT2
VADC0.
EMUX02
CCU40.IN2
C
P0.3
ERU0.
PDOUT3
LEDTS0.
LINE4
ERU0.
GOUT3
CCU40.
OUT3
VADC0.
EMUX01
CCU40.IN3
C
P0.4
BCCU0.
OUT0
LEDTS0.
LINE3
LEDTS0.
COL3
CCU40.
OUT1
VADC0.
EMUX00
P0.5
BCCU0.
OUT1
LEDTS0.
LINE2
LEDTS0.
COL2
CCU40.
OUT0
ACMP2.
OUT
P0.6
BCCU0.
OUT2
LEDTS0.
LINE1
LEDTS0.
COL1
CCU40.
OUT0
USIC0_CH USIC0_CH
1.MCLKOU 1.DOUT0
T
CCU40.IN0
B
USIC0_CH
1.DX0C
P0.7
BCCU0.
OUT3
LEDTS0.
LINE0
LEDTS0.
COL0
CCU40.
OUT1
USIC0_CH USIC0_CH
0.SCLKOU 1.DOUT0
T
CCU40.IN1
B
USIC0_CH USIC0_CH USIC0_CH
0.DX1C
1.DX0D
1.DX1C
P0.8
BCCU0.
OUT4
LEDTS1.
LINE0
LEDTS0.
COLA
CCU40.
OUT2
USIC0_CH USIC0_CH
0.SCLKOU 1.SCLKOU
T
T
CCU40.IN2
B
USIC0_CH USIC0_CH
0.DX1B
1.DX1B
P0.9
BCCU0.
OUT5
LEDTS1.
LINE1
LEDTS0.
COL6
CCU40.
OUT3
USIC0_CH USIC0_CH
0.SELO0
1.SELO0
CCU40.IN3
B
USIC0_CH USIC0_CH
0.DX2B
1.DX2B
P0.10
BCCU0.
OUT6
LEDTS1.
LINE2
LEDTS0.
COL5
ACMP0.
OUT
USIC0_CH USIC0_CH
0.SELO1
1.SELO1
USIC0_CH USIC0_CH
0.DX2C
1.DX2C
P0.11
BCCU0.
OUT7
LEDTS1.
LINE3
LEDTS0.
COL4
USIC0_CH
0.MCLKOU
T
USIC0_CH USIC0_CH
0.SELO2
1.SELO2
USIC0_CH USIC0_CH
0.DX2D
1.DX2D
P0.12
BCCU0.
OUT6
LEDTS1.
LINE4
LEDTS0.
COL3
LEDTS1.
COL3
USIC0_CH
0.SELO3
P0.13
WWDT.
LEDTS1.
SERVICE_ LINE5
OUT
LEDTS0.
COL2
LEDTS1.
COL2
USIC0_CH
0.SELO4
USIC0_CH
0.DX2F
P0.14
BCCU0.
OUT7
LEDTS0.
COL1
LEDTS1.
COL1
USIC0_CH USIC0_CH
0.DOUT0
0.SCLKOU
T
USIC0_CH USIC0_CH
0.DX0A
0.DX1A
LEDTS1.
LINE6
ALT5
ALT6
ALT7
Input
SCU.
VDROP
Input
Input
Input
Input
Input
Input
Input
USIC0_CH USIC0_CH
0.DX2A
1.DX2A
WWDT.
SERVICE_
OUT
BCCU0.
TRAPINA
CCU40.IN0 CCU40.IN1 CCU40.IN2 CCU40.IN3 USIC0_CH
A
A
A
A
0.DX2E
XMC1200 AB-Step
XMC1000 Family
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
ALT1
Data Sheet
Table 9
Port I/O Functions
Function
Outputs
Inputs
27
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
Input
Input
Input
Input
P0.15
BCCU0.
OUT8
LEDTS1.
LINE7
LEDTS0.
COL0
LEDTS1.
COL0
USIC0_CH USIC0_CH
0.DOUT0
1.MCLKOU
T
USIC0_CH
0.DX0B
P1.0
BCCU0.
OUT0
CCU40.
OUT0
LEDTS0.
COL0
LEDTS1.
COLA
ACMP1.
OUT
USIC0_CH
0.DX0C
P1.1
VADC0.
EMUX00
CCU40.
OUT1
LEDTS0.
COL1
LEDTS1.
COL0
USIC0_CH USIC0_CH
0.DOUT0
1.SELO0
USIC0_CH USIC0_CH USIC0_CH
0.DX0D
0.DX1D
1.DX2E
P1.2
VADC0.
EMUX01
CCU40.
OUT2
LEDTS0.
COL2
LEDTS1.
COL1
ACMP2.
OUT
USIC0_CH
1.DX0B
P1.3
VADC0.
EMUX02
CCU40.
OUT3
LEDTS0.
COL3
LEDTS1.
COL2
USIC0_CH USIC0_CH
1.SCLKOU 1.DOUT0
T
USIC0_CH USIC0_CH
1.DX0A
1.DX1A
P1.4
VADC0.
EMUX10
USIC0_CH LEDTS0.
1.SCLKOU COL4
T
LEDTS1.
COL3
USIC0_CH USIC0_CH
0.SELO0
1.SELO1
USIC0_CH USIC0_CH
0.DX5E
1.DX5E
P1.5
VADC0.
EMUX11
USIC0_CH LEDTS0.
0.DOUT0
COLA
BCCU0.
OUT1
USIC0_CH USIC0_CH
0.SELO1
1.SELO2
USIC0_CH
1.DX5F
P1.6
VADC0.
EMUX12
USIC0_CH LEDTS0.
1.DOUT0
COL5
USIC0_CH BCCU0.
0.SCLKOU OUT2
T
USIC0_CH USIC0_CH
0.SELO2
1.SELO3
P2.0
ERU0.
PDOUT3
CCU40.
OUT0
ERU0.
GOUT3
LEDTS1.
COL5
USIC0_CH USIC0_CH
0.DOUT0
0.SCLKOU
T
VADC0.
G0CH5
ERU0.0B0
USIC0_CH USIC0_CH USIC0_CH
0.DX0E
0.DX1E
1.DX2F
P2.1
ERU0.
PDOUT2
CCU40.
OUT1
ERU0.
GOUT2
LEDTS1.
COL6
USIC0_CH USIC0_CH ACMP2.INP VADC0.
0.DOUT0
1.SCLKOU
G0CH6
T
ERU0.1B0
USIC0_CH USIC0_CH USIC0_CH
0.DX0F
1.DX3A
1.DX4A
P2.2
ACMP2.INN VADC0.
G0CH7
ERU0.0B1
USIC0_CH USIC0_CH USIC0_CH ORC0.AIN
0.DX3A
0.DX4A
1.DX5A
P2.3
VADC0.
G1CH5
ERU0.1B1
USIC0_CH USIC0_CH USIC0_CH ORC1.AIN
0.DX5B
1.DX3C
1.DX4C
P2.4
VADC0.
G1CH6
ERU0.0A1
USIC0_CH USIC0_CH USIC0_CH ORC2.AIN
0.DX3B
0.DX4B
1.DX5B
P2.5
VADC0.
G1CH7
ERU0.1A1
USIC0_CH USIC0_CH USIC0_CH ORC3.AIN
0.DX5D
1.DX3E
1.DX4E
P2.6
ACMP1.INN VADC0.
G0CH0
ERU0.2A1
USIC0_CH USIC0_CH USIC0_CH ORC4.AIN
0.DX3E
0.DX4E
1.DX5D
P2.7
ACMP1.INP VADC0.
G1CH1
ERU0.3A1
USIC0_CH USIC0_CH USIC0_CH ORC5.AIN
0.DX5C
1.DX3D
1.DX4D
USIC0_CH
0.DOUT0
USIC0_CH
1.DOUT0
Input
Input
Input
Input
USIC0_CH
0.DX5F
XMC1200 AB-Step
XMC1000 Family
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
ALT1
Data Sheet
Table 9
Port I/O Functions
Function
Outputs
ALT1
ALT2
ALT3
ALT4
Inputs
ALT5
ALT6
ALT7
Input
Input
Input
Input
P2.8
ACMP0.INN VADC0.
G0CH1
VADC0.
G1CH0
ERU0.3B1
USIC0_CH USIC0_CH USIC0_CH ORC6.AIN
0.DX3D
0.DX4D
1.DX5C
P2.9
ACMP0.INP VADC0.
G0CH2
VADC0.
G1CH4
ERU0.3B0
USIC0_CH USIC0_CH USIC0_CH ORC7.AIN
0.DX5A
1.DX3B
1.DX4B
USIC0_CH
1.DOUT0
Input
Input
Input
P2.10
ERU0.
PDOUT1
CCU40.
OUT2
ERU0.
GOUT1
LEDTS1.
COL4
ACMP0.
OUT
VADC0.
G0CH3
VADC0.
G1CH2
ERU0.2B0
USIC0_CH USIC0_CH USIC0_CH
0.DX3C
0.DX4C
1.DX0F
P2.11
ERU0.
PDOUT0
CCU40.
OUT3
ERU0.
GOUT0
LEDTS1.
COL3
USIC0_CH USIC0_CH ACMP.REF VADC0.
1.SCLKOU 1.DOUT0
G0CH4
T
VADC0.
G1CH3
ERU0.2B1
USIC0_CH USIC0_CH
1.DX0E
1.DX1E
Input
28
XMC1200 AB-Step
XMC1000 Family
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
Data Sheet
Table 10
Hardware Controlled I/O Functions
Function
Outputs
HWO0
HWO1
Inputs
Pull Control
HWI0
HWI1
HW0_PD
HW0_PU
HW1_PD
Reserved for LEDTS
Scheme A:
pull-down disabled
always
Reserved for LEDTS
Scheme A:
pull-down enabled
always
Reserved for LEDTS Scheme B:
pull-up enabled and pull-down disabled, and
vice versa
LEDTS0.TSIN7
LEDTS0. TSIN7
P0.1
LEDTS0.
EXTENDED6
LEDTS0.TSIN6
LEDTS0. TSIN6
P0.2
LEDTS0.
EXTENDED5
LEDTS0.TSIN5
LEDTS0. TSIN5
P0.3
LEDTS0.
EXTENDED4
LEDTS0.TSIN4
LEDTS0. TSIN4
P0.4
LEDTS0.
EXTENDED3
LEDTS0. TSIN3
LEDTS0. TSIN3
P0.5
LEDTS0.
EXTENDED2
LEDTS0. TSIN2
LEDTS0. TSIN2
P0.6
LEDTS0.
EXTENDED1
LEDTS0. TSIN1
LEDTS0. TSIN1
P0.7
LEDTS0.
EXTENDED0
LEDTS0. TSIN0
LEDTS0. TSIN0
P0.8
LEDTS1.
EXTENDED0
LEDTS1. TSIN0
LEDTS1. TSIN0
P0.9
LEDTS1.
EXTENDED1
LEDTS1. TSIN1
LEDTS1. TSIN1
P0.10
LEDTS1.
EXTENDED2
LEDTS1. TSIN2
LEDTS1. TSIN2
P0.11
LEDTS1.
EXTENDED3
LEDTS1. TSIN3
LEDTS1. TSIN3
P0.12
LEDTS1.
EXTENDED4
LEDTS1. TSIN4
LEDTS1. TSIN4
P0.13
LEDTS1.
EXTENDED5
LEDTS1. TSIN5
LEDTS1. TSIN5
P0.14
LEDTS1.
EXTENDED6
LEDTS1. TSIN6
LEDTS1. TSIN6
P0.15
LEDTS1.
EXTENDED7
LEDTS1. TSIN7
LEDTS1. TSIN7
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
P1.0
USIC0_CH0.DOUT0
USIC0_CH0.HWIN0
BCCU0.OUT2
BCCU0.OUT2
P1.1
USIC0_CH0.DOUT1
USIC0_CH0.HWIN1
BCCU0.OUT3
BCCU0.OUT3
P1.2
USIC0_CH0.DOUT2
USIC0_CH0.HWIN2
BCCU0.OUT4
BCCU0.OUT4
HW1_PU
XMC1200 AB-Step
XMC1000 Family
LEDTS0.
EXTENDED7
29
P0.0
Data Sheet
Table 10
Hardware Controlled I/O Functions
Function
Outputs
HWO0
Inputs
30
HW0_PD
HW0_PU
USIC0_CH0.HWIN3
BCCU0.OUT5
BCCU0.OUT5
HW1_PU
P1.4
BCCU0.OUT6
BCCU0.OUT6
P1.5
BCCU0.OUT7
BCCU0.OUT7
P1.6
BCCU0.OUT8
BCCU0.OUT8
P2.0
BCCU0.OUT1
BCCU0.OUT1
P2.1
BCCU0.OUT6
BCCU0.OUT6
P2.2
BCCU0.OUT0
BCCU0.OUT0
P2.3
ACMP2.OUT
ACMP2.OUT
CCU40.OUT3
CCU40.OUT3
P2.4
BCCU0.OUT8
BCCU0.OUT8
P2.5
ACMP1.OUT
ACMP1.OUT
P2.6
BCCU0.OUT2
P2.7
BCCU0.OUT8
BCCU0.OUT2
CCU40.OUT3
CCU40.OUT3
BCCU0.OUT8
CCU40.OUT3
P2.8
CCU40.OUT3
BCCU0.OUT1
BCCU0.OUT1
CCU40.OUT2
CCU40.OUT2
P2.9
BCCU0.OUT7
BCCU0.OUT7
CCU40.OUT2
CCU40.OUT2
P2.10
BCCU0.OUT4
BCCU0.OUT4
P2.11
BCCU0.OUT5
BCCU0.OUT5
XMC1200 AB-Step
XMC1000 Family
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
HW1_PD
USIC0_CH0.DOUT3
HWI0
Pull Control
HWI1
P1.3
HWO1
XMC1200 AB-Step
XMC1000 Family
Electrical Parameter
3
Electrical Parameter
This section provides the electrical parameter which are implementation-specific for the
XMC1200.
3.1
General Parameters
3.1.1
Parameter Interpretation
The parameters listed in this section represent partly the characteristics of the XMC1200
and partly its requirements on the system. To aid interpreting the parameters easily
when evaluating them for a design, they are indicated by the abbreviations in the
“Symbol” column:
•
•
CC
Such parameters indicate Controller Characteristics, which are distinctive feature of
the XMC1200 and must be regarded for a system design.
SR
Such parameters indicate System Requirements, which must be provided by the
application system in which the XMC1200 is designed in.
Data Sheet
31
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1200 AB-Step
XMC1000 Family
Electrical Parameter
3.1.2
Absolute Maximum Ratings
Stresses above the values listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions may affect device reliability.
Table 11
Absolute Maximum Rating Parameters
Parameter
Symbol
Values
Min Typ. Max.
.
Unit Note /
Test Cond
ition
115
°C
–
125
°C
–
6
V
–
TJ
SR -40 –
TST
SR -40 –
VDDP SR -0.3 –
Voltage on digital pins with
respect to VSSP1)
VIN
VDDP + 0.5 V
Voltage on P2 pins with
respect to VSSP2)
Voltage on analog input pins
with respect to VSSP
Junction temperature
Storage temperature
Voltage on power supply pin
with respect to VSSP
Input current on any pin
during overload condition
or max. 6
whichever
is lower
VINP2 SR -0.3 –
VDDP + 0.3 V
–
VAIN
-0.5 –
VAREF SR
IIN
SR -10 –
VDDP + 0.5 V
whichever
is lower
Absolute maximum sum of all ΣIIN
input currents during overload
condition
SR -0.5 –
SR -50
–
or max. 6
10
mA
–
+50
mA
–
1) Excluding port pins P2.[1,2,6,7,8,9,11].
2) Applicable to port pins P2.[1,2,6,7,8,9,11].
Data Sheet
32
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1200 AB-Step
XMC1000 Family
Electrical Parameter
3.1.3
Pin Reliability in Overload
When receiving signals from higher voltage devices, low-voltage devices experience
overload currents and voltages that go beyond their own IO power supplies specification.
Table 12 defines overload conditions that will not cause any negative reliability impact if
all the following conditions are met:
•
•
full operation life-time is not exceeded
Operating Conditions are met for
– pad supply levels (VDDP)
– temperature
If a pin current is outside of the Operating Conditions but within the overload
conditions, then the parameters of this pin as stated in the Operating Conditions can no
longer be guaranteed. Operation is still possible in most cases but with relaxed
parameters.
Note: An overload condition on one or more pins does not require a reset.
Note: A series resistor at the pin to limit the current to the maximum permitted overload
current is sufficient to handle failure situations like short to battery.
Table 12
Overload Parameters
Parameter
Symbol
Values
Min.
Input current on any port pin
during overload condition
IOV
Absolute sum of all input
circuit currents during
overload condition
IOVS SR –
SR -5
Typ.
Unit Note /
Test Condition
Max.
–
5
mA
–
25
mA
Figure 10 shows the path of the input currents during overload via the ESD protection
structures. The diodes against VDDP and ground are a simplified representation of these
ESD protection structures.
Data Sheet
33
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1200 AB-Step
XMC1000 Family
Electrical Parameter
VDDP VDDP
Pn.y
IOVx
GND
ESD
Figure 10
GND
Pad
Input Overload Current via ESD structures
Table 13 and Table 14 list input voltages that can be reached under overload conditions.
Note that the absolute maximum input voltages as defined in the Absolute Maximum
Ratings must not be exceeded during overload.
Table 13
PN-Junction Characterisitics for positive Overload
Pad Type
Standard, High-current,
AN/DIG_IN
P2.[1,2,6:9,11]
Table 14
PN-Junction Characterisitics for negative Overload
Pad Type
Standard, High-current,
AN/DIG_IN
P2.[1,2,6:9,11]
Data Sheet
IOV = 5 mA
VIN = VDDP + 0.5 V
VAIN = VDDP + 0.5 V
VAREF = VDDP + 0.5 V
VINP2 = VDDP + 0.3 V
IOV = 5 mA
VIN = VSS - 0.5 V
VAIN = VSS - 0.5 V
VAREF = VSS - 0.5 V
VINP2 = VSS - 0.3 V
34
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1200 AB-Step
XMC1000 Family
Electrical Parameter
3.1.4
Operating Conditions
The following operating conditions must not be exceeded in order to ensure correct
operation and reliability of the XMC1200. All parameters specified in the following tables
refer to these operating conditions, unless noted otherwise.
Table 15
Operating Conditions Parameters
Parameter
Symbol
Values
Min.
Unit
Note /
Test Condition
85
°C
Temp. Range F
Temp. Range X
Typ.
Max.
SR -40
−
Ambient Temperature
TA
-40
−
105
°C
Digital supply voltage1)
VDDP SR 1.8
fMCLK CC −
fPCLK CC −
−
5.5
V
−
33.2
MHz CPU clock
−
66.4
MHz Peripherals
clock
Short circuit current of
digital outputs
ISC
−
5
mA
Absolute sum of short
circuit currents of the
device
ΣISC_D SR −
−
25
mA
MCLK Frequency
PCLK Frequency
SR
-5
1) See also the Supply Monitoring thresholds, Chapter 3.3.2.
Data Sheet
35
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1200 AB-Step
XMC1000 Family
Electrical Parameter
3.2
DC Parameters
3.2.1
Input/Output Characteristics
Table 16 provides the characteristics of the input/output pins of the XMC1200.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Note: Unless otherwise stated, input DC and AC characteristics, including peripheral
timings, assume that the input pads operate with the standard hysteresis.
Table 16
Input/Output Characteristics (Operating Conditions apply)
Parameter
Symbol
Limit Values
Min.
Output low voltage on
port pins
(with standard pads)
VOLP
Output low voltage on
high current pads
VOLP1
Output high voltage on
port pins
(with standard pads)
VOHP
Unit
Test Conditions
V
IOL = 11 mA (5 V)
IOL = 7 mA (3.3 V)
IOL = 5 mA (5 V)
IOL = 3.5 mA (3.3 V)
IOL = 50 mA (5 V)
IOL = 25 mA (3.3 V)
IOL = 10 mA (5 V)
IOL = 5 mA (3.3 V)
IOH = -10 mA (5 V)
IOH = -7 mA (3.3 V)
IOH = -4.5 mA (5 V)
IOH = -2.5 mA (3.3 V)
IOH = -6 mA (5 V)
V
IOH = -8 mA (3.3 V)
V
IOH = -4 mA (3.3 V)
0.19 × V
CMOS Mode
(5 V, 3.3 V & 2.2 V)
Max.
CC –
1.0
V
–
0.4
V
CC –
1.0
V
–
0.32
V
–
0.4
V
–
V
VDDP - –
V
CC VDDP 1.0
0.4
Output high voltage on
high current pads
VOHP1 CC VDDP - –
0.32
VDDP - –
1.0
VDDP - –
0.4
Input low voltage on port VILPS
pins
(Standard Hysteresis)
SR
VIHPS
SR
Input high voltage on
port pins
(Standard Hysteresis)
Data Sheet
–
VDDP
0.7 ×
VDDP
36
–
V
CMOS Mode
(5 V, 3.3 V & 2.2 V)
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1200 AB-Step
XMC1000 Family
Electrical Parameter
Table 16
Input/Output Characteristics (Operating Conditions apply) (cont’d)
Parameter
Symbol
Limit Values
Min.
Input low voltage on port VILPL
pins
(Large Hysteresis)
SR
Input high voltage on
port pins
(Large Hysteresis)
VIHPL
SR
Rise time on High
Current Pad1)
tHCPR
Fall time on High
Current Pad1)
Rise time on Standard
Pad1)
Fall time on Standard
Pad1)
Input Hysteresis8)
Unit
0.08 × V
–
VDDP
0.85 × –
tR
tF
HYS
CMOS Mode
(5 V, 3.3 V & 2.2 V)10)
9
ns
50 pF @ 5 V2)
–
12
ns
50 pF @ 3.3 V3)
–
25
ns
50 pF @ 1.8 V4)
9
ns
50 pF @ 5 V2)
–
12
ns
50 pF @ 3.3 V3)
–
25
ns
50 pF @ 1.8 V4)
CC –
12
ns
50 pF @ 5 V5)
–
15
ns
50 pF @ 3.3 V6)
–
31
ns
50 pF @ 1.8 V7)
CC –
12
ns
50 pF @ 5 V5)
–
15
ns
50 pF @ 3.3 V6)
–
31
ns
50 pF @ 1.8 V7)
V
CMOS Mode (5 V),
Standard Hysteresis
V
CMOS Mode (3.3 V),
Standard Hysteresis
V
CMOS Mode (2.2 V),
Standard Hysteresis
CC –
CC –
CC 0.08 × –
VDDP
0.03 × –
VDDP
0.02 × –
VDDP
Data Sheet
CMOS Mode
(5 V, 3.3 V & 2.2 V)10)
V
VDDP
tHCPF
Test Conditions
Max.
0.5 ×
0.75 × V
VDDP
VDDP
0.4 ×
0.75 × V
VDDP
VDDP
0.2 ×
0.65 × V
VDDP
VDDP
37
CMOS Mode(5 V),
Large Hysteresis
CMOS Mode(3.3 V),
Large Hysteresis
CMOS Mode(2.2 V),
Large Hysteresis
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1200 AB-Step
XMC1000 Family
Electrical Parameter
Table 16
Input/Output Characteristics (Operating Conditions apply) (cont’d)
Parameter
Symbol
Limit Values
Min.
Unit
Test Conditions
Max.
Pin capacitance (digital
inputs/outputs)
CIO
CC –
10
pF
Pull-up resistor on port
pins
RPUP
CC 20
50
kohm VIN = VSSP
Pull-down resistor on
port pins
RPDP
CC 20
50
kohm VIN = VDDP
Input leakage current9)
IOZP
CC -1
1
μA
0 < VIN < VDDP,
TA ≤ 105 °C
Voltage on any pin
during VDDP power off
VPO
SR
–
0.3
V
10)
Maximum current per
pin (excluding P1, VDDP
and VSS)
IMP
SR
-10
11
mA
–
Maximum current per
high currrent pins
IMP1A
SR
-10
50
mA
–
Maximum current into
VDDP (TSSOP28/16,
VQFN24)
IMVDD1 SR –
130
mA
10)
Maximum current into
VDDP (TSSOP38,
VQFN40)
IMVDD2 SR –
260
mA
10)
Maximum current out of IMVSS1 SR
VSS (TSSOP28/16,
VQFN24)
–
130
mA
10)
Maximum current out of IMVSS2 SR
VSS (TSSOP38,
VQFN40)
–
260
mA
10)
1) Rise/Fall time parameters are taken with 10% - 90% of supply.
2) Additional rise/fall time valid for CL = 50 pF - CL = 100 pF @ 0.150 ns/pF at 5 V supply voltage.
3) Additional rise/fall time valid for CL = 50 pF - CL = 100 pF @ 0.205 ns/pF at 3.3 V supply voltage.
4) Additional rise/fall time valid for CL = 50 pF - CL = 100 pF @ 0.445 ns/pF at 1.8 V supply voltage.
5) Additional rise/fall time valid for CL = 50 pF - CL = 100 pF @ 0.225 ns/pF at 5 V supply voltage.
6) Additional rise/fall time valid for CL = 50 pF - CL = 100 pF @ 0.288 ns/pF at 3.3 V supply voltage.
7) Additional rise/fall time valid for CL = 50 pF - CL = 100 pF @ 0.588 ns/pF at 1.8 V supply voltage.
Data Sheet
38
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1200 AB-Step
XMC1000 Family
Electrical Parameter
8) Hysteresis is implemented to avoid meta stable states and switching due to internal ground bounce. It cannot
be guaranteed that it suppresses switching due to external system noise.
9) An additional error current (IINJ) will flow if an overload current flows through an adjacent pin.
10) However, for applications with strict low power-down current requirements, it is mandatory that no active
voltage source is supplied at any GPIO pin when VDDP is powered off.
Data Sheet
39
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1200 AB-Step
XMC1000 Family
Electrical Parameter
3.2.2
Analog to Digital Converters (ADC)
Table 17 shows the Analog to Digital Converter (ADC) characteristics.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 17
ADC Characteristics (Operating Conditions apply)1)
Parameter
Symbol
Values
Min.
Supply voltage range
(internal reference)
Unit Note / Test Condition
Typ. Max.
VDD_int SR 2.0
–
3.0
V
SHSCFG.AREF = 11B
CALCTR.CALGNSTC
= 0CH
3.0
–
5.5
V
SHSCFG.AREF = 10B
3.0
–
5.5
V
SHSCFG.AREF = 00B
VSSP
–
VDDP V
Supply voltage range
(external reference)
VDD_ext
Analog input voltage
range
VAIN SR
Auxiliary analog
reference ground
VREFGND
VSSP
SR
- 0.05
SR
- 0.05
VSSP
+
0.05
–
1.0
V
G0CH0
–
0.2
V
G1CH0
- 0.05
Internal reference
voltage (full scale
value)
VREFINT
5
V
CC
Switched capacitance CAINS CC
of an analog input
–
1.2
2
pF
GNCTRxz.GAINy = 00B
(unity gain)
–
1.2
2
pF
GNCTRxz.GAINy = 01B
(gain g1)
–
4.5
6
pF
GNCTRxz.GAINy = 10B
(gain g2)
–
4.5
6
pF
GNCTRxz.GAINy = 11B
(gain g3)
Total capacitance of
an analog input
CAINT CC –
–
10
pF
Total capacitance of
the reference input
CAREFT
–
10
pF
Data Sheet
–
CC
40
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1200 AB-Step
XMC1000 Family
Electrical Parameter
Table 17
ADC Characteristics (Operating Conditions apply)1) (cont’d)
Parameter
Symbol
Values
Min.
Gain settings
Sample Time
GIN CC
tsample CC 3
Unit Note / Test Condition
Typ. Max.
1
–
GNCTRxz.GAINy = 00B
(unity gain)
3
–
GNCTRxz.GAINy = 01B
(gain g1)
6
–
GNCTRxz.GAINy = 10B
(gain g2)
12
–
GNCTRxz.GAINy = 11B
(gain g3)
1/
VDD = 5.0 V
–
–
fADC
3
–
–
1/
VDD = 3.3 V
fADC
30
–
–
1/
VDD = 2.0 V
fADC
Sigma delta loop hold
time
tSD_hold
Conversion time
in fast compare mode
tCF CC
Conversion time
in 12-bit mode
tC12 CC
20
–
–
μs
Residual charge stored
in an active sigma delta
loop remains available
1/
2)
CC
9
fADC
Maximum sample rate fC12 CC
in 12-bit mode 3)
20
–
–
1/
fADC
fADC / –
1 sample
–
–
42.5
pending
fADC / –
2 samples
pending
62.5
Conversion time
in 10-bit mode
tC10 CC
Maximum sample rate fC10 CC
in 10-bit mode 3)
18
–
–
1/
Data Sheet
tC8 CC
2)
fADC
fADC / –
1 sample
–
–
40.5
pending
fADC / –
2 samples
pending
58.5
Conversion time
in 8-bit mode
2)
16
1/
2)
fADC
41
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1200 AB-Step
XMC1000 Family
Electrical Parameter
Table 17
ADC Characteristics (Operating Conditions apply)1) (cont’d)
Parameter
Symbol
Maximum sample rate fC8 CC
in 8-bit mode 3)
Values
Unit Note / Test Condition
Min.
Typ. Max.
–
–
fADC / –
38.5
–
fADC / –
–
54.5
RMS noise 4)
ENRMS
–
1.5
–
CC
1 sample
pending
2 samples
pending
LSB DC input,
12
VDD = 5.0 V,
VAIN = 2.5 V,
25°C
DNL error
EADNL CC –
±2.0 –
LSB
12
INL error
EAINL CC –
±4.0 –
LSB
12
Gain error with
external reference
EAGAIN
–
±0.5 –
%
CC
SHSCFG.AREF = 00B
(calibrated)
–
±3.6 –
%
SHSCFG.AREF = 1XB
(calibrated),
-40°C - 105°C
–
±2.0 –
%
SHSCFG.AREF = 1XB
(calibrated),
0°C - 85°C
EAOFF CC –
±8.0 –
mV
Calibrated,
VDD = 5.0 V
Gain error with internal EAGAIN
reference 5)
CC
Offset error
1) The parameters are defined for ADC clock frequency fSH = 32MHz, SHSCFG.DIVS = 0000B. Usage of any
other frequencies may affect the ADC performance.
2) No pending samples assumed, excluding sampling time and calibration.
3) Includes synchronization and calibration (average of gain and offset calibration).
4) This parameter can also be defined as an SNR value: SNR[dB] = 20 × log(AMAXeff / NRMS).
With AMAXeff = 2N / 2, SNR[dB] = 20 × log ( 2048 / NRMS) [N = 12].
NRMS = 1.5 LSB12, therefore, equals SNR = 20 × log (2048 / 1.5) = 62.7 dB.
5) Includes error from the reference voltage.
Data Sheet
42
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1200 AB-Step
XMC1000 Family
Electrical Parameter
VAIN
SAR
Converter
:
0
VSS
1X
VCAL
00
1
VREFGND
VDD
VREF
VAGND
CH7
.
.
CH0
VREFINT
VAREF
Internal
Reference
VDDint/
VDD
VDDext
CHNR
REFSEL
AREF
MC_VADC_AREFPATHS
Figure 11
Data Sheet
ADC Voltage Supply
43
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1200 AB-Step
XMC1000 Family
Electrical Parameter
3.2.3
Out of Range Comparator (ORC) Characteristics
The Out-of-Range Comparator (ORC) triggers on analog input voltages (VAIN) above the
VDDP on selected input pins (ORCx.AIN) and generates a service request trigger
(ORCx.OUT).
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 18
Out of Range Comparator (ORC) Characteristics (Operating
Conditions apply; VDDP = 3.0 V - 5.5 V; CL = 0.25 pF)
Parameter
Symbol
Values
Min. Typ.
Hysteresis
Never detected
Overvoltage Pulse
Max.
−
183
mV
−
54
mV
−
−
ns
−
−
ns
tOPDN CC −
−
21
ns
−
−
11
ns
DC Switching Level VODC
C
Always detected
Overvoltage Pulse
Unit Note / Test Condition
C
54
VOHYS CC 15
tOPDD CC 103
88
VAIN ≥ VDDP + VODC
VAIN ≥ VDDP + 150 mV
VAIN ≥ VDDP + 350 mV
VAIN ≥ VDDP + 150 mV
VAIN ≥ VDDP + 350 mV
VAIN ≥ VDDP + 150 mV
VAIN ≥ VDDP + 350 mV
CC 39
−
132
ns
31
−
121
ns
Release Delay
tORD
CC 44
−
240
ns
57
−
340
ns
VAIN ≤ VDDP; VDDP = 5 V
VAIN ≤ VDDP; VDDP = 3.3 V
Enable Delay
tOED
CC −
−
300
ns
ORCCTRL.ENORCx = 1
VODC
VOH YS
Detection Delay of a tODD
persistent
Overvoltage
VD D P
VSS
ORCx.AIN
ORCx.OUT
tOD D
Figure 12
Data Sheet
tOR D
ORCx.OUT Trigger Generation
44
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1200 AB-Step
XMC1000 Family
Electrical Parameter
V AIN (V)
T < tOPDN
VDDP + 350 mV
T < tOPDN
VDDP + 150 mV
tOPDN < T < tOPDD
t OPDN < T < tOPDD
T > tOPDD
T > tOPDD
T > tOPDD
V DDP + 60 mV
VDDP
VSSA
Figure 13
Data Sheet
Never
detected
Overvoltage
Pulse
(Too low)
Overvoltage
may be
detected
(long enough,
level uncertain )
Never
detected
Overvoltage
Pulse
(Too short)
Overvoltage
may be
detected
Always detected
Overvoltage Pulse
Never
detected
Overvoltage
Pulse
(Too short)
Overvoltage
may be
detected
Always detected
Overvoltage Pulse
ORC Detection Ranges
45
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1200 AB-Step
XMC1000 Family
Electrical Parameter
3.2.4
Analog Comparator Characteristics
Table 19 below shows the Analog Comparator characteristics.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 19
Analog Comparator Characteristics (Operating Conditions apply)
Parameter
Symbol
Limit Values
Min.
Typ.
Max.
Unit Notes/
Test Conditions
Input Voltage
VCMP
SR -0.05 –
VDDP + V
0.05
Input Offset
VCMPOFF
CC –
–
mV
High power mode
Δ VCMP < 200 mV
+/-20 –
mV
Low power mode
Δ VCMP < 200 mV
CC –
25
–
ns
High power mode,
Δ VCMP = 100 mV
–
80
–
ns
High power mode,
Δ VCMP = 25 mV
–
250
–
ns
Low power mode,
Δ VCMP = 100 mV
–
700
–
ns
Low power mode,
Δ VCMP = 25 mV
CC –
100
–
μA
First active ACMP in
high power mode,
ΔVCMP > 30 mV
–
66
–
μA
Each additional
ACMP in high power
mode, ΔVCMP > 30 mV
–
10
–
μA
First active ACMP in
low power mode
–
6
–
μA
Each additional
ACMP in low power
mode
CC –
+/-15 –
mV
CC –
5
ns
–
Propagation
Delay1)
Current
Consumption
Input Hysteresis
Filter Delay
1)
tPDELAY
IACMP
VHYS
tFDELAY
+/-3
–
1) Total Analog Comparator Delay is the sum of Propagation Delay and Filter Delay.
Data Sheet
46
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1200 AB-Step
XMC1000 Family
Electrical Parameter
3.2.5
Temperature Sensor Characteristics
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 20
Temperature Sensor Characteristics
Parameter
Symbol
Values
Min.
Measurement time
Temperature sensor range
Sensor Accuracy1)
Typ. Max.
Unit Note /
Test Condition
tM CC
−
TSR SR
-40
TTSAL CC -6
−
10
ms
−
115
°C
–
6
°C
-10
–
10
°C
-18
–
18
°C
TJ > 20°C
0°C ≤ TJ ≤ 20°C
-25°C ≤ TJ <
0°C
-31
Start-up time after enabling
tTSSTE SR −
–
31
°C
−
15
μs
-40°C ≤ TJ < 25°C
1) The temperature sensor accuracy is independent of the supply voltage.
Data Sheet
47
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1200 AB-Step
XMC1000 Family
Electrical Parameter
3.2.6
Power Supply Current
The total power supply current defined below consists of a leakage and a switching
component.
Application relevant values are typically lower than those given in the following tables,
and depend on the customer's system operating conditions (e.g. thermal connection or
used application configurations).
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 21
Power Supply Parameters; VDDP = 5V
Parameter
Symbol
Values
Unit
Note /
Test Condition
Min Typ.1) Max.
.
Active mode current
Peripherals enabled
fMCLK / fPCLK in MHz2)
Active mode current
Peripherals disabled
fMCLK / fPCLK in MHz3)
Active mode current
Code execution from RAM
Flash is powered down
fMCLK / fPCLK in MHz
Sleep mode current
Peripherals clock enabled
fMCLK / fPCLK in MHz4)
Data Sheet
IDDPAE CC −
8.8
11.5
mA
32 / 64
−
7.7
−
mA
24 / 48
−
6.4
−
mA
16 / 32
−
5.3
−
mA
8 / 16
−
3.9
−
mA
1/1
IDDPAD CC −
4.8
−
mA
32 / 64
−
4.1
−
mA
24 / 48
−
3.3
−
mA
16 / 32
−
2.6
−
mA
8 / 16
−
1.5
−
mA
1/1
IDDPAR CC −
6.7
−
mA
32 / 64
−
5.8
−
mA
24 / 48
−
4.9
−
mA
16 / 32
−
4.0
−
mA
8 / 16
−
3.1
−
mA
1/1
IDDPSE CC −
6.2
−
mA
32 / 64
5.6
−
mA
24 / 48
5.0
−
mA
16 / 32
4.4
−
mA
8 / 16
3.7
−
mA
1/1
48
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1200 AB-Step
XMC1000 Family
Electrical Parameter
Table 21
Power Supply Parameters; VDDP = 5V
Parameter
Symbol
Values
Unit
Note /
Test Condition
Min Typ.1) Max.
.
Sleep mode current
Peripherals clock disabled
Flash active
fMCLK / fPCLK in MHz5)
Sleep mode current
Peripherals clock disabled
Flash powered down
fMCLK / fPCLK in MHz6)
IDDPSD CC −
IDDPSR CC −
Deep Sleep mode current7) IDDPDS CC −
1.8
−
mA
32 / 64
1.7
−
mA
24 / 48
1.6
−
mA
16 / 32
1.5
−
mA
8 / 16
1.4
−
mA
1/1
1.2
−
mA
32 / 64
1.1
−
mA
24 / 48
1.0
−
mA
16 / 32
0.8
−
mA
8 / 16
0.7
−
mA
1/1
0.24
−
mA
Wake-up time from Sleep to tSSA CC
Active mode8)
−
6
−
cycles
tDSA CC
−
280
−
μsec
Wake-up time from Deep
Sleep to Active mode9)
1) The typical values are measured at TA = + 25 °C and VDDP = 5 V.
2) CPU and all peripherals clock enabled, Flash is in active mode.
3) CPU enabled, all peripherals clock disabled, Flash is in active mode.
4) CPU in sleep, all peripherals clock enabled and Flash is in active mode.
5) CPU in sleep, Flash is in active mode.
6) CPU in sleep, Flash is powered down and code executed from RAM after wake-up.
7) CPU in sleep, peripherals clock disabled, Flash is powered down and code executed from RAM after wake-up.
8) CPU in sleep, Flash is in active mode during sleep mode.
9) CPU in sleep, Flash is in powered down mode during deep sleep mode.
Data Sheet
49
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1200 AB-Step
XMC1000 Family
Electrical Parameter
Figure 14 shows typical graphs for active mode supply current for VDDP = 5V, VDDP =
3.3V, VDDP = 1.8V across different clock frequencies.
10
8
ID DPA E 5V/3.3V
6
I (m A )
4
ID DPA E 1.8V
2
ID DPA D
5V/3.3V/1.8V
0
1/1
8/16 16/32 24/48 32/64
M CL K / PCL K (M Hz)
C ondition:
1. T A = + 25° C
Figure 14
Data Sheet
Active mode, a) peripherals clocks enabled, b) peripherals clocks
disabled: Supply current IDDPA over supply voltage VDDP for different
clock frequencies
50
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XMC1200 AB-Step
XMC1000 Family
Electrical Parameter
Figure 15 shows typical graphs for sleep mode current for VDDP = 5V, VDDP = 3.3V, VDDP
= 1.8V across different clock frequencies.
1 .4
1 .2
1
I (m A )
0 .8
0 .6
ID DP S R
5 V /3 .3 V /1 .8 V
0 .4
0 .2
0
1 /1
8 /1 6
1 6 /3 2
2 4 /4 8
3 2 /6 4
M CL K / P C L K (M H z )
C o n d itio n :
1. TA = +25° C
Figure 15
Data Sheet
Sleep mode, peripherals clocks disabled, Flash powered down:
Supply current IDDPSR over supply voltage VDDP for different clock
frequencies
51
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XMC1200 AB-Step
XMC1000 Family
Electrical Parameter
Table 22 provides the active current consumption of some modules operating at 5 V
power supply at 25° C. The typical values shown are used as a reference guide on the
current consumption when these modules are enabled.
Table 22
Typical Active Current Consumption
Active Current
Consumption
Symbol
Limit
Values
Unit
Test Condition
Typ.
Baseload current
ICPUDDC
5.04
mA
Modules including Core, SCU,
PORT, memories, ANATOP1)
VADC and SHS
IADCDDC
IUSIC0DDC
ICCU40DDC
ILTSxDDC
IBCCU0DDC
IWDTDDC
IRTCDDC
3.4
mA
Set CGATCLR0.VADC to 12)
0.87
mA
Set CGATCLR0.USIC0 to 13)
0.94
mA
Set CGATCLR0.CCU40 to 14)
0.76
mA
Set CGATCLR0.LEDTSx to 15)
0.24
mA
Set CGATCLR0.BCCU0 to 16)
0.03
mA
Set CGATCLR0.WDT to 17)
0.01
mA
Set CGATCLR0.RTC to 18)
USIC0
CCU40
LEDTSx
BCCU0
WDT
RTC
1) Baseload current is measured with device running in user mode, MCLK=PCLK=32 MHz, with an endless loop
in the flash memory. The clock to the modules stated in CGATSTAT0 are gated.
2) Active current is measured with: module enabled, MCLK=32 MHz, running in auto-scan conversion mode
3) Active current is measured with: module enabled, alternating messages sent to PC at 57.6kbaud every 200ms
4) Active current is measured with: module enabled, MCLK=PCLK=32 MHz, 1 CCU4 slice for PWM switching
from 1500Hz and 1000Hz at regular intervals, 1 CCU4 slice in capture mode for reading period and duty cycle
5) Active current is measured with: module enabled, MCLK=32 MHz, 1 LED column, 6 LED/TS lines, Pad
Scheme A with large pad hysteresis config, time slice duration = 1.048 ms
6) Active current is measured with: module enabled, MCLK=32 MHz, PCLK=64MHz, FCLK=0.8MHz, Normal
mode (BCCU Clk = FCLK/4), 3 BCCU Channels and 1 Dimming Engine, change color or dim every 1s
7) Active current is measured with: module enabled, MCLK=32 MHz, time-out mode; WLB = 0, WUB =
0x00008000; WDT serviced every 1s
8) Active current is measured with: module enabled, MCLK=32 MHz, Periodic interrupt enabled
Data Sheet
52
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1200 AB-Step
XMC1000 Family
Electrical Parameter
3.2.7
Flash Memory Parameters
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 23
Flash Memory Parameters
Parameter
Erase Time per
page / sector
Symbol
tERASE CC
Program time per block tPSER CC
Values
Unit
Min.
Typ. Max.
6.8
7.1
7.6
ms
102
152
204
μs
−
32.2 −
μs
−
50
−
ns
10
−
−
years
Note /
Test Condition
Data Retention Time
tWU CC
ta CC
tRET CC
Flash Wait States 1)
NWSFLASH CC 0
0
0
0
1
1
1
1.3
2
0
0
1
NVM_CONFIG1.
FIXWS = 1B,
fMCLK ≤ 16 MHz
1
1
1
NVM_CONFIG1.
FIXWS = 1B,
16 MHz < fMCLK
≤ 32 MHz
Wake-Up time
Read time per word
NFWSFLASH
Fixed Flash Wait
States configured in bit SR
NVM_NVMCONF.WS
Max. 100 erase /
program cycles
fMCLK = 8 MHz
fMCLK = 16 MHz
fMCLK = 32 MHz
Erase Cycles
NECYC CC
−
−
5*104 cycles Sum of page and
sector erase
cycles
Total Erase Cycles
NTECYC CC
−
−
2*106 cycles
1) Flash wait states are automatically inserted by the Flash module during memory read when needed. Typical
values are calculated from the execution of the Dhrystone benchmark program.
Data Sheet
53
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1200 AB-Step
XMC1000 Family
Electrical Parameter
3.3
AC Parameters
3.3.1
Testing Waveforms
VD D P
VSS
90%
90%
10%
10%
tR
Figure 16
tF
Rise/Fall Time Parameters
VD D P
VD D P / 2
Test Points
VD D P / 2
VSS
Figure 17
Testing Waveform, Output Delay
VL OAD + 0.1V
VL OAD - 0.1V
Figure 18
Data Sheet
Timing
Reference
Points
VOH - 0.1V
VOL + 0.1V
Testing Waveform, Output High Impedance
54
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1200 AB-Step
XMC1000 Family
Electrical Parameter
3.3.2
Power-Up and Supply Monitoring Characteristics
Table 24 provides the characteristics of the power-up and supply monitoring in
XMC1200.
The guard band between the lowest valid operating voltage and the brownout reset
threshold provides a margin for noise immunity and hysteresis. The electrical
parameters may be violated while VDDP is outside its operating range.
The brownout detection triggers a reset within the defined range. The prewarning
detection can be used to trigger an early warning and issue corrective and/or fail-safe
actions in case of a critical supply voltage drop.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 24
Power-Up and Supply Monitoring Parameters (Operating Conditions
apply)1)
Parameter
Symbol
Values
Min.
Unit
Typ. Max.
Note /
Test Condition
VDDP ramp-up time
tRAMPUP SR
VDDP/
−
SVDDPrise
107
μs
VDDP slew rate
SVDDPOP SR
0
−
0.1
V/μs Slope during
normal operation
SVDDP10 SR
0
−
10
V/μs Slope during fast
transient within +/10% of VDDP
SVDDPrise SR 0
−
10
V/μs Slope during
power-on or
restart after
brownout event
SVDDPfall2) SR 0
−
0.25
V/μs Slope during
supply falling out
of the +/-10%
limits3)
VDDPPW CC
2.1
2.25
2.4
V
ANAVDEL.VDEL_
SELECT = 00B
2.85
3
3.15
V
ANAVDEL.VDEL_
SELECT = 01B
4.2
4.4
4.6
V
ANAVDEL.VDEL_
SELECT = 10B
VDDP prewarning
voltage
Data Sheet
55
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1200 AB-Step
XMC1000 Family
Electrical Parameter
Table 24
Power-Up and Supply Monitoring Parameters (Operating Conditions
apply)1) (cont’d)
Parameter
Symbol
Values
Min.
Typ. Max.
Unit
Note /
Test Condition
calibrated, before
user code starts
running
VDDP brownout reset
voltage
VDDPBO CC
1.55
1.62
1.75
V
VDDP voltage to
ensure defined pad
states
VDDPPA CC
−
1.0
−
V
Start-up time from
power-on reset
tSSW SR
−
320
–
μs
Time to the first
user code
instruction in all
start-up modes4)
BMI program time
tBMI SR
−
8.25
–
ms
Time taken from a
user-triggered
system reset after
BMI installation is
is requested
1) Not all parameters are 100% tested, but are verified by design/characterisation.
2) A capacitor of at least 100 nF has to be added between VDDP and VSSP to fulfill the requirement as stated for
this parameter.
3) Valid for a 100 nF buffer capacitor connected to supply pin where current from capacitor is forwarded only to
the chip. A larger capacitor value has to be chosen if the power source sink a current.
4) This values does not include the ramp-up time. During startup firmware execution, MCLK is running at 32 MHz
and the clocks to peripheral as specified in register CGATSTAT0 are gated.
5.0V
}
VDDP
VDDPPW
V DDPBO
Figure 19
Data Sheet
Supply Threshold Parameters
56
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1200 AB-Step
XMC1000 Family
Electrical Parameter
3.3.3
On-Chip Oscillator Characteristics
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 25 provides the characteristics of the 64 MHz clock output from the digital
controlled oscillator, DCO1 in XMC1200.
Table 25
64 MHz DCO1 Characteristics (Operating Conditions apply)
Parameter
Symbol
Limit Values
Min.
Unit Test Conditions
Typ. Max.
Nominal frequency
fNOM CC –
64
–
MHz under nominal
conditions1) after
trimming
Accuracy2)
ΔfLT
-1.7
–
3.4
%
with respect to fNOM(typ),
over temperature
(0 °C to 85 °C)
-3.9
–
4.0
%
with respect to fNOM(typ),
over temperature
(-40 °C to 105 °C)
CC
1) The deviation is relative to the factory trimmed frequency at nominal VDDC and TA = + 25 °C.
2) The accuracy of the DCO1 oscillator can be further improved through alternative methods, refer to XMC1000
Oscillator Handling Application Note.
Data Sheet
57
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1200 AB-Step
XMC1000 Family
Electrical Parameter
Figure 20 shows the typical curves for the accuracy of DCO1, with and without
calibration based on temperature sensor, respectively.
4.00
3.00
Accuracy [%]
2.00
Without calibration based
on temperature sensor
1.00
With calibration based on
temperature sensor
0.00
- 1.00
- 2.00
- 3.00
- 4.00
-50
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100 110 120
Temperature [ °C]
Figure 20
Typical DCO1 accuracy over temperature
Table 26 provides the characteristics of the 32 kHz clock output from digital controlled
oscillators, DCO2 in XMC1200.
Table 26
32 kHz DCO2 Characteristics (Operating Conditions apply)
Parameter
Symbol
Limit Values
Nominal frequency
fNOM CC –
32.75 –
kHz under nominal
conditions1) after trimming
Accuracy
ΔfLT CC -1.7
–
3.4
%
with respect to fNOM(typ),
over temperature
(0 °C to 85 °C)
-3.9
–
4.0
%
with respect to fNOM(typ),
over temperature
(-40 °C to 105 °C)
Min.
Typ.
Unit Test Conditions
Max.
1) The deviation is relative to the factory trimmed frequency at nominal VDDC and TA = + 25 °C.
Data Sheet
58
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1200 AB-Step
XMC1000 Family
Electrical Parameter
3.3.4
Serial Wire Debug Port (SW-DP) Timing
The following parameters are applicable for communication through the SW-DP
interface.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 27
SWD Interface Timing Parameters(Operating Conditions apply)
Parameter
Symbol
Values
Unit Note /
Test Condition
Min.
Typ.
Max.
t1 SR
t2 SR
t3 SR
50
–
500000 ns
–
50
–
500000 ns
–
10
–
–
ns
–
SWDIO input hold
t4 SR
after SWDCLK rising edge
10
–
–
ns
–
SWDCLK high time
SWDCLK low time
SWDIO input setup
to SWDCLK rising edge
SWDIO output valid time t5
after SWDCLK rising edge
CC –
–
68
ns
CL = 50 pF
–
–
62
ns
CL = 30 pF
t6
SWDIO output hold time
from SWDCLK rising edge
CC 4
–
–
ns
t1
t2
SWDCLK
t6
SWDIO
(Output )
t5
t3
t4
SWDIO
(Input )
Figure 21
Data Sheet
SWD Timing
59
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1200 AB-Step
XMC1000 Family
Electrical Parameter
3.3.5
SPD Timing Requirements
The optimum SPD decision time between 0B and 1B is 0.75 µs. With this value the
system has maximum robustness against frequency deviations of the sampling clock on
tool and on device side. However it is not always possible to exactly match this value
with the given constraints for the sample clock. For instance for a oversampling rate of
4, the sample clock will be 8 MHz and in this case the closest possible effective decision
time is 5.5 clock cycles (0.69 µs).
Table 28
Optimum Number of Sample Clocks for SPD
Sample
Effective Remark
Sample Sampling Sample
Freq.
Factor
Clocks 0B Clocks 1B Decision
Time1)
8 MHz
4
1 to 5
6 to 12
0.69 µs
The other closest option
(0.81 µs) for the effective
decision time is less robust.
1) Nominal sample frequency period multiplied with 0.5 + (max. number of 0B sample clocks)
For a balanced distribution of the timing robustness of SPD between tool and device, the
timing requirements for the tool are:
•
•
Frequency deviation of the sample clock is +/- 5%
Effective decision time is between 0.69 µs and 0.75 µs (calculated with nominal
sample frequency)
Data Sheet
60
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1200 AB-Step
XMC1000 Family
Electrical Parameter
3.3.6
Peripheral Timings
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
3.3.6.1
Synchronous Serial Interface (USIC SSC) Timing
The following parameters are applicable for a USIC channel operated in SSC mode.
Note: Operating Conditions apply.
Table 29
USIC SSC Master Mode Timing
Parameter
Symbol
Values
Min.
SCLKOUT master clock
period
Unit
Typ. Max.
tCLK CC 62.5
−
−
ns
Slave select output SELO t1
active to first SCLKOUT
transmit edge
CC 80
−
−
ns
Slave select output SELO t2
inactive after last
SCLKOUT receive edge
CC 0
−
−
ns
CC -10
−
10
ns
Receive data input
t4
DX0/DX[5:3] setup time to
SCLKOUT receive edge
SR 80
−
−
ns
Data input DX0/DX[5:3]
t5
hold time from SCLKOUT
receive edge
SR 0
−
−
ns
Data output DOUT[3:0]
valid time
Data Sheet
t3
61
Note /
Test Condition
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1200 AB-Step
XMC1000 Family
Electrical Parameter
Table 30
USIC SSC Slave Mode Timing
Parameter
Symbol
Values
Min.
Unit
Typ. Max.
−
−
ns
Select input DX2 setup to
t10
first clock input DX1 transmit
edge1)
SR 10
−
−
ns
Select input DX2 hold after
last clock input DX1 receive
edge1)
t11
SR 10
−
−
ns
Receive data input
DX0/DX[5:3] setup time to
shift clock receive edge1)
t12
SR 10
−
−
ns
Data input DX0/DX[5:3] hold t13
time from clock input DX1
receive edge1)
SR 10
−
−
ns
Data output DOUT[3:0] valid t14
time
CC -
−
80
ns
DX1 slave clock period
tCLK SR 125
Note /
Test Condition
1) These input timings are valid for asynchronous input signal handling of slave select input, shift clock input, and
receive data input (bits DXnCR.DSEN = 0).
Data Sheet
62
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1200 AB-Step
XMC1000 Family
Electrical Parameter
Master Mode Timing
t1
Select Output
SELOx
t2
Inactive
Inactive
Active
Clock Output
SCLKOUT
Receive
Edge
First Transmit
Edge
t3
Last Receive
Edge
Transmit
Edge
t3
Data Output
DOUT[3:0]
t4
Data Input
DX0/DX[5:3]
t4
t5
Data
valid
t5
Data
valid
Slave Mode Timing
t1 0
Select Input
DX2
Clock Input
DX1
t1 1
Active
Inactive
Receive
Edge
First Transmit
Edge
t1 2
Data Input
DX0/DX[5:3]
Inactive
Last Receive
Edge
Transmit
Edge
t1 2
t1 3
Data
valid
t13
Data
valid
t14
t1 4
Data Output
DOUT[3:0]
Transmit Edge: with this clock edge, transmit data is shifted to transmit data output.
Receive Edge: with this clock edge, receive data at receive data input is latched
.
Drawn for BRGH .SCLKCFG = 00B. Also valid for for SCLKCFG = 01B with inverted SCLKOUT signal.
USIC_SSC_TMGX.VSD
Figure 22
USIC - SSC Master/Slave Mode Timing
Note: This timing diagram shows a standard configuration, for which the slave select
signal is low-active, and the serial clock signal is not shifted and not inverted.
Data Sheet
63
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1200 AB-Step
XMC1000 Family
Electrical Parameter
3.3.6.2
Inter-IC (IIC) Interface Timing
The following parameters are applicable for a USIC channel operated in IIC mode.
Note: Operating Conditions apply.
Table 31
USIC IIC Standard Mode Timing1)
Parameter
Symbol
Values
Unit
Min.
Typ.
Max.
Fall time of both SDA and t1
SCL
CC/SR
-
-
300
ns
Rise time of both SDA and t2
SCL
CC/SR
-
-
1000
ns
0
-
-
µs
250
-
-
ns
4.7
-
-
µs
4.0
-
-
µs
4.0
-
-
µs
4.7
-
-
µs
4.0
-
-
µs
4.7
-
-
µs
-
-
400
pF
Data hold time
t3
Note /
Test Condition
CC/SR
Data set-up time
t4
CC/SR
LOW period of SCL clock
t5
CC/SR
HIGH period of SCL clock t6
CC/SR
Hold time for (repeated)
START condition
t7
Set-up time for repeated
START condition
t8
Set-up time for STOP
condition
t9
Bus free time between a
STOP and START
condition
t10
Capacitive load for each
bus line
Cb SR
CC/SR
CC/SR
CC/SR
CC/SR
1) Due to the wired-AND configuration of an IIC bus system, the port drivers of the SCL and SDA signal lines
need to operate in open-drain mode. The high level on these lines must be held by an external pull-up device,
approximalely 10 kOhm for operation at 100 kbit/s, approximately 2 kOhm for operation at 400 kbit/s.
Data Sheet
64
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1200 AB-Step
XMC1000 Family
Electrical Parameter
Table 32
USIC IIC Fast Mode Timing1)
Parameter
Symbol
Values
Min.
Fall time of both SDA and t1
SCL
CC/SR
Typ.
Unit
Max.
20 +
0.1*Cb
300
ns
20 +
0.1*Cb
300
ns
0
-
-
µs
100
-
-
ns
1.3
-
-
µs
0.6
-
-
µs
0.6
-
-
µs
0.6
-
-
µs
0.6
-
-
µs
1.3
-
-
µs
-
-
400
pF
Note /
Test Condition
2)
Rise time of both SDA and t2
SCL
CC/SR
Data hold time
t3
CC/SR
Data set-up time
t4
CC/SR
LOW period of SCL clock
t5
CC/SR
HIGH period of SCL clock t6
CC/SR
Hold time for (repeated)
START condition
t7
Set-up time for repeated
START condition
t8
Set-up time for STOP
condition
t9
Bus free time between a
STOP and START
condition
t10
Capacitive load for each
bus line
Cb SR
CC/SR
CC/SR
CC/SR
CC/SR
1) Due to the wired-AND configuration of an IIC bus system, the port drivers of the SCL and SDA signal lines
need to operate in open-drain mode. The high level on these lines must be held by an external pull-up device,
approximalely 10 kOhm for operation at 100 kbit/s, approximately 2 kOhm for operation at 400 kbit/s.
2) Cb refers to the total capacitance of one bus line in pF.
Data Sheet
65
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1200 AB-Step
XMC1000 Family
Electrical Parameter
t1
SDA
t2
t4
70%
30%
t1
t3
t2
t6
SCL
th
t7
9
clock
t5
t10
S
SDA
t8
t7
t9
SCL
th
9
clock
Sr
Figure 23
3.3.6.3
P
S
USIC IIC Stand and Fast Mode Timing
Inter-IC Sound (IIS) Interface Timing
The following parameters are applicable for a USIC channel operated in IIS mode.
Note: Operating Conditions apply.
Table 33
USIC IIS Master Transmitter Timing
Parameter
Clock period
Clock HIGH
Symbol
t1 CC
t2 CC
Values
Unit
Note /
Test Condition
VDDP ≥ 3 V
VDDP < 3 V
Min.
Typ.
Max.
2/fMCLK
-
-
ns
4/fMCLK
-
-
ns
0.35 x
-
-
ns
-
-
ns
0
-
-
ns
-
-
0.15 x
ns
t1min
Clock Low
t3 CC
0.35 x
t1min
Hold time
Clock rise time
t4 CC
t5 CC
t1min
Data Sheet
66
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1200 AB-Step
XMC1000 Family
Electrical Parameter
t1
t2
t5
t3
SCK
t4
WA/
DOUT
Figure 24
USIC IIS Master Transmitter Timing
Table 34
USIC IIS Slave Receiver Timing
Parameter
Symbol
t6 SR
t7 SR
Clock period
Clock HIGH
Values
Unit
Min.
Typ.
Max.
4/fMCLK
-
-
ns
0.35 x
-
-
ns
-
-
ns
-
-
ns
-
-
ns
Note /
Test Condition
t6min
t8 SR
Clock Low
0.35 x
t6min
t9 SR
Set-up time
0.2 x
t6min
t10 SR
Hold time
10
t6
t7
t8
SCK
t9
t10
WA/
DIN
Figure 25
Data Sheet
USIC IIS Slave Receiver Timing
67
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1200 AB-Step
XMC1000 Family
Package and Reliability
4
Package and Reliability
The XMC1200 is a member of the XMC1000 Family of microcontrollers. It is also
compatible to a certain extent with members of similar families or subfamilies.
Each package is optimized for the device it houses. Therefore, there may be slight
differences between packages of the same pin-count but for different device types. In
particular, the size of the exposed die pad may vary.
If different device types are considered or planned for an application, it must be ensured
that the board layout fits all packages under consideration.
4.1
Package Parameters
Table 35 provides the thermal characteristics of the packages used in XMC1200.
Table 35
Thermal Characteristics of the Packages
Parameter
Symbol
Limit Values
Unit
Package Types
Min.
Max.
Exposed Die Pad
Dimensions
Ex × Ey
CC
-
2.7 × 2.7
mm
PG-VQFN-24-19
-
3.7 × 3.7
mm
PG-VQFN-40-13
Thermal resistance
Junction-Ambient
RΘJA CC
-
104.6
K/W
PG-TSSOP-16-81)
-
83.2
K/W
PG-TSSOP-28-161)
-
70.3
K/W
PG-TSSOP-38-91)
-
46.0
K/W
PG-VQFN-24-191)
-
38.4
K/W
PG-VQFN-40-131)
1) Device mounted on a 4-layer JEDEC board (JESD 51-5); exposed pad soldered.
Note: For electrical reasons, it is required to connect the exposed pad to the board
ground VSSP, independent of EMC and thermal requirements.
4.1.1
Thermal Considerations
When operating the XMC1200 in a system, the total heat generated in the chip must be
dissipated to the ambient environment to prevent overheating and the resulting thermal
damage.
The maximum heat that can be dissipated depends on the package and its integration
into the target board. The “Thermal resistance RΘJA” quantifies these parameters. The
power dissipation must be limited so that the average junction temperature does not
exceed 115 °C.
Data Sheet
68
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1200 AB-Step
XMC1000 Family
Package and Reliability
The difference between junction temperature and ambient temperature is determined by
ΔT = (PINT + PIOSTAT + PIODYN) × RΘJA
The internal power consumption is defined as
PINT = VDDP × IDDP (switching current and leakage current).
The static external power consumption caused by the output drivers is defined as
PIOSTAT = Σ((VDDP-VOH) × IOH) + Σ(VOL × IOL)
The dynamic external power consumption caused by the output drivers (PIODYN) depends
on the capacitive load connected to the respective pins and their switching frequencies.
If the total power dissipation for a given system configuration exceeds the defined limit,
countermeasures must be taken to ensure proper system operation:
•
•
•
•
Reduce VDDP, if possible in the system
Reduce the system frequency
Reduce the number of output pins
Reduce the load on active output drivers
Data Sheet
69
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1200 AB-Step
XMC1000 Family
Package and Reliability
4.2
Figure 26
Data Sheet
Package Outlines
PG-TSSOP-38-9
70
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1200 AB-Step
XMC1000 Family
Package and Reliability
Figure 27
Data Sheet
PG-TSSOP-28-16
71
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1200 AB-Step
XMC1000 Family
Package and Reliability
Figure 28
Data Sheet
PG-TSSOP-16-8
72
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1200 AB-Step
XMC1000 Family
Package and Reliability
Figure 29
Data Sheet
PG-VQFN-24-19
73
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1200 AB-Step
XMC1000 Family
Package and Reliability
Figure 30
PG-VQFN-40-13
All dimensions in mm.
Data Sheet
74
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
XMC1200 AB-Step
XMC1000 Family
Quality Declaration
5
Quality Declaration
Table 36 shows the characteristics of the quality parameters in the XMC1200.
Table 36
Quality Parameters
Parameter
Symbol Limit Values
Unit
Notes
Min.
Max.
VHBM
ESD susceptibility
according to Human Body SR
Model (HBM)
-
2000
V
Conforming to
EIA/JESD22A114-B
VCDM
ESD susceptibility
SR
according to Charged
Device Model (CDM) pins
-
500
V
Conforming to
JESD22-C101-C
MSL
-
3
-
JEDEC
J-STD-020D
-
260
°C
Profile according
to JEDEC
J-STD-020D
Moisture sensitivity level
CC
Soldering temperature
TSDR
SR
Data Sheet
75
V1.8, 2016-09
Subject to Agreement on the Use of Product Information
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Published by Infineon Technologies AG