XMC1301T038X0064ABXUMA2

XMC1100 / XMC1200 / XMC1300 Fixed Flash Wait States XMC1000 Family ARM® Cortex®-M0 32-bit processor core Data Sheet Addendum V1.0 2016-02 Microcontrollers Edition 2016-02 Published by Infineon Technologies AG 81726 Munich, Germany © 2016 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. XMC1100 / XMC1200 / XMC1300 Fixed Flash Wait States XMC1000 Family ARM® Cortex®-M0 32-bit processor core Data Sheet Addendum V1.0 2016-02 Microcontrollers XMC1100 / XMC1200 / XMC1300 XMC1000 Family XMC1100 / XMC1200 / XMC1300 Data Sheet Addendum Revision History: V1.0 2016-02 Previous Version: none Page Subjects Initial version. Trademarks C166™, TriCore™ , XMC™ and DAVE™ are trademarks of Infineon Technologies AG. ARM®, ARM Powered®, Cortex®, Thumb® and AMBA® are registered trademarks of ARM, Limited. CoreSight™, ETM™, Embedded Trace Macrocell™ and Embedded Trace Buffer™ are trademarks of ARM, Limited. We Listen to Your Comments Is there any information in this document that you feel is wrong, unclear or missing? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com Data Sheet Addendum V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC1100 / XMC1200 / XMC1300 XMC1000 Family Table of Contents Table of Contents 1 1.1 1.2 1.3 1.3.1 Fixed Flash Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Flash read access with fixed wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 NVM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Data Sheet Addendum 5 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC1100 / XMC1200 / XMC1300 XMC1000 Family Fixed Flash Wait States 1 Fixed Flash Wait States The parameter limits defined in this addendum extend the electrical parameters defined in the XMC1100 / XMC1200 / XMC1300 Data Sheet stated below. • • Data Sheet AA-Step, V1.4, 2014-05 Data Sheet AB-Step, V1.6, 2015-04 1.1 Flash read access with fixed wait states Per default the XMC1100 / XMC1200 / XMC1300 devices use a configuration with adaptive wait states for read accesses to the flash memory, dynamically adapting to the system frequency and flash access timing without user software interaction. Alternatively, it is possible to configure the XMC1100 / XMC1200 / XMC1300 devices to apply fixed wait states to each flash read access, improving determinism of program execution from flash. The required number of wait states depends on the system frequency fMCLK, as defined in the parameter NFWSFLASH. The number of wait states can be configured with the bit NVM_NVMCONF.WS, the selection of adaptive or fixed wait states is done with the bit NVM_CONFIG1.WS. Attention: Any write operation to the register NVM_CONFIG1 to switch between adaptive and fixed wait states configuration must only modify the bit NVM_CONFIG1.FIXWS. Changing other bits in NVM_CONFIG1 can lead to unpredictable results. Attention: Before and after the fixed wait states configuration or the system frequency fMCLK is changed, the number of selected wait states must always comply to the parameter NFWSFLASH. Below is a code snippet defining the register addresses, configuring one wait state and then switching to operation with fixed wait states. Example // Headers and variables to fix number of wait states to "1" #define ADDR1 0x40050008 //Address of NVM_NVMCONF uint32_t * NVM_NVMCONF = (uint32_t *) ADDR1; #define ADDR2 0x40050048 //Address of NVM_CONFIG1 uint32_t * NVM_CONFIG1 = (uint32_t *) ADDR2; // init sequence to fix number of wait states to "1" *NVM_NVMCONF = *NVM_NVMCONF | 0x1000; //Set .WS bit => 1WS *NVM_CONFIG1 = *NVM_CONFIG1 | 0x0800; //Set .FIXWS bit => fixed WS scheme Data Sheet Addendum 6 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC1100 / XMC1200 / XMC1300 XMC1000 Family Fixed Flash Wait States 1.2 NVM Registers NVM Configuration Register The definition of bit NVMCONF.12 changes to NVMCONF.WS. NVM_NVMCONF NVM Configuration Register 15 14 NVM INT_ _ON ON rw rw 13 12 11 0 WS rw rw 10 (4005 0008H) 9 8 7 Reset Value: 9000H 6 5 4 3 2 1 0 SECPROT 0 HRLEV 0 rw r rw rw Field Bits Type Description NVM_ON 15 rw NVM On When cleared, no software code can be executed anymore from the NVM, until it is set again. I.e., already the software code that initiates the change in NVM_ON itself may not reside in the NVM, otherwise the software is stalled forever. SLEEP, NVM is switched to or stays in sleep mode. 0B 1B NORM, NVM is switched to or stays in normal mode. INT_ON 14 rw Interrupt On When enabled the completion of a sequence started by setting NVMPROG.ACTION (write or erase sequence) will be indicated by NVM interrupt. The same is true for the wake-up sequence. INTOFF, No NVM ready interrupts are generated. 0B 1B INTON, NVM ready interrupts are generated. 0 13 rw Reserved for Future Use Must be written with 0 to allow correct operation. WS 12 rw Number of fixed Wait States Defines the number of fixed wait states when NVM_CONFIG1.FIXWS = 1B. 0 fixed wait states. 0B 1B 1 fixed wait state. SECPROT 11:4 rw Sector Protection1) This field defines the number of write, erase, verify protected sectors, starting with physical sector 0. Data Sheet Addendum 7 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC1100 / XMC1200 / XMC1300 XMC1000 Family Fixed Flash Wait States Field Bits Type Description 0 3 r Reserved Read as 0; should be written with 0. HRLEV 2:1 rw Hardread Level2) Defines single hardread level for verification with NVMPROG.ACTION.VERIFY = 11B: 00B NR, Normal read 01B HRW, Hardread written 10B HRE, Hardread erased 11B RFU, Reserved for Future Use 0 0 rw Reserved for Future Use Must be written with 0 to allow correct operation. 1) For SECPROT > 0, SECPROT defines the number of protected sectors. The sectors 0 to SECPROT-1 cannot be written, erased, or verified. All writes that target the protected sectors are accepted, but are internally ignored. 2) HRLEV defines the hardread level for a stand-alone verification sequence started with NVMPROG.ACTION.VERIFY = 11B. This hardread level is used until the end of the verification sequence. HRLEV may not be changed in between. Configuration 1 Register The bit NVM_CONFIG1.FIXWS allows to switch between adaptive and fixed wait state configuration. Attention: Any write operation to the register NVM_CONFIG1 to switch between adaptive and fixed wait states configuration must only modify the bit NVM_CONFIG1.FIXWS. Changing other bits in NVM_CONFIG1 can lead to unpredictable results. NVM_CONFIG1 Configuration 1 Register 15 14 13 12 11 (4005 0048H) 10 9 8 7 Reset Value: XXXXH 6 5 RES FIX WS RES rw rw rw Field Bits RES 15:12 rw Data Sheet Addendum 4 3 2 1 0 Type Description Reserved Must not be changed when programming the NVM_CONFIG1 register. 8 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC1100 / XMC1200 / XMC1300 XMC1000 Family Fixed Flash Wait States Field Bits Type Description FIXWS 11 rw Wait States Scheme Defines the scheme by which flash wait states are generated. Withfixed wait states NVM_NVMCONF.WS defines the number of wait states. adaptive wait states. 0B fixed wait states. 1B RES 10:0 rw Reserved Must not be changed when programming the NVM_CONFIG1 register. Data Sheet Addendum 9 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC1100 / XMC1200 / XMC1300 XMC1000 Family Fixed Flash Wait States 1.3 Electrical Parameters 1.3.1 Flash Memory Parameters This definition expands the flash wait states definition by parameters for the configuration with fixed wait states. Table 1 Flash Memory Parameters Parameter Symbol Values Fixed Flash Wait States configured in bit NVM_NVMCONF.WS NFWSFLASH 0 Min. Typ. Max. Data Sheet Addendum 0 1 NVM_CONFIG1. FIXWS = 1B, fMCLK ≤ 16 MHz 1 1 NVM_CONFIG1. FIXWS = 1B, 16 MHz < fMCLK ≤ 32 MHz SR 1 10 Unit Note / Test Condition V1.0, 2016-02 Subject to Agreement on the Use of Product Information w w w . i n f i n e o n . c o m Published by Infineon Technologies AG