EUA2310B
15-W Stereo Class-D Audio Power
Amplifier with Speaker Protection
DESCRIPTION
FEATURES
The EUA2310B is a high efficiency, 2 channel bridged-tied
load (BTL), class-D audio power amplifier. Operating from
a 16V power supply, EUA2310B is capable of delivering
15W/ channel of continuous output power to a 8Ω load
with 10% THD+N. The EUA2310B features a differential
input architecture offering improved noise immunity over a
single-ended (SE) input amplifier. Amplifier gain is
internally configured and can be selected to 20, 26, 32 or
36dB utilizing the G0 and G1 gain select pins. Advanced
EMI suppression technology enables the use of
inexpensive ferrite bead at the outputs while meeting EMC
requirements.
The speaker protection circuitry is integrated into
EUA2310B to limit the amount of current through the
speaker. Meanwhile, the AGC detects output signal clip
due to the over level input signal and suppresses it
automatically. The EUA2310B also features short-circuit
and thermal protection preventing the device from being
damaged during a fault condition. The EUA2310B is
available in thermally efficient 28-pin TSSOP package.
Wide Supply Voltage: 5.5V to 26V
Unique Modulation Scheme Reduces EMI Emission
15-W/ch into an 8-Ω Load From a 16-V Supply
10-W/ch into an 8-Ω Load From a 13-V Supply
30W into a 4-Ω Mono Load From a 16-V Supply
87% Efficient Class-D Operation Eliminates
Need for Heat Sinks
Four Selectable, Gain Settings
Differential Inputs
Speaker Protection Circuitry
Auto Gain Control and Power Clamp
Thermal and Short-Circuit Protection
28-pin TSSOP Package with Thermal Pad
RoHS compliant and 100% lead(Pb)-free
Halogen-Free
APPLICATIONS
Televisions
Typical Application Circuit
Figure1. Simplified Application Schematic
DS2310B
Ver1.1
Dec. 2013
1
EUA2310B
Pin Configurations
Package Type
Pin Configurations
TSSOP-28 (EP)
Pin Description
PIN
SD
1
I
FAULT
2
O
LINP
3
I
DESCRIPTION
Shutdown logic input for audio amp (LOW = outputs Hi-Z, HIGH = outputs
enabled). TTL logic levels with compliance to AVCC.
Open drain output used to display short circuit or dc detect fault status.
Voltage compliant to AVCC.
Positive audio input for left channel.
LINN
4
I
Negative audio input for left channel.
GAIN0
5
I
Gain select least significant bit. TTL logic levels with compliance to AVCC.
GAIN1
6
I
Gain select most significant bit. TTL logic levels with compliance to AVCC.
AVCC
7
P
Analog supply
AGND
8
P
GVDD
9
O
PLIMIT
10
I
RINN
11
I
Analog signal ground. Connect to the thermal pad.
High-side FET gate drive supply. Nominal voltage is 4.5V. Also should be
used as supply for PLIMIT function.
Power limit level adjust. Connect a resistor divider from GVDD to GND to
set power limit. Connect directly to GVDD for no power limit.
Negative audio input for right channel.
RINP
12
I
Positive audio input for right channel.
NC
13
P
Power limit mode select. Defaulted low level for AGC function.
PBTL
14
I
PVCCR
15,16
P
BSPR
17
I
Parallel BTL mode switch
Power supply for right channel H-bridge. Right channel and left channel
power supply inputs are connect internally.
Bootstrap I/O for right channel, positive high-side FET.
OUTPR
18
O
Class-D H-bridge positive output for right channel.
PGND
19
OUTNR
20
O
Class-D H-bridge negative output for right channel.
BSNR
21
I
Bootstrap I/O for right channel, negative high-side FET.
BSNL
22
I
Bootstrap I/O for left channel, negative high-side FET.
DS2310B
TSSOP-28(EP) I/O/P
Ver1.1
Dec. 2013
Power ground for the H-bridges.
2
EUA2310B
Pin Description (Continued)
PIN
TSSOP-28(EP)
I/O
DESCRIPTION
OUTNL
23
O
PGND
24
OUTPL
25
O
Class-D H-bridge positive output for left channel.
BSPL
26
I
PVCCL
27,28
P
Bootstrap I/O for left channel, positive high-side FET.
Power supply for left channel H-bridge. Right channel and left channel
power supply inputs are connect internally.
Class-D H-bridge negative output for left channel.
Power ground for the H-bridges.
Ordering Information
Order Number
Package Type
Marking
Operating Temperature Range
EUA2310BXIR1
TSSOP-28 (EP)
xxxxx
EUA2310B
-40 °C to +85°C
EUA2310B □ □ □ □
Lead Free Code
1: Lead Free, Halogen Free
Packing
R: Tape & Reel
Operating temperature range
I: Industry Standard
Package Type
X:TSSOP (EP)
DS2310B
Ver1.1
Dec. 2013
3
EUA2310B
Absolute Maximum Ratings
▓
▓
▓
▓
▓
▓
▓
▓
▓
▓
Supply Voltage, AVCC,PVCC, ------------------------------------------------------------------------- -0.3 V to 30V
Input Voltage, SD ,GAIN0,GAIN1,PBTL, FAULT ----------------------------------------- -0.3 V to VCC +0.3V
Input Voltage, PLIMIT ---------------------------------------------------------------------- -0.3 V to GVDD +0.3V
Input Voltage, RINN,RINP,LINN,LINP ------------------------------------------------------------- -0.3 V to 6.3V
Thermal Resistance θJA (TSSOP-28_EP) ---------------------------------------------------------------34°C /W
Free-air Temperature Range, TA -------------------------------------------------------------------- -40°C to +85°C
Junction Temperature Range, TJ ------------------------------------------------------------------- -40°C to +150°C
Storage Temperature Rang, Tstg ------------------------------------------------------------------ -65°C to +150°C
Lead Temperature ----------------------------------------------------------------------------------------260°C
Load Resistance, RLOAD ---------------------------------------------------------------------------------- 3.2Ω Minimum
Recommended Operating Conditions
Supply voltage, VCC
Min.
Max.
Unit
5.5
26
V
PVCC,AVCC
High-level input voltage, VIH
SD
2
GAIN0,GAIN1,PBTL,NC
4
V
Low-level input voltage, VIL
SD ,GAIN0,GAIN1,PBTL,NC
0.8
V
High-level input current, IIH
SD ,GAIN0,GAIN1,PBTL,VI=2V,VCC=18V
50
µA
Low-level input current, IIL
SD ,GAIN0,GAIN1,PBTL,VI=0.8V,VCC=18V
5
µA
Low-level output voltage, VOL
FAULT , RPULL-UP=100k, VCC=26V
0.8
V
Oscillator frequency, fOSC
230
330
kHz
Operating free-air temperature, TA
-40
85
°C
DC Characteristics TA = +25°C ,VCC=24V, RL=8Ω (Unless otherwise noted)
Symbol
VOS
ICC
Parameter
Conditions
Class-D output offset voltage
(measured differentially)
VI= 0V, Gain = 36dB
Quiescent supply current
SD =2V, no load, PVCC=24V
5
ICC(SD)
Quiescent supply current in shutdown
SD =0.8V, no load, PVCC=24V
mode
rDS(on)
Drain-source on-state resistance
200
High Side
VCC=12V,
IO=500mA, TJ=25°C Low Side
GAIN1=0.8V
G
EUA2310B
Unit
Min. Typ. Max.
Gain
GAIN1=4V
50
mV
65
mA
1000
µA
240
mΩ
240
GAIN0=0.8V
19
20
21
GAIN0=4V
25
26
27
GAIN0=0.8V
31
32
33
GAIN0=4V
35
36
37
dB
dB
tON
Turn-on time
SD =2V
28
ms
tOFF
Turn-off time
SD =0.8V
28
ms
GVDD Gate Drive Supply
IGVDD=100µA
tDCDET
V(RINN)=5V, VRINP=0V
DS2310B
DC Detect time
Ver1.1
Dec. 2013
4
4.2
4.5
420
4.8
V
ms
EUA2310B
DC Characteristics TA = +25°C ,VCC=12V, RL=8Ω (Unless otherwise noted)
Symbol
VOS
ICC
Parameter
Conditions
Class-D output offset voltage
(measured differentially)
VI= 0V,Gain =36dB
Quiescent supply current
SD =2V, no load, PVCC=12V
5
ICC(SD)
Quiescent supply current in shutdown
SD =0.8V, no load, PVCC=12V
mode
rDS(on)
Drain-source on-state resistance
200
High Side
VCC=12V,
IO=500mA, TJ=25°C Low Side
GAIN1=0.8V
G
EUA2310B
Unit
Min. Typ. Max.
Gain
GAIN1=4V
50
mV
45
mA
1000
µA
240
mΩ
240
GAIN0=0.8V
19
20
21
GAIN0=4V
25
26
27
GAIN0=0.8V
31
32
33
GAIN0=4V
35
36
37
dB
dB
tON
Turn-on time
SD =2V
28
ms
tOFF
Turn-off time
SD =0.8V
28
ms
GVDD Gate Drive Supply
VO
Output voltage maximum under
PLIMIT control
IGVDD=2mA
4.2
4.5
4.8
V
V(PLIMIT)=1.3V, VI=1Vrms
6.75
7.90
8.75
V
AC Characteristics TA = +25°C ,VCC=24V, RL=8Ω (Unless otherwise noted)
Symbol
KSVR
PO
Parameter
Conditions
EUA2310B
Unit
Min. Typ. Max.
Power supply ripple rejection
200mVPP ripple at 1kHz,
Gain= 20dB, Inputs ac-coupled to AGND
-60
dB
Continuous output power
THD+N=10%, f=1kHz, VCC=16V
15
W
0.2
%
THD+N Total harmonic distortion +noise VCC=16V, f=1kHz, Po=7.5W( half-power)
Vn
Output integrated noise
20Hz to 22kHz, A-weighted filter,
Gain=20dB
200
µV
-74
dBV
Crosstalk
VO=1Vrms, Gain=20dB, f=1kHz
Maximum output at THD+N< 1%,
f=1kHz,Gain=20dB, A-weighted
-100
dB
90
dB
SNR
Signal-to-noise ratio
fOSC
Oscillator frequency
DS2310B
230
280
330
kHz
Thermal trip point
150
°C
Thermal hysteresis
30
°C
Ver1.1
Dec. 2013
5
EUA2310B
AC Characteristics TA = +25°C ,VCC=12V, RL=8Ω (Unless otherwise noted)
Symbol
KSVR
PO
Parameter
Conditions
EUA2310B
Unit
Min. Typ. Max.
Power supply ripple rejection
200mVPP ripple from 20Hz ~1kHz,
Gain= 20dB, Inputs ac-coupled to AGND
-60
dB
Continuous output power
THD+N=10%, f=1kHz, VCC=13V
10
W
0.2
%
THD+N Total harmonic distortion +noise RL=8Ω, f=1kHz, Po=5W( half-power)
Vn
Output integrated noise
20Hz to 22kHz, A-weighted filter,
Gain=20dB
200
µV
-74
dBV
Crosstalk
PO=1W, Gain=20dB, f=1kHz
Maximum output at THD+N< 1%,
f=1kHz,Gain=20dB, A-weighted
-100
dB
90
dB
SNR
Signal-to-noise ratio
fOSC
Oscillator frequency
230
330
kHz
Thermal trip point
150
°C
Thermal hysteresis
30
°C
Block Diagram
Figure2.
DS2310B
280
Ver1.1
Dec. 2013
6
EUA2310B
Typical Characteristics
Figure3.
DS2310B
Ver1.1
Dec. 2013
Figure4.
Figure5.
Figure6.
Figure7.
Figure8.
7
EUA2310B
DS2310B
Ver1.1
Dec. 2013
Figure9.
Figure10.
Figure11.
Figure12.
Figure13.
Figure14.
8
EUA2310B
Figure15.
Figure16.
Figure17.
Figure18.
Figure19.
DS2310B
Ver1.1
Dec. 2013
Figure20.
9
EUA2310B
DS2310B
Ver1.1
Dec. 2013
Figure21.
Figure22.
Figure23.
Figure24.
Figure25.
Figure26.
10
EUA2310B
Figure27.
Figure28.
Figure29.
Figure30.
Figure31.
DS2310B
Ver1.1
Dec. 2013
Figure32.
11
EUA2310B
Figure33.
Figure34.
Figure35.
Figure36.
Figure37.
DS2310B
Ver1.1
Dec. 2013
Figure38.
12
EUA2310B
Figure39. EMI Test and FCC Limits
DS2310B
Ver1.1
Dec. 2013
13
EUA2310B
Application Information
Differential Input
The differential input stage of the amplifier cancels any common-mode noise that appears on both input lines of the audio
channel. To use the EUA2310B with a differential source, connect the positive signal of the audio source to the INP pin
and the negative signal from the audio source to the INN pin (Figure 40).
Figure 40. Differential Input
Single-Ended Input
When using an audio source with a single-ended “out”, it is important to connect the RINN and LINN pins to the GND of
the audio source with coupling capacitors. (Figure 41).
Figure 41. Single Ended Input
DS2310B
Ver1.1
Dec. 2013
14
EUA2310B
Application Information (continued)
Figure 42. 4Ω/30W PBTL Output
DS2310B
Ver1.1
Dec. 2013
15
EUA2310B
duty cycle to fixed maximum value. This limit can be
thought of as a "virtual" voltage rail which is lower than
the supply connected to PVCC. This "virtual" rail is 4
times the voltage at the PLIMIT pin. The output voltage
can be used to calculate the maximum output power for a
given maximum input voltage and speaker impedance.
Gain Selection
The gain of the EUA2310B is set by two input terminals,
GAIN0 and GAIN1.
The gains listed in Table 1 are realized by changing the
taps on the input resistors and feedback resistors inside
the amplifier. This causes the input impedance (ZI) to be
dependent on the gain setting. The actual gain settings are
controlled by ratios of resistors, so the gain variation from
part-to-part is small. However, the input impedance from
part-to-part at the same gain may shift by ±20% due to
shifts in the actual resistance of the input resistors.
For design purposes, the input network should be
designed assuming an input impedance of 40 kΩ, which is
the absolute minimum input impedance of the EUA2310B.
At the lower gain settings, the input impedance could
increase as high as 120 kΩ.
Table.1 Gain Setting
GAIN1 GAIN0
0
0
1
1
0
1
0
1
POUT
AMPLIFIER
INPUT
GAIN (dB) IMPEDANCE (kΩ)
TYP
TYP
20
100
26
50
32
50
36
50
6.5 × VPLIMIT
VP =
V
2.5 × INP
2
Dec. 2013
If 0.65 × VPLIMIT <
If
VINP
< 2.6 × VPLIMIT
2
VINP
> 2.6 × VPLIMIT
2
------------------------------------------------------ (2)
For power clamp mode：
VP = 4 × VPLIMIT if VPLIMIT < 4 × VP -------------- (3)
POUT (10%THD) = 1.25 × POUT (unclipped)
Table.2 PLIMIT Typical Operation (AGC mode)
Test Conditions
PLIMIT Mode Select
The power limit mode is set by the pin 13 NC. The NC
pin is default set to logical low and the auto gain control
circuit is activated. Connect NC pin to high level for
power clamp function.
PLIMIT
The voltage at pin 10 can be used to limit the power to
levels below that which is possible based on the supply
rail .Add a resistor divider from GVDD to ground to set
the voltage at the PLIMIT pin. An external reference may
also be used if tighter tolerance is required. Also add a
1µF capacitor from pin 10 to ground.
Auto Gain Control circuit is included to limit the output
peak-to-peak voltage, by adjusting the gain of the
amplifier. The gain changes depending on the amplitude,
the PLIMIT level, and the attack and release time. The
gain changes constantly as the audio signal increases
and/or decreases to suppress the clipped output signal.
The Power clamp circuit sets a limit on the output
peak-to-peak voltage. The limiting is done by limiting the
Ver1.1
-------------- (1)
For unclipped power
Where:
RS is the total series resistance including RDS(on), and any
resistance in the output filter.
RL is the load resistance.
VP is the peak amplitude of the output, VIN is the input
amplitude.
For auto gain control mode:
SD Operation
Connect SD to a logic high for normal operation. Pulling
SD low causes the outputs to mute and the amplifier to
enter a low-current state. Never leave SD unconnected,
because amplifier operation would be unpredictable.
For the best power-off pop performance, place the
amplifier in the shutdown prior to removing the power
supply voltage.
DS2310B
RL
R + 2 × R × 2 VP
L
S
=
2× RL
PVCC=24V, VIN=1Vrms,
RL =8Ω, Gain=26dB
PVCC=24V, VIN=1Vrms,
RL =8Ω,Gain=26dB
PVCC=24V, VIN=1Vrms,
RL =8Ω, Gain=26dB
PVCC=24V, VIN=1Vrms,
RL =8Ω, Gain=26dB
PVCC=24V, VIN=1Vrms,
RL =8Ω, Gain=26dB
PVCC=24V, VIN=1Vrms,
RL =8Ω, Gain=20dB
PVCC=24V, VIN=1Vrms,
RL =8Ω, Gain=20dB
PVCC=24V, VIN=1Vrms,
RL =8Ω, Gain=20dB
PVCC=24V, VIN=1Vrms,
RL =8Ω, Gain=20dB
16
PLIMIT
Output
Voltage Power (W)
Output Voltage
Amplitude
(VP-P)
4.5
35.2
43.6
1.6
18.4
35.4
1.31
13.1
30
1.01
8.8
25.2
0.102
4.05
17.2
4.5
12.2
29.2
1.2
11.2
28
1.024
8.1
24
0.1
1.05
9.2
EUA2310B
Table.2 PLIMIT Typical Operation (AGC mode)
Test Conditions
PLIMIT
Output
Voltage Power (W)
PVCC=12V, VIN=1Vrms,
RL =8Ω, Gain=20dB
PVCC=12V, VIN=1Vrms,
RL=8Ω, Gain=20dB
PVCC=12V, VIN=1Vrms,
RL=8Ω, Gain=20dB
DC Detect
EUA2310B has circuitry which will protect the speakers
from DC current which might occur due to defective
capacitors on the input or shorts on the printed circuit
board at the inputs. A DC detect fault will be reported on
the FAULT pin as a low state. The DC Detect fault will
also cause the amplifier to shutdown by changing the state
of the outputs to Hi-Z. To clear the DC Detect it is
necessary to cycle the PVCC supply. Cycling SD will
NOT clear a DC detect fault.
A DC Detect Fault is issued when the output differential
duty-cycle of either channel exceeds 20% (for example,
+60%, -40%) for more than 420 mSec at the same polarity.
This feature protects the speaker from large DC currents
or AC currents less than 2Hz. To avoid nuisance faults
due to the DC detect circuit, hold the SD pin low at
power-up until the signals at the inputs are stable. Also,
take care to match the impedance seen at the positive and
negative inputs to avoid nuisance DC detect faults.
PBTL Select
EUA2310B offers the feature of parallel BTL operation
with two outputs of each channel connected directly. If
the PBTL pin (pin 14) is tied high, the positive and
negative outputs of each channel (left and right) are
synchronized and in phase. To operate in this PBTL
(mono) mode, apply the input signal to the RIGHT input
and place the speaker between the LEFT and RIGHT
outputs. Connect the positive and negative output together
for best efficiency. For an example of the PBTL
connection, see the schematic in the APPLICATION
INFORMATION section.
For normal BTL operation, connect the PBTL pin to local
ground.
Short-Circuit Protection and Automatic Recovery
Feature
The EUA2310B has short-circuit protection circuitry on
the outputs that prevents damage to the device during
output-to-output shorts, output-to-GND shorts, and
output-to-VCC shorts. When a short circuit is detected on
the outputs, the part disables the output drive. A latched
fault flag is resulted. The EUA2310B can automatic
recover for normal operation if short was removed. If the
short was not removed, the protection circuitry again
activates.
Output Voltage
Amplitude
(VP-P)
4.5
9.25
22.8
0.75
4.18
17.6
0.1
1.07
9.4
Table.3 PLIMIT Typical Operation (Power Clamp mode)
Test Conditions
PLIMIT
Output
Voltage Power (W)
PVCC=24V, VIN=1Vrms,
RL=8Ω, Gain=26dB
PVCC=24V, VIN=1Vrms,
RL=8Ω,Gain=26dB
PVCC=24V, VIN=1Vrms,
RL=8Ω, Gain=26dB
PVCC=24V, VIN=1Vrms,
RL=8Ω, Gain=26dB
PVCC=24V, VIN=1Vrms,
RL=8Ω, Gain=26dB
PVCC=24V, VIN=1Vrms,
RL=8Ω, Gain=20dB
PVCC=24V, VIN=1Vrms,
RL=8Ω, Gain=20dB
PVCC=24V, VIN=1Vrms,
RL=8Ω, Gain=20dB
PVCC=24V, VIN=1Vrms,
RL=8Ω, Gain=20dB
PVCC=12V, VIN=1Vrms,
RL=8Ω, Gain=20dB
PVCC=12V, VIN=1Vrms,
RL=8Ω, Gain=20dB
PVCC=12V, VIN=1Vrms,
RL=8Ω, Gain=20dB
Output Voltage
Amplitude
(VP-P)
4.5
24.5
34.8
1.6
8.51
20
1.31
6.65
17.6
1.01
4.95
15.2
0.102
1.22
8.4
4.5
12.1
29.2
1.2
4.9
16.4
1.024
4.2
15.2
0.1
1.09
8
4.5
9.2
23
0.75
3.1
12.8
0.1
1.05
8
Auto Gain Control Function
The AGC works by detecting the audio input envelope.
The gain changes depending on the amplitude, the power
supply level, and the attack and release time. The gain
changes constantly as the audio signal increases and/or
decreases to suppress the clipped output signal. The
maximum attenuation is -12dB. The attack time is
24mSec and the released time is 24mSec per step.
Thermal Protection
Thermal protection on the EUA2310B prevents damage to
the device when the internal die temperature exceeds
150oC. There is a 10oC tolerance on this trip point from
device to device. Once the die temperature exceeds the
thermal set point, the device enters into the shutdown
state and the outputs are disabled. This is not a latched
fault. The thermal fault is cleared once the temperature of
the die is reduced by 30oC. The device begins normal
operation at this point with no external system interaction.
GVDD Supply
The GVDD Supply is used to power the gates of the
output full bridge transistors. It can also be used to supply
the PLIMIT voltage divider circuit. Add a 1µF capacitor
to ground at this pin.
DS2310B
Ver1.1
Dec. 2013
17
EUA2310B
Input Resistance
Changing the gain setting can vary the input resistance of
the amplifier from its smallest value, 50 kΩ ±20%, to the
largest value, 100 kΩ ±20%. As a result, if a single
capacitor is used in the input high-pass filter, the -3 dB or
cutoff frequency may change when changing gain steps.
prevents oscillations for long lead lengths between the
amplifier and the speaker. The optimum decoupling is
achieved by using two capacitors of different types that
target different types of noise on the power supply leads.
For higher frequency transients, spikes, or digital hash on
the line, a good low equivalent-series-resistance (ESR)
ceramic capacitor, typically 0.1µF to 1µF placed as close
as possible to the device VCC lead works best. For
filtering lower frequency noise signals, a larger aluminum
electrolytic capacitor of 220µF or greater placed near the
audio power amplifier is recommended. The 220µF
capacitor also serves as local storage capacitor for
supplying current during large signal transients on the
amplifier outputs. The PVCC terminals provide the power
to the output transistors, so a 220µF or larger capacitor
should be placed on each PVCC terminal. A 10µF
capacitor on the AVCC terminal is adequate.
BSN and BSP Capacitors
The full H-bridge output stages use only NMOS
transistors, that require bootstrap capacitors for the high
side of each output to turn on correctly. A 220nF~1uF
ceramic capacitor, rated for at least 25V, must be
connected from each output to its corresponding bootstrap
input. (See application circuit diagram in Figure 38,39.)
The bootstrap capacitors connected between the BSxx
pins and corresponding output function as a floating
power supply for the high-side N-channel power
MOSFET gate drive circuitry. During each high-side
switching cycle, the bootstrap capacitors hold the
gate-to-source voltage high enough to keep the high-side
MOSFETs turned on.
The -3dB frequency can be calculated using Equation 4.
Use the ZI values given in Table 1.
f =
1
2 πZ C
i i
---------------- (4)
Input Capacitor, CI
In the typical application, an input capacitor (CI) is
required to allow the amplifier to bias the input signal to
the proper dc level for optimum operation. In this case, CI
and the input impedance of the amplifier (ZI) form a
high-pass filter with the corner frequency determined in
Equation 5.
Using Low-ESR Capacitors
1
f =
c 2 πZ C
i i
Use capacitors with an ESR less than 100mΩ for
optimum performance. Low-ESR ceramic capacitors
minimize the output resistance. For best performance over
the extended temperature range, select X7R capacitors.
-----------------(5)
The value of CI is important, as it directly affects the bass
(low-frequency) performance of the circuit. Consider the
example where ZI is 50 kΩ and the specification calls for
a flat bass response down to 20 Hz. Equation 5 is
reconfigured as Equation 6.
1
C =
i 2 πZ f
i c
Output Filter
Most applications require a ferrite bead filter. The ferrite
filter reduces EMI around 1 MHz and higher (FCC and
CE only test radiated emissions greater than 30 MHz).
When selecting a ferrite bead, choose one with high
impedance at high frequencies, but low impedance at low
frequencies.
Use an LC output filter if there are low frequency (
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