EUP3420

EUP3420 2A/1.5MHz, Synchronous Step-Down Converter with Soft Start DESCRIPTION The EUP3420 is a synchronous current mode step-down dc-dc converter, capable of delivering 2A load current with excellent line and load regulation. Operating with an input voltage range between 2.7V and 5.5V, the device is ideal for portable applications powered by a single Li-Ion battery cell or by 3-cell NiMH/NiCd batteries. The EUP3420 operates at 1.5MHz fixed frequency PWM mode and provides very low output ripple voltage for noise sensitive applications. The internal integrated synchronous switch increases efficiency while eliminates the need for an external Schottky diode. The EUP3420 is available in the 10-pin MSOP and 10-pin TDFN package. FEATURES High Efficiency up to 96% Up to 2A Load Current 300µA Typical Quiescent Current 1.5MHz Constant Switching Frequency 2.7V to 5.5V Input Voltage Range Adjustable Output Voltage as Low as 0.7V 100% Duty Cycle Low Dropout Operation No Schottky Diode Required Short Circuit and Thermal Protection Excellent Line and Load Transient Response ＜1µA Shutdown Current Built-In Soft-Start Available in MSOP-10 and TDFN-10 Package RoHS Compliant and 100% Lead(Pb)-Free APPLICATIONS Cellular and Smart Phones Portable Media Players/ MP3 Players Digital Still and Video Cameras Portable Instruments WLAN PC Cards Typical Application Circuit Figure 1. DS3420 Ver1.2 Mar. 2009 1 EUP3420 Pin Configurations Package Type Pin Configurations Package Type Pin Configurations MSOP-10 TDFN-10 Pin Description Name EN VIN GND FB MODE SW PGND MSOP-10 1 2,3 4 5 6 7,8 9,10 TDFN-10 1 2,3 4 5 6 7,8 9,10 DESCRIPTION Chip enable pin. Forcing this pin above 1.5V enables the part. Forcing this pin below 0.3V shuts down the device. Do not leave EN floating. Supply voltage input. Analog ground. Feedback pin. Pulling the MODE pin high allows the device to be forced into fixed frequency operation. Switch node connection to inductor. This pin connects to the drains of the internal main and synchronous power MOSFET switches. Power ground. Block Diagram Figure 2. DS3420 Ver1.2 Mar. 2009 2 EUP3420 Ordering Information Order Number EUP3420MIR1 EUP3420JIR1 Package Type MSOP-10 TDFN-10 Marking xxxxx P3420 xxxxx P3420 Operating Temperature Range -40 °C to +85°C -40 °C to +85°C EUP3420 □ □ □ □ Lead Free Code 1: Lead Free 0: Lead Packing R: Tape & Reel Operating temperature range I: Industry Standard Package Type M: MSOP J: TDFN DS3420 Ver1.2 Mar. 2009 3 EUP3420 Absolute Maximum Ratings (1) Input Supply Voltage ----------------------------------------------------------- -0.3V to 6V EN, FB Voltages ---------------------------------------------------------------- -0.3V to VIN P-Channel Switch Source Current (DC) ------------------------------------------2.2A N-Channel Switch Sink Current (DC) ---------------------------------------------2.2A Peak SW Sink and Source Current -------------------------------------------------3A Junction Temperature ------------------------------------------------------------------- 125°C Storage Temperature ------------------------------------------------------- -65°C to 150°C Lead Temp (Soldering, 10sec) ------------------------------------------------------260°C Recommend Operating Conditions (2) Supply Voltage (VIN) ----------------------------------------------------------- 2.7V to 5.5V Operating Temperature Range --------------------------------------------- -40°C to +85°C Note (1): Stress beyond those listed under “Absolute Maximum Ratings” may damage the device. Note (2): The device is not guaranteed to function outside the recommended operating conditions. Electrical Characteristics The ● denote the Spec. apply over the full operating temperature range, otherwise Spec. are TA=+25℃. VIN=3.6V unless otherwise specified. Symbol VIN UVLO IFB VFB ∆VFB ∆VOUT IQ ISHDN IPK fOSC RPFET RNFET ILSW VEN Parameter Input Voltage Range Input Undervoltage Lockout Feedback Current Regulated Feedback Voltage Reference Voltage Line Regulation Output Voltage Line Regulation Quiescent Current Shutdown Current Peak Inductor Current Oscillator Frequency RDS(ON) of P-Channel FET RDS(ON) of N-Channel FET SW Leakage Current EN Threshold Conditions ● ● TA=+25°C (Note 3) -40°C≤ TA≤+85°C (Note 3) VIN=2.7V to 5.5V VIN=2.7V to 5.5V ILOAD=0mA to 2000mA VFB=0.45V, ILOAD=0A VEN=0V VIN=3.6V, VFB=0.45V VFB=0.45V VFB=0V ISW=200mA ISW=200mA VEN=0V, VSW=0 or 5V, VIN=5V Min 2.7 1.5 EUP3420 Typ Max. 5.5 2.3 0 0.5 0.5 0.26 0.26 0.2 0.51 0.515 0.4 0.4 400 1 1.8 210 210 1 1.0 1.5 Unit V V nA V %/V %/V % µA µA A MHz kHz mΩ mΩ µA V 0.49 ● 0.485 VLOADREG Output Voltage Load Regulation ● 300 0.1 2.8 ● ● ● 1.2 1.5 750 132 126 -1 ● 0.3 IEN EN Leakage Current 1 µA Note (3): The EUP3420 is tested in a proprietary test mode that connects FB to the output of the error amplifier. DS3420 Ver1.2 Mar. 2009 4 EUP3420 Typical Operating Characteristics DS3420 Ver1.2 Mar. 2009 5 EUP3420 Typical Operating Characteristics (continued) DS3420 Ver1.2 Mar. 2009 6 EUP3420 Typical Operating Characteristics (continued) DS3420 Ver1.2 Mar. 2009 7 EUP3420 Application Information The EUP3420 uses a slope-compensated constant frequency, current mode architecture. Both the main (P-Channel MOSFET) and synchronous (N-channel MOSFET) switches are internal. During normal operation, the EUP3420 regulates output voltage by switching at a constant frequency and then modulating the power transferred to the load each cycle using PWM comparator. The duty cycle is controlled by three weighted differential signals: the output of error amplifier, the main switch sense voltage and the slope-compensation ramp. It modulates output power by adjusting the inductor-peak current during the first half of each cycle. An N-channel, synchronous switch turns on during the second half of each cycle (off time). When the inductor current starts to reverse or when the PWM reaches the end of the oscillator period, the synchronous switch turns off. This keeps excess current from flowing backward through the inductor, from the output capacitor to GND, or through the main and synchronous switch to GND. Soft-Start The EUP3420 has an internal soft-start circuit that limits the inrush current and output voltage overshoot during startup. The soft-start is implemented with a digital circuit increasing the switch current in steps. Short-Circuit Protection As soon as the output voltage drops below 50% of the nominal output voltage, the converter switching frequency as well as the current limit is reduced to 50% of the nominal value. Input Undervoltage Lockout The undervoltage lockout circuit prevents device misoperation at low input voltages. It prevents the converter from turning on the switch or rectifier MOSFET with undefined conditions. Inductor Selection The EUP3420 typically uses a 2.2uH output inductor. Larger or smaller inductor values can be used to optimize the performance of the device for specific operation conditions. The output inductor is selected to limit the ripple current to some predetermined value, typically 20%~40% of the full load current at the maximum input voltage. Large value inductors lower ripple currents. Higher VIN or VOUT also increases the ripple current as shown in equation. A reasonable starting point for setting ripple current is ∆IL=800mA (40% of 2A). I =I × The DC current rating of the inductor should be at least equal to the maximum load current plus half the ripple current to prevent core saturation. Thus, a 2400mA rated inductor should be enough for most applications (2A+400mA). The DC-resistance of the inductor directely influences the efficiency of the converter. Therefore for better efficiency, choose a low DC-resistance inductor. CIN and COUT Selection In continuous mode, the source current of the top MOSFET is a square wave of duty cycle VOUT/VIN. The primary function of the input capacitor is to provide a low impedance loop for the edges of pulsed current drawn by the EUP3420. A low ESR input capacitor sized for the maximum RMS current must be used. The size required will vary depending on the load, output voltage and input voltage source impedance characteristics. A typical value is around 22µF. The input capacitor RMS current varies with the input voltage and the output voltage. The equation for the maximum RMS current in the input capacitor is: RMS O V V O × 1 − O V V  IN  IN      The output capacitor COUT has a strong effect on loop stability. The selection of COUT is driven by the required effective series resistance (ESR). ESR is a direct function of the volume of the capacitor; that is, physically larger capacitors have lower ESR. Once the ESR requirement for COUT has been met, the RMS current rating generally far exceeds the IRIPPLE(P-P) requirement. The output ripple ∆VOUT is determined by: ∆VOUT ≅ ∆IL  ESR +      8fCOUT   1 When choosing the input and output ceramic capacitors, choose the X5R or X7R dielectric formulations. These dielectrics have the best temperature and voltage characteristics of all the ceramics for a given value and size. ∆I L = V  VOUT1 − OUT   VIN  (f)(L)   1 DS3420 Ver1.2 Mar. 2009 8 EUP3420 Output Voltage Programming The output voltage is set by a resistive divider according to the following formula: PC Board Layout Checklist For all switching power supplies, the layout is an important step in the design especially at high peak currents and switching frequencies. If the layout is not carefully done, the regulator might show stability problems as well as EMI problems. When laying out the printed circuit board, the following guidelines should be used to ensure proper operation of the EUP3420. 1. The input capacitor CIN should connect to VIN as closely as possible. This capacitor provides the AC current to the internal power MOSFETs. 2. The power traces, consisting of the GND trace, the SW trace and the VIN trace should be kept short, direct and wide. 3. The FB pin should connect directly to the feedback resistors. The resistive divider R1/R2 must be connected between the COUT and ground. 4. Keep the switching node, SW, away from the sensitive FB node.  R2  VOUT = 0.5V 1 +   R1  Choose R1 value 50kΩ for most applications. The external resistive divider is connected to the output, allowing remote voltage sensing as shown below. Thermal Considerations To avoid the EUP3420 from exceeding the maximum junction temperature, the user will need to do a thermal analysis. The goal of the thermal analysis is to determine whether the operating conditions exceed the maximum junction temperature of the part. The temperature rise is given by: TR=(PD)(θJA) Where PD=ILOAD2 × RDS(ON) is the power dissipated by the regulator ; θJA is the thermal resistance from the junction of the die to the ambient temperature. The junction temperature, TJ, is given by: TJ=TA+TR Where TA is the ambient temperature. TJ should be below the maximum junction temperature of 125°C. DS3420 Ver1.2 Mar. 2009 9 EUP3420 Packaging Information MSOP-10 SYMBOLS A A1 D E1 E L b e D1 E2 MILLIMETERS MIN. MAX. 1.10 0.00 0.15 3.00 3.00 4.70 5.10 0.40 0.80 0.17 0.33 0.50 1.80 1.66 INCHES MIN. 0.000 0.118 0.118 0.185 0.016 0.006 0.020 0.071 0.065 0.201 0.031 0.013 MAX. 0.043 0.006 DS3420 Ver1.2 Mar. 2009 10 EUP3420 TDFN-10 SYMBOLS A A1 D1 D E1 E L b e D1 MILLIMETERS MIN. MAX. 0.70 0.80 0.00 0.05 2.50 2.90 3.10 1.70 2.90 3.10 0.30 0.50 0.18 0.30 0.50 2.40 INCHES MIN. 0.028 0.000 0.098 0.114 0.067 0.114 0.012 0.007 0.020 0.094 0.122 0.020 0.012 0.122 MAX. 0.031 0.002 DS3420 Ver1.2 Mar. 2009 11