EUP7171

2A Sink/Source Bus Termination Regulator DESCRIPTION The EUP7171 is a high performance linear regulator designed to provide power for termination of a DDR memory bus. It significantly reduces parts count, board space and overall system cost over previous switching solutions. The EUP7171 contains a high-speed operational amplifier to provide excellent response to load transients. It also has an independent power source pin (VCNTL) for achieving better output driving capability. The regulator can both sink and source up to 2A current. The output termination voltage can be tightly regulated to track 1/2 VDDQ by two external voltage divider resistors. The EUP7171, used in conjunction with series termination resistors, provides an excellent voltage source for active termination schemes of high speed transmission lines as those seen in high speed memory buses. A typical DDR memory system is seen in Figure 1. EUP7171 FEATURES Compatible with DDR-I (1.25VTT) or DDR-II (0.9VTT) SDRAM Systems. Low Quiescent Current (1.1mA) Fast Transient Response Time Capable of Sourcing and Sinking 2A Adjustable VOUT by Two External Resistors Current Limiting Protection Over-Temperature Protection High Accuracy Output Voltage at Full-Load Low External Component Count Available in SOP-8 Exposed Pad Package RoHS Compliant and 100% Lead (Pb)-Free APPLICATIONS DDR SDRAM Termination Voltage Simplified System Diagram Figure1. DS7171 Ver1.0 Mar. 2005 1 EUP7171 Pin Configurations Part Number Pin Configurations (TOP VIEW) EUP7171 (Plastic SOP-8) Pin Description PIN 1 2 3 4 6 5,7,8 SYMBOL VIN GND VREF VOUT VCNTL NC DESCRIPTION Power Input pin Ground Reference voltage input and chip enable (Chip enable when REFEN > 0.8V) Output voltage for regulation terminator voltage Gate driver voltage NC Typical Application Circuit DS7171 Ver1.0 Mar. 2005 2 EUP7171 Ordering Information Order Number EUP7171DIT1 EUP7171DIR1 Package Type SOP-8 SOP-8 Marking xxxx EUP7171 xxxx EUP7171 Operating Temperature range -40°C to 125°C -40°C to 125°C EUP7171 □□□□ Lead Free Code 1: Lead Free 0: Lead Packing T: Tube R: Tape & Reel Operating temperature range I: Industry Standard Package Type D: SOP DS7171 Ver1.0 Mar. 2005 3 EUP7171 Absolute Maximum Ratings Input voltage - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Power dissipation - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ESD rating - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -Maximum junction temperature - - - - - - - - - - - - - - - - - - - - - - - - - Storage temperature range - - - - - - - - - - - - - - - - - - - - - - - - - - - - Lead temperature (soldering , 5 sec) - - - - - - - - - - - - - - - - - - - - - Package thermal resistance SOP-8 (FD) , θjA - - - - - - - - - - - - - - - - - 6V Internal limiting 2KV 150 °C -65°C to150°C 260 °C 42.3 °C/W Electrical Characteristics (Limits in standard typeface are for TA=25 °C, unless otherwise specified: VIN=2.5V/1.8V, VCNTL=3.3V, VREF=1.25V/0.9V, COUT=10µf (Ceramic) Symbol VOS Parameter Output Offset Voltage Conditions IOUT = 0A, (Note1) IL : 0 →2A(DDRI)/1.5(DDRII) Min -20 Typ 0 Max 20 Units mV ΔVLOAD VIN VCNTL IVCNTL ISHDN Load Regulation IL : 0 → -2A(DDRI)/-1.5(DDRII) Input Voltage Range (DDR I / DDR I I ) Operating Current of VCNTL Current in Shutdown mode Keep VCNTL ≥ VIN on operation power on and power off sequences IL = 0A VREF ＜ 0.2V -20 0 20 mV ----- 2.5/1.8 3.3 1.4 60 -V 5.5 2 110 mA µA Short Circuit Protection ILIMIT Current Limit Thermal Shutdown Temperature Thermal Shutdown Hysteresis 2.2 --A Over Temperature Protection TSD TSD _HYS VIH -Guaranteed by design -157 40 --°C °C Shutdown function VIL Shutdown Threshold Output = High Output = Low 0.8 -- --- -0.2 V Note 1: VOS offset is the voltage measurement defined as VOUT subtracted from VREF. DS7171 Ver1.0 Mar. 2005 4 EUP7171 Typical Operating Characteristics DS7171 Ver1.0 Mar. 2005 5 EUP7171 DS7171 Ver1.0 Mar. 2005 6 EUP7171 DS7171 Ver1.0 Mar. 2005 7 EUP7171 Function Block Diagram Pin Functions VCNTL and VIN VCNTL and VIN are the input supply pins for the EUP7171. VIN provides the rail voltage for VOUT generation. VCNTL is used to supply the internal control circuitry. The limitation on input voltage selection is that VIN must be equal to or lower than VCNTL. For DDR I application, a separation connection of VIN and VCNTL to 2.5V and 3.3V respectively can achieve better output drive capability. VREF REFEN is an external reference input for the EUP7171. For SSTL-2 applications, VREF should be a 1.25V that the regulator can trace for termination voltage VOUT. It is recommended to place a 0.01uF to 0.1uF bypass capacitor at close to the VREF pin. An additional function included in the VREF is an active low shutdown. When VREF is pulled low the VOUT output will tri-state providing a high impedance output. A power savings advantage can be obtained in this mode through lower quiescent current. VOUT VOUT provides a regulated output for termination bus usage. It is capable of sinking and sourcing current while regulating the output voltage precisely at REFEN. The regulator is designed to handle continue current up to +/-2A with fast transient response. If the application requires high load current with low voltage dropped, a large output capacitor with lower ESR(Equivalent Series DS7171 Ver1.0 Mar. 2005 Resistance) connected at VOUT is recommended. Thermal dissipation should be considered if the large current continues with long duration time. If the junction temperature exceeds the thermal shutdown point, the VOUT will turn to tri-state. Component Selection In order to obtain the best performance from the EUP7171, using lower ESR capacitor is necessary to Cin and Cout for high current load. The ESR of the output bulk capacitor primarily affects the capability to deliver a current surge within a specified delta voltage drop (ΔV) at VOUT. With a given capacitor ESR, the ΔV drop will be proportional to the load current, and a step in voltage drop will occur. (ΔVstep-peak = ESR * IL), the SSTL-2 spec indicates a maximum delta voltage drop of 40mV. A very good, low ESR electrolytic capacitor of no less than 470uF should be placed next to the terminator, which should be placed as possible to memory array. It might be possible to reduce the total capacitance, provided the performance remains stable. Examine the behavior of the VOUT bus carefully when the system is operating and verify that deviations in the bus voltage do not exceed the DDR specification (+/-40 mV). REFEN input is needed a high-frequency decoupling capacitor (CSS). A 0.1uf ceramic capacitor should be placed as possible to REFEN. 8 EUP7171 PCB Layout Considerations The EUP7171 regulator is packaged in plastic SOP-8 package. This small footprint package is unable to convectively dissipate at high current levels. The junction temperature should be kept well away from the thermal shutdown temperature in normal operation. To do this, care should be taken to derate the part dependent on several variables: the thickness of copper on PCB; the area of top side copper used and the airflow. Since multiple GND pins on the SOP-8 package are internally connected, the lowest thermal resistance will result if these pins are tightly connected on larger ground traces and more copper on top side of the printed circuit board. If the large ground trace around the IC is unavailable on top, numerous vias from the ground connection to the internal ground plane will help. The vias should be small enough to retain solder when the board is wavesoldered. Additional improvements can be achieved with a constant airflow across the package. Test Circuit Figure 2. Load transient (+2A ~ –2A) test circuit DS7171 Ver1.0 Mar. 2005 9 EUP7171 Packaging Information X Y Z Standard Solder Map Bottom Ues as much copper area as possible EXPOSED PAD Symbols A B C D E H F L1 L2 M N A1 B1 Dimension in Millimeters Min. Max. 4.80 5.00 5.80 6.20 3.80 4.00 1.194 1.346 1.45 1.55 0.00 0.10 0.33 0.51 0.19 0.25 0.40 1.27 0° 8° 40° 50° 2.6 2.8 2.4 2.6 Dimension in Inches Min. Max. 0.189 0.197 0.228 0.244 0.150 0.157 0.047 0.053 0.057 0.061 0.000 0.004 0.013 0.020 0.007 0.010 0.016 0.050 0° 8° 40° 50° 0.102 0.110 0.095 0.102 8 – Lead SOP(FD) Plastic Package DS7171 Ver1.0 Mar. 2005 10