Photolink- Fiber Optic Receiver
EAPLRAA4
Features
• High PD sensitivity optimized for red light
• Data : NRZ signal
• Low power consumption for extended battery life
• Built-in threshold control for improved noise Margin
• The product itself will remain within RoHS compliant version
• Receiver sensitivity: up to –27dBm (Min. for 16Mbps)
Description
The optical receiver is packaged with custom optic data link interface, integrated
on a proprietary CMOS PDIC process.
The unit functions by converting optical signals into electric ones.
The unit is operated at 2.4 ~ 5.5 V and the signal output interface is TTL
compatible with high performance at low power consumption.
Applications
• Digital Optical Data-Link
• Dolby AC-3 Digital Audio Interface
1
Copyright © 2010, Everlight Americas Inc. All Rights Reserved. Release Date : 05.30.2013. Issue No: 1
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DATASHEET
Photolink- Fiber Optic Receiver
EAPLRAA4
Absolute Maximum Ratings (Ta=25℃)
Parameter
Symbol
Rating
Unit
Supply Voltage
Vcc
-0.5 ~ +5.5
V
Output Voltage
Vout
Vcc +0.3
V
Storage Temperature
Tstg
-40 to 85
ºC
Operating Temperature
Topr
-20 to 70
ºC
Soldering Temperature
Tsol
260*
ºC
Human Body Model ESD
HBM
2000
V
Machine Model ESD
MM
100
V
Notes: Soldering time≦10 seconds
Recommended Operating Conditions
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Supply Voltage
Vcc
-
2.4
3.0
5.50
V
Electro-Optical Characteristics (Ta=25℃)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Peak sensitivity wavelength
p
-
-
650
-
nm
Transmission Distance
d
*1
0.2
--
5
m
Maximum receiver power
Pc,max
Refer to Fig.1
-
-
-14
dBm
Minimum receiver power
Pc,min
Refer to Fig.1
-27
-
-
dBm
Icc
Refer to Fig.2
-
4
12
mA
High level output voltage
VOH
Refer to Fig.3
2.1
2.5
-
V
Low level output voltage
VOL
Refer to Fig.3
-
0.2
0.4
V
Rise time
tr
Refer to Fig.3
-
10
20
ns
Fall time
tf
Refer to Fig.3
-
10
20
ns
Propagation delay Low to High
tPLH
Refer to Fig.3
-
-
120
ns
Propagation delay High to Low
tPHL
Refer to Fig.3
-
-
120
ns
Pulse Width Distortion
tw
Refer to Fig.3
-25
-
+25
ns
tj
Refer to Fig.3, Pc=-14dBm
-
1
15
ns
Jitter
Refer to Fig.3, Pc=-27dBm
-
5
20
ns
NRZ signal
0.1
-
16
Mb/s
Dissipation current
Transfer rate
2
T
Copyright © 2010, Everlight Americas Inc. All Rights Reserved. Release Date : 05.30.2013. Issue No: 1
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DATASHEET
Photolink- Fiber Optic Receiver
EAPLRAA4
Measuring Method
*Fig.1 Measuring Method of Maximum and Minimum Input Power that Receiver Unit Need
Control Circuit
Standard plastic optic fiber cable
Transmitter
EAPLRAA4 Receiver
PLR135 Receiver
Unit Unit
Optical Power Meter
*Fig.2 Measuring Method of Dissipation Current
Standard plastic optic fiber cable
EAPLRAA4 Receiver
Standard Transmitter Unit
Vin
Vcc
PLR135 Receiver
Unit
Unit
GND
A
16 Mbps NRZ "0101" successive signal input
3
Vout
0.1uF
47uH
Signal
Input
GND
Vcc
Copyright © 2010, Everlight Americas Inc. All Rights Reserved. Release Date : 05.30.2013. Issue No: 1
3V
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DATASHEET
Photolink- Fiber Optic Receiver
EAPLRAA4
*Fig.3 Measuring Method of Output Voltage, Pulse and Jitter
Standard plastic optic fiber cable
EAPLRAA4 Receiver
Standard Transmitter Unit
Vin
Vcc
PLR135 Receiver
Unit
Unit
GND
GND
Vcc
0.1uF
47uH
Signal
Input
Vout
A
3V
16 Mbps NRZ "0101" successive signal input
TPHL
TPLH
Input
CH1
50%
CH2
Output
50%
tj1
tj2
tw = TPHL-TPLH
Application Circuit
(1) General application circuit for Vcc=3V
Receiver Unit
Receiver Unit
C1
C1
Vcc
(2) General application circuit for Vcc=5V
GND
L2
Vout
C1:0.1uF
3V
Vcc
C2
GND
L2
L2:47uH
5V
Vout
C1:0.1uF
C2:30pF (Suggestion)
L2:47uH
Note: For having good coupling, the C1,C2 capacitor must be placed within 7mm
4
Copyright © 2010, Everlight Americas Inc. All Rights Reserved. Release Date : 05.30.2013. Issue No: 1
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DATASHEET
Photolink- Fiber Optic Receiver
EAPLRAA4
Typical Electro-Optical Characteristics Curves
*Fig.4 Power supply voltage vs. Minimum receiver
*Fig.5
power
Operating Transfer Rate
16Mbps
25Mbps
-32
Operating Voltage Vcc=3.3V
Optical Input Sensitivity (dBm)
Optical Input Sensitivity (dBm)
-30
-28
-26
-24
-22
-20
2.0
2.5
3.0
3.5
Transfer rate vs. Minimum receiver power
4.0
4.5
5.0
5.5
6.0
-30
-28
-26
-24
-22
-20
-18
0
5
Operating Voltage (V)
Note: Before using the
rate.
5
10
15
20
25
Transfer Rate (Mbps)
EAPLRAA4 device, please confirm the minimum sensitivity at different operating voltage and transmission
Copyright © 2010, Everlight Americas Inc. All Rights Reserved. Release Date : 05.30.2013. Issue No: 1
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DATASHEET
Photolink- Fiber Optic Receiver
EAPLRAA4
Package Dimension
Note: Tolerances unless mentioned ±0.3mm. Unit = mm
PCB Layout for Electrical Circuit
Note: PCB Tolerances:1.6mm. Unit = mm
6
Copyright © 2010, Everlight Americas Inc. All Rights Reserved. Release Date : 05.30.2013. Issue No: 1
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DATASHEET
Photolink- Fiber Optic Receiver
EAPLRAA4
Moisture Resistant Packing Materials
Label Explanation
‧CPN: Customer’s Product Number
‧P/N: Product Number
‧QTY: Packing Quantity
‧CAT: Luminous Intensity Rank
‧HUE: Dom. Wavelength Rank
‧REF: Forward Voltage Rank
‧LOT No: Lot Number
‧X: Month
‧Reference: Identify Label Number
Packing Quantity Specification
1. 60 pcs/tube
2. 36 tube/box
3. 4 boxes/carton
7
Copyright © 2010, Everlight Americas Inc. All Rights Reserved. Release Date : 05.30.2013. Issue No: 1
www.everlightamericas .com
DATASHEET
Photolink- Fiber Optic Receiver
EAPLRAA4
Notes
1.
2.
3.
Above specification may be changed without notice. EVERLIGHT Americas will reserve authority on material
change for above specification.
.When using this product, please observe the absolute maximum ratings and the instructions for using outlined
in these specification sheets. EVERLIGHT Americas assumes no responsibility for any damage resulting from
use of the product which does not comply with the absolute maximum ratings and the instructions included in
these specification sheets.
These specification sheets include materials protected under copyright of EVERLIGHT Americas corporation.
Please don’t reproduce or cause anyone to reproduce them without EVERLIGHT Americas’s consent.
Application Notes: EAPLRAA4 PCB layout for motherboard integration
To achieve better jitter and low input optical power performances, several PCB layout guidelines must be followed.
These guidelines ensure the most reliable EAPLRAA4 POF performance for the motherboard integration. Failed to
implement these PCB guidelines may affect the EAPLRAA4 jitter and low input power performances.
8
1.
Careful decoupling of the power supplies is very important. Place a 0.1uf surface mount (size 805 or smaller)
capacitor as close as (less than 2cm) to the POF Vdd and Gnd leads. The 0.1uf act as a low impedance path to
ground for any stray high frequency transient noises.
2.
To reduce the digital noises form the digital IC on the motherboard, the planar capacitance formed by an
isolated Vcc and Gnd planes is critical. The POF device must be mounted directly on these two planes to
reduce the lead parasitic inductance.
3.
The isolated Vdd and Gnd planes must be connected to the main Vcc and Gnd (digital) planes at a single point
using ferrite beads. The beads are used to block the high frequency noises from the digital planes while still
allowing the DC connections between the planes
Copyright © 2010, Everlight Americas Inc. All Rights Reserved. Release Date : 05.30.2013. Issue No: 1
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