MP7528KP

MP7528 CMOS Dual Buffered Multiplying 8-Bit Digital-to-Analog Converter FEATURES • • • • • • On-Chip Latches for Both DACs +5 V to +15 V Operation DACs Matched to 1% Four Quadrant Multiplication 15 V CMOS Compatible See MP7529A or MP7529B for Improved Performance APPLICATIONS • • • • • Microprocessor Controlled Gain Circuits Microprocessor Controlled Attenuator Circuits Microprocessor Controlled Function Generation Precision AGC Circuits Bus Structured Instruments GENERAL DESCRIPTION The MP7528 is a dual 8-bit digital/analog converter designed using EXAR’s proven decoded DAC architecture. It features excellent DAC-to-DAC matching and guaranteed monotonicity. Separate on-chip latches are provided for each DAC to allow easy microprocessor interface. Data is transferred into either of the two DAC data latches via a common 8-bit TTL/CMOS compatible input port. Control input DACA/DACB determines which DAC is to be loaded. The MP7528’s load cycle is similar to the write cycle of a random access memory and the device is bus compatible with most 8-bit microprocessors. The device operates from a +5V to +15V power supply with only 2 mA of current (maximum). Both DACs offer excellent four quadrant multiplication characteristics with a separate reference input and feedback resistor for each DAC. SIMPLIFIED BLOCK AND TIMING DIAGRAM VDD VREFA DB7-DB0 DACA/DACB CS WR RFBB D Q LATCH B E DAC B IOUTB AGND OUT RFBA DB7-DB0 DACA/DACB D Q LATCH A E DAC A IOUTA CS WR DGND VREFB Rev. 2.00 1 MP7528 ORDERING INFORMATION Package Type Plastic Dip Plastic Dip Plastic Dip SOIC SOIC SOIC PLCC PLCC PLCC Ceramic Dip Ceramic Dip Ceramic Dip Ceramic Dip Ceramic Dip Temperature Range –40 to +85°C –40 to +85°C –40 to +85°C –40 to +85°C –40 to +85°C –40 to +85°C –40 to +85°C –40 to +85°C –40 to +85°C –40 to +85°C –40 to +85°C –40 to +85°C –55 to +125°C –55 to +125°C Part No. MP7528JN MP7528KN MP7528LN MP7528JS MP7528KS MP7528LS MP7528JP MP7528KP MP7528LP MP7528AD MP7528BD MP7528CD MP7528SD* MP7528TD* INL (LSB) +1 +1/2 +1/4 +1 +1/2 +1/4 +1 +1/2 +1/4 +1 +1/2 +1/4 +1 +1/2 DNL (LSB) +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 Gain Error (LSB) +6 +4 +3 +6 +4 +3 +6 +4 +3 +6 +4 +3 +6 +4 *Contact factory for non-compliant military processing PIN CONFIGURATIONS See Packaging Section for Package Dimensions AGND IOUTA RFBA VREFA DGND DACA/DACB (MSB) DB7 DB6 DB5 DB4 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 IOUTB RFBB VREFB VDD WR CS DB0 (LSB) DB1 DB2 DB3 1 2 3 4 5 6 7 8 9 10 20 19 18 See Pin Out at Left 17 16 15 14 13 12 11 20 Pin CDIP, PDIP (0.300”) D20, N20 20 Pin SOIC (Jedec, 0.300”) S20 Rev. 2.00 2 MP7528 PIN CONFIGURATIONS (CONT’D) IOUTB IOUTA AGND RFBA RFBB 3 2 1 20 19 VREFA DGND DACA/DACB (MSB) DB7 DB6 4 5 6 7 8 18 17 16 15 14 VREFB VDD WR CS DB0 (LSB) 9 10 11 12 13 DB5 DB3 DB1 DB4 DB2 20 Pin PLCC P20 PIN OUT DEFINITIONS PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 NAME AGND IOUTA RFBA VREFA DGND DAC A/ DAC B DB7 (MSB) DB6 DB5 DB4 DB3 DB2 DB1 DB0 (LSB) CS WR VDD VREFB RFBB IOUTB DESCRIPTION Analog Ground Current Out DAC A Feedback Resistor for DAC A Reference Input for DAC A Digital Ground DAC Select Data Input Bit 7 Data Input Bit 6 Data Input Bit 5 Data Input Bit 4 Data Input Bit 3 Data Input Bit 2 Data Input Bit 1 Data Input Bit 0 Chip Select Write Power Supply Reference Input for DAC B Feedback Resistor for DAC B Current Out DAC B Rev. 2.00 3 MP7528 ELECTRICAL CHARACTERISTICS (VDD = + 5 V, VREF = +10 V unless otherwise noted) Parameter STATIC PERFORMANCE1 Resolution (All Grades) Integral Non-Linearity (Relative Accuracy) J, A, S K, B, T L, C Monotonicity Differential Non-Linearity J, A, S K, B, T L, C Gain Error J, A, S K, B, T L, C Gain Temperature Coefficient2 Power Supply Rejection Ratio DNL +1 +1 LSB N INL +1 +1/2 +1/4 +1 +1/2 +1/4 Guaranteed over temp All grades monotonic over full temperature range. 8 8 LSB Bits End Point Linearity Spec. Symbol Min 25°C Typ Max Tmin to Tmax Min Max Units Test Conditions/Comments GE +4 +2 +1 TCGE PSRR +200 +6 +4 +3 +70 +400 LSB Using Internal RFB Digital Inputs = VINH ppm/°C ppm/% ∆Gain/∆Temperature |∆Gain/∆VDD| ∆VDD = + 5% Digital Inputs = VINH Digital Inputs = VINL Digital Inputs = VINH TC = –300 ppm/°C max. 11 kΩ typical Output Leakage Current (Pin 2) Output Leakage Current (Pin 20) Input Resistance IOUT1 IOUT2 VREFA VREFB 8 8 +50nA +50nA 15 15 +1 8 8 +400nA +400nA 15 15 +1 nA nA kΩ kΩ % Input Resistance Matching DYNAMIC PERFORMANCE2 Harmonic Distortion Digital Crosstalk Channel-to-Channel Isolation AC Feedthrough at IOUT1 Glitch Energy Propagation Delay THD Q CCI FT Egl tPD –85 30 –77 –70 160 220 RL=100Ω, CL=13pF dB nVs dB dB nVs ns VIN = 6VRMS @ 1 KHz Measured for code transition ZS to FSS VREF = 10kHz, 20 Vp-p, sinewave ZS to FS Input Change From digital input to 90% of final analog output current –65 270 Rev. 2.00 4 MP7528 ELECTRICAL CHARACTERISTICS (CONT’D) Parameter DIGITAL INPUTS3 Logical “1” Voltage Logical “0” Voltage Input Leakage Current Input Capacitance2 Data Control ANALOG OUTPUTS2 Output Capacitance COUTA COUTA COUTB COUTB POWER SUPPLY5 Functional Voltage Range2 Supply Current VDD IDD 4.5 15.75 2 2 4.5 15.75 2 2 V mA mA 120 50 120 50 120 50 120 50 pF pF pF pF DAC Inputs all 1’s DAC Inputs all 0’s DAC Inputs all 1’s DAC Inputs all 0’s VIH VIL ILKG CIN CIN 2.4 0.8 +1 10 15 2.4 0.8 +10 10 15 V V µA pF pF Symbol Min 25°C Typ Max Tmin to Tmax Min Max Units Test Conditions/Comments All digital inputs = 0 V or all = 5 V All digital inputs = VIL or all = VIH SWITCHING CHARACTERISTICS4 Chip Select to Write Set-Up Time Chip Select to Write Hold Time DAC Select to Write Set-Up Time DAC Select to Write Hold Time Data Valid to Write Set-Up Time Data Valid to Write Hold Time Write Pulse Width tCS tCH tAS tAH tDS tDH tWR 200 20 200 20 110 0 180 230 30 230 30 130 0 200 ns ns ns ns ns ns NOTES: 1 2 3 4 5 Full Scale Range (FSR) is 10V for unipolar mode. Guaranteed but not production tested. Digital input levels should not go below ground or exceed the positive supply voltage, otherwise damage may occur. See timing diagram. Specified values guarantee functionality. Refer to other parameters for accuracy. Specifications are subject to change without notice Rev. 2.00 5 MP7528 ELECTRICAL CHARACTERISTICS (VDD = + 15 V, VREF = +10 V unless otherwise noted) 25°C Typ Tmin to Tmax Min Max Parameter STATIC PERFORMANCE1 Resolution (All Grades) Integral Non-Linearity (Relative Accuracy) J, A, S K, B, T L, C Monotonicity Differential Non-Linearity J, A, S K, B, T L, C Gain Error J, A, S K, B, T L, C Gain Temperature Coefficient2 Power Supply Rejection Ratio Symbol Min Max Units Test Conditions/Comments N INL 8 8 LSB +1 +1/2 +1/4 +1 +1/2 +1/4 Bits End Point Linearity Spec. Guaranteed over temp DNL +1 +1 +1 GE +4 +2 +1 TCGE PSRR +100 +5 +3 +1 +35 +200 ppm/°C ppm/% +1 +1 +1 LSB LSB All grades monotonic over full temperature range. Using Internal RFB Digital Inputs = VINH ∆Gain/∆Temperature |∆Gain/∆VDD| ∆VDD = + 5% Digital Inputs = VINH Digital Inputs = VINL Digital Inputs = VINH TC = –300 ppm/°C max. 11 kΩ typical Output Leakage Current (Pin 2) Output Leakage Current (Pin 20) Input Resistance IOUT1 IOUT2 VREFA VREFB 8 8 +50nA +50nA 15 15 +1 8 8 +200nA +200nA 15 15 +1 nA nA kΩ kΩ % Input Resistance Matching DYNAMIC PERFORMANCE2 Harmonic Distortion Digital Crosstalk Channel-to-Channel Isolation AC Feedthrough at IOUT1 Glitch Energy Propagation Delay THD Q CCI FT Egl tPD –85 60 –77 –70 440 RL=100Ω, CL=13pF dB nVs dB dB nVs ns VIN = 6VRMS @ 1 KHz Measured for code transition ZS to FS VREF = 10kHz, 20 Vp-p, sinewave ZS to FS Input Change From 50% of digital input to 90% of final analog output current –65 80 100 DIGITAL INPUTS3 Logical “1” Voltage Logical “0” Voltage Input Leakage Current Input Capacitance2 Data Control VIH VIL IILKG CIN CIN 13.5 1.5 +1 10 15 13.5 1.5 +10 10 15 V V µA pF pF Rev. 2.00 6 MP7528 ELECTRICAL CHARACTERISTICS (CONT’D) Parameter ANALOG OUTPUTS2 Output Capacitance COUTA COUTA COUTB COUTB POWER SUPPLY5 Functional Voltage Range2 Supply Current VDD IDD 4.5 15.75 2 2 4.5 15.75 2 2 V mA mA 120 50 120 50 120 50 120 50 pF pF pF pF DAC Inputs all 1’s DAC Inputs all 0’s DAC Inputs all 1’s DAC Inputs all 0’s Symbol Min 25°C Typ Max Tmin to Tmax Min Max Units Test Conditions/Comments All digital inputs = 0 V or all = 5 V All digital inputs = VIL or all = VIH SWITCHING CHARACTERISTICS Chip Select to Write Set-Up Time Chip Select to Write Hold Time DAC Select to Write Set-Up Time DAC Select to Write Hold Time Data Valid to Write Set-Up Time Data Valid to Write Hold Time Write Pulse Width NOTES: 1 2 3 4 5 tCS tCH tAS tAH tDS tDH tWR 60 10 60 10 30 0 60 80 15 80 15 40 0 80 ns ns ns ns ns ns ns Full Scale Range (FSR) is 10V for unipolar mode. Guaranteed but not production tested. Digital input levels should not go below ground or exceed the positive supply voltage, otherwise damage may occur. See timing diagram. Specified values guarantee functionality. Refer to other parameters for accuracy. Specifications are subject to change without notice ABSOLUTE MAXIMUM RATINGS (TA = +25°C unless otherwise noted)1, 2, 3 VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +17 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1 V (Functionality Guaranteed +0.5 V) Digital Input Voltage to DGND . . . . . . . . . . . . . –0.5 V, +17 V VPIN2, VPIN20 to GND . . . . . . . . . . . . . . . . . . . . –0.5 V, +17 V VREFA, VREFB to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +25 VRFBA, VRFBB to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . +25 V Storage Temperature . . . . . . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 10 secs.) . . . . . . . . . +300°C Package Power Dissipation Rating to 75°C CDIP, PDIP, SOIC, PLCC . . . . . . . . . . . . . . . . . . 900mW Derates above 75°C . . . . . . . . . . . . . . . . . . . . . 12mW/°C NOTES: 1 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2 Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. 3 GND refers to AGND and DGND. Rev. 2.00 7 MP7528 INTERFACE LOGIC INFORMATION DAC Selection: Both DAC latches share a common 8-bit input port. The control input DACA/DACB selects which DAC can accept data from the input port. Mode Selection: Inputs CS and WR control the operating mode of the selected DAC. See Mode Selection Table below: Write Mode: When CS and WR are both low the selected DAC is in the write mode. The input data latches of the selected DAC are transparent and its analog output responds to activity on DB0-DB7. Hold Mode: The selected DAC latch retains the data which was present on DB0-DB7 just prior to CS and WR assuming a high state. Both analog outputs remain at the values corresponding to the data in their respective latches. DAC A/DAC B L H X X CS L L H X WR L L X H DAC A Write Hold Hold Hold DAC B Hold Write Hold Hold L = LOW state, H = HIGH state, X = Don’t care state Table 1. Mode Selection Table tCS CS tCH VDD 0 DAC A/DAC B tAS tAH VDD 0 tWR WR tDS DATA IN (DB0-DB7) VIH VIL VIH VIL DATA IN STABLE tDH VDD 0 VDD 0 NOTES: 1. All input signal rise and fall times measured from 10% to 90% of VDD. VDD = +5 V, tr = tf = 20 ns VDD = +15 V, tr = tf = 40 ns 2. Timing measurement reference level is VIH + VIL / 2 Figure 1. Write Cycle Timing Diagram Rev. 2.00 8 MP7528 MICROPROCESSOR INTERFACE A0-A15 A* VMA Address Decode Logic A+1** DACA/DACB CS Address Decode Logic A+1** MP7528 DAC B Address Bus A8-A15 A* DACA/DACB CS DAC A Address Bus DAC A CPU 6800 φ2 WR DB0 DB7 MP7528 CPU 8085 WR ALE WR Latch 8212 DB0 DB7 DAC B D0–D7 Data Bus AD0–AD7 ADDR/Data Bus Analog circuitry has been omitted for clarity *A = Decoded 7528 DAC A Address **A + 1 = Decoded 7528 DAC B Address Analog circuitry has been omitted for clarity *A = Decoded 7528 DAC A Address **A + 1 = Decoded 7528 DAC B Address NOTE: 8085 instruction SHLD (store H & L direct) can update both DACS with data from H and L registers Figure 2. MP7528 Dual DAC to 6800 CPU Interface Figure 3. MP7528 Dual DAC to 8085 CPU Interface PERFORMANCE CHARACTERISTICS Graph 1. Relative Accuracy vs. Digital Code 5V Rev. 2.00 9 Graph 2. Relative Accuracy vs. Digital Code 15 V MP7528 This page left blank Rev. 2.00 10 MP7528 20 LEAD CERAMIC DUAL-IN-LINE (300 MIL CDIP) D20 S1 See Note 1 20 S 11 1 10 E1 D Base Plane Seating Plane L b e b1 c L1 Q A E α INCHES SYMBOL A b b1 c D E E1 e L L1 Q S S1 MIN –– 0.014 0.038 0.008 –– 0.220 0.290 MAX 0.200 0.023 0.065 0.015 1.060 0.310 0.320 MILLIMETERS MIN –– 0.356 0.965 0.203 –– 5.59 7.37 MAX 5.08 0.584 1.65 0.381 26.92 7.87 8.13 NOTES –– –– 2 –– 4 4 7 5 –– –– 3 6 6 –– NOTES 1. Index area; a notch or a lead one identification mark is located adjacent to lead one and is within the shaded area shown. 2. The minimum limit for dimension b1 may be 0.023 (0.58 mm) for all four corner leads only. 3. Dimension Q shall be measured from the seating plane to the base plane. 4. This dimension allows for off-center lid, meniscus and glass overrun. 5. The basic lead spacing is 0.100 inch (2.54 mm) between centerlines. 6. Applies to all four corners. 7. This is measured to outside of lead, not center. 0.100 BSC 0.125 0.150 0.015 –– 0.005 0° 0.200 –– 0.070 0.080 –– 15° 2.54 BSC 3.18 3.81 0.381 –– 0.13 0° 5.08 –– 1.78 2.03 –– 15° α Rev. 2.00 11 MP7528 20 LEAD PLASTIC DUAL-IN-LINE (300 MIL PDIP) N20 S 20 1 Q1 D 11 10 E1 E A1 Seating Plane A L B e B1 α C INCHES SYMBOL A A1 B B1 (1) C D E E1 e L MIN –– 0.015 0.014 0.038 0.008 0.945 0.295 0.220 MAX 0.200 –– 0.023 0.065 0.015 1.060 0.325 0.310 MILLIMETERS MIN –– 0.38 0.356 0.965 0.203 24.0 7.49 5.59 MAX 5.08 –– 0.584 1.65 0.381 26.92 8.26 7.87 0.100 BSC 0.115 0° 0.055 0.040 (1) 0.150 15° 0.070 0.080 2.54 BSC 2.92 0° 1.40 1.02 3.81 15° 1.78 2.03 α Q1 S Note: The minimum limit for dimensions B1 may be 0.023” (0.58 mm) for all four corner leads only. Rev. 2.00 12 MP7528 20 LEAD SMALL OUTLINE (300 MIL JEDEC SOIC) S20 D 20 11 E H 10 h x 45° C Seating Plane e B A1 L A α INCHES SYMBOL A A1 B C D E e H h L MIN 0.097 0.0050 0.014 0.0091 0.500 0.292 MAX 0.104 0.0115 0.019 0.0125 0.510 0.299 MILLIMETERS MIN 2.464 0.127 0.356 0.231 12.70 7.42 MAX 2.642 0.292 0.483 0.318 12.95 7.59 0.050 BSC 0.400 0.010 0.016 0° 0.410 0.016 0.035 8° 1.27 BSC 10.16 0.254 0.406 0° 10.41 0.406 0.889 8° α Rev. 2.00 13 MP7528 Notes Rev. 2.00 14 MP7528 Notes Rev. 2.00 15 MP7528 NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contains here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright EXAR Corporation Datasheet April 1995 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. Rev. 2.00 16