MP7543

MP7543 5 V CMOS Serial Input 12-Bit Digital-to-Analog Converter FEATURES • • • • • • • • • • • 12-Bit DAC with Serial Digital Input Interface Nonlinearity +1/2 LSB from Tmin to Tmax Lowest Sensitivity to Amplifier VOS Low Output Capacitance Full 4-Quadrant Multiplication Latch-Up Free Asynchronous CLEAR Input Serial Load On Positive or Negative Strobes +5 V Supply Operation 3 V Version: MP75L43 4-Bit Parallel Version: MP7542 BENEFITS • Compatible with Serial Addressing Systems GENERAL DESCRIPTION The MP7543 is a precision, 12-bit CMOS 4-quadrant multiplying Digital-to-Analog Converter designed for serial interface applications. The MP7543 consists of two 12-bit registers, control logic and a 12-bit multiplying D/A converter. The input register (register A) is a 12-bit serial-in parallel-out shift register. Serial data at the SR1 pin is clocked into Register A on the leading or trailing edge (user selected) of the strobe input, with the MSB loaded first. Register B is a 12-bit parallel-in parallel-out register that follows register A. The contents of register A are loaded into register B under control of the Load inputs. A CLEAR input is provided for the asynchronous resetting of register B to all 0’s. The MP7543 is manufactured using an advanced thin film monolithic CMOS fabrication process. A unique decoding technique is utilized yielding excellent accuracy and stability. 12-bit linearity is achieved without laser trimming. The MP7543 reduces the additional linearity errors due to output amplifier offset to only 330 µV per millivolt of offset - half the value of a standard R-2R CMOS DAC design approach. SIMPLIFIED BLOCK DIAGRAM RFB VREF 12-Bit D/A Converter IOUT1 IOUT2 AGND CLR LD1 LD2 STB1 STB4 STB3 STB2 VDD DGND DAC Register B Load Register A 12-Bit Shift Register SRI Rev. 2.00 1 MP7543 ORDERING INFORMATION Package Type Plastic Dip Plastic Dip SOIC SOIC PLCC PLCC Ceramic Dip Ceramic Dip Ceramic Dip Ceramic Dip Temperature Range –40 to +85°C –40 to +85°C –40 to +85°C –40 to +85°C –40 to +85°C –40 to +85°C –40 to +85°C –40 to +85°C –55 to +125°C –55 to +125°C Part No. MP7543JN MP7543KN MP7543JS MP7543KS MP7543JP MP7543KP MP7543AD MP7543BD MP7543SD* MP7543TD* INL (LSB) +1 +1/2 +1 +1/2 +1 +1/2 +1 +1/2 +1 +1/2 DNL (LSB) +2 +1 +2 +1 +2 +1 +2 +1 +2 +1 Gain Error (LSB) +14.5 +14.5 +14.5 +14.5 +14.5 +14.5 +14.5 +14.5 +14.5 +14.5 *Contact factory for non-compliant military processing PIN CONFIGURATIONS See Packaging Section for Package Dimensions RFB IOUT1 N/C IOUT2 VREF 3 2 1 20 19 1 2 3 4 5 6 7 8 16 15 IOUT1 IOUT2 AGND STB1 LD1 N/C SRI STB2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 RFB VREF VDD CLR DGND STB4 STB3 LD2 AGND STB1 N/C LD1 N/C 4 5 6 7 8 18 17 16 15 14 VDD CLR N/C DGND STB4 See Pin Out at Left 14 13 12 11 10 9 9 10 11 12 13 SRI N/C STB3 STB2 LD2 16 Pin CDIP, PDIP (0.300”) D16, N16 16 Pin SOIC (Jedec, 0.300”) S16 20 Pin PLCC P20 Rev. 2.00 2 MP7543 PIN OUT DEFINITIONS PDIP, CDIP and SOIC PIN NO. 1 2 3 4 5 NAME IOUT1 IOUT2 AGND STB1 LD1 DESCRIPTION DAC current output pin. Normally terminated at op amp virtual ground. DAC current output pin. Normally terminated at AGND. Analog Ground. Register A Strobe 1 input, See Table 1. DAC Register B Load 1 input. When LD1 and LD2 go low the contents of Register A are loaded into DAC Register B. No Connection. Serial Data Input to Register A. Register A Strobe 2 input, See Table 1. DAC Register B Load 2 input. When LD1 and LD2 go low the contents of Register A are loaded into DAC Register B. Register A Strobe 3 input, See Table 1. Register A Strobe 4 input, See Table 1. Digital Ground. Register B CLEAR input (active LOW), can be used to asynchronously reset Register B to 0000 0000 0000. +5 V Supply Input. Reference input. Can be positive or negative DC voltage or AC signal. DAC Feedback Resistor. 18 19 20 VDD VREF RFB 13 14 15 16 17 STB3 STB4 DGND N/C CLR 8 9 10 11 12 N/C SR1 STB2 N/C LD2 4 5 6 7 PLCC PIN NO. 1 2 3 NAME N/C IOUT1 IOUT2 AGND STB1 N/C LD1 DESCRIPTION No Connection. DAC current output pin. Normally terminated at op amp virtual ground. DAC current output pin. Normally terminated at AGND. Analog Ground. Register A Strobe 1 input, See Table 1. No Connection. DAC Register B Load 1 input. When LD1 and LD2 go low the contents of Register A are loaded into DAC Register B. No Connection. Serial Data Input to Register A. Register A Strobe 2 input, See Table 1. No Connection. DAC Register B Load 2 input. When LD1 and LD2 go low the contents of Register A are loaded into DAC Register B. Register A Strobe 3 input, See Table 1. Register A Strobe 4 input, See Table 1. Digital Ground. No Connection. Register B CLEAR input (active LOW), can be used to asynchronously reset Register B to 0000 0000 0000. +5 V Supply Input. Reference input. Can be positive or negative DC voltage or AC signal. DAC Feedback Resistor. 6 7 8 9 N/C SRI STB2 LD2 10 11 12 13 STB3 STB4 DGND CLR 14 15 16 VDD VREF RFB Rev. 2.00 3 MP7543 ELECTRICAL CHARACTERISTICS (VDD = + 5 V, VREF = +10 V unless otherwise noted) 25°C Typ Tmin to Tmax Min Max Parameter STATIC PERFORMANCE1 Resolution (All Grades) Integral Non-Linearity (Relative Accuracy) J, A, S K, B, T Differential Non-Linearity J, A, S K, B, T Gain Error J, A, K, B, S, T Gain Temperature Coefficient2 Power Supply Rejection Ratio Output Leakage Current J, K, A, B S, T DYNAMIC PERFORMANCE Current Output Settling Time2 AC Feedthrough at IOUT12 REFERENCE INPUT Input Resistance DIGITAL INPUTS3 Logical “1” Voltage Logical “0” Voltage Input Leakage Current ANALOG OUTPUTS2 Output Capacitance Symbol Min Max Units Test Conditions/Comments N INL 12 12 Bits LSB Best Fit Straight Line Spec. (Max INL – Min INL) / 2 +1 +1/2 DNL +2 +1 GE +12.3 TCGE PSRR IOUT +10 +10 +50 +1 +1/2 LSB +2 +1 LSB +14.5 +2 +100 ppm/°C ppm/% nA +10 +200 ∆Gain/∆Temperature |∆Gain/∆VDD| ∆VDD = + 5% Monotonicity: 11 Bits Guaranteed 12 Bits Guaranteed Using Internal RFB tS FT 2 2 µs 2.5 2.5 mV p-p RL=100Ω, CL=13pF Full Scale Output Settles to 1/2 LSB of Final Value VREF = 10kHz, 20 Vp-p, sinewave RIN 5 10 20 5 20 kΩ VIH VIL ILKG 3.0 0.8 +1 3.0 0.8 +1 V V µA COUT1 COUT1 COUT2 COUT2 POWER SUPPLY Supply Voltage Supply Current VDD IDD 4.75 260 100 50 210 260 100 50 210 pF pF pF pF DAC Inputs all 1’s DAC Inputs all 0’s DAC Inputs all 1’s DAC Inputs all 0’s 5.25 2.5 4.75 5.25 2.5 V mA VDD = +5 V +5% for specified performance All digital inputs = 0 V or all = 5 V Rev. 2.00 4 MP7543 ELECTRICAL CHARACTERISTICS (CONT’D) Parameter SWITCHING CHARACTERISTICS2, 4 Serial Input to Strobe Set-up Time Serial Input to Strobe Set-up Time Serial Input to Strobe Set-up Time Serial Input to Strobe Set-up Time Serial Input to Strobe Hold Time Serial Input to Strobe Hold Time Serial Input to Strobe Hold Time Serial Input to Strobe Hold Time SRI Data Pulse Width STB1 Pulse Width STB4 Pulse Width STB3 Pulse Width STB2 Pulse Width Load Pulse Width Minimum time between strobing Reg. A and loading Reg. B CLR pulse width NOTES: 1 2 3 4 Symbol Min 25°C Typ Max Tmin to Tmax Min Max Units Test Conditions/Comments tDS1 tDS4 tDS3 tDS2 tDH1 tDH4 tDH3 tDH2 tSRI tSTB1 tSTB4 tSTB3 tSTB2 tLD1, 2 tASB tCLR 50 0 0 20 30 80 80 60 80 80 100 100 80 150 0 200 100 0 0 40 60 160 160 120 160 160 200 200 160 300 0 400 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns STB1 used as a strobe STB4 used as a strobe STB3 used as a strobe STB2 used as a strobe STB1 used as a strobe STB4 used as a strobe STB3 used as a strobe STB2 used as a strobe Full Scale Range (FSR) is 10V for unipolar mode. Guaranteed but not production tested. Digital input levels should not go below ground or exceed the positive supply voltage, otherwise damage may occur. See timing diagram. Specifications are subject to change without notice ABSOLUTE MAXIMUM RATINGS (TA = +25°C unless otherwise noted)1, 2, 3 VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V Digital Input Voltage to GND (2) . GND –0.5 to VDD +0.5 V IOUT1, IOUT2 to GND . . . . . . . . . . . GND –0.5 to VDD +0.5 V VREF to GND (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +25 V VRFB to GND (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +25 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1 V (Functionality Guaranteed +0.5 V) Storage Temperature . . . . . . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 10 seconds) . . . . . . +300°C Package Power Dissipation Rating to 75°C CDIP, PDIP, SOIC, PLCC . . . . . . . . . . . . . . . . . . 700mW Derates above 75°C . . . . . . . . . . . . . . . . . . . . . 10mW/°C NOTES: 1 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2 Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short transients outside the supplies of less than 100mA for less than 100µs. 3 GND refers to AGND and DGND. Rev. 2.00 5 MP7543 TIMING DIAGRAM tSRI SR1 tDS1, tDS2, tDS4 Strobe Input (STB1, STB2, STB4 (Note) 1 tSTB1 tSTB2 tSTB4 LOADING REGISTER A tASB LD1 AND LD2 Note: Strobe Waveform is Inverted if STB3 is Used to Strobe Serial Data Bits into Register A Loading Register B with Contents of Register A tLD1 tLD2 Bit 1 MSB Bit 2 tDH1, tDH2, tDH4 2 11 12 Bit 11 Bit 12 LSB MP7543 Logic Inputs Register A Control Inputs STB4 0 0 0 1 1 X X X X 0 X X STB3 1 1 0 0 X X 1 X STB2 0 0 0 0 X X X 1 0 1 1 1 X 1 X 0 X X 1 0 Clear Register B to code 0000 0000 0000 (Asynchronous) No Operation (Register B) Load Register B with the contents of Register A 1, 3 3 3 No Operation (Register A) 3 STB1 Register B Control Inputs CLR X X X X LD2 X X X X LD1 X X X X Data appearing at SRI strobed into Register A Data appearing at SRI strobed into Register A Data appearing at SRI strobed into Register A Data appearing at SRI strobed into Register A 2, 3 2, 3 2, 3 2, 3 MP7543 Operation Notes NOTES 1. CLR = 0 Asynchronously resets Register B to 0000 0000 0000, but has no effect on Register A. 2. Serial data is loaded into Register A MSB first, on edges shown is positive edge, is negative edge. 3. 0 = Logic LOW, 1 = Logic HIGH, X = Don’t Care. Table 1. Truth Table Rev. 2.00 6 MP7543 APPLICATION NOTES Refer to Section 8 for Applications Information (8) 8085 ALE ADDRESS BUS (16) A0-15 ADDRESS (16) 6800 R/W ADDRESS BUS (16) A0-15 ADDRESS (16) 8212 +5 V E1 E3 8205 DECODER φ2 E1 E3 E2 8205 DECODER WR E2 D0 D7 (8) AD0-7 DATA DATA (8) DATA BUS (8) DATA (8) SOD +5 V SR1 LD2 STB2 STB3 MP7543 STB1 STB4 CLR LD1 +5 V SR1 LD2 STB1 STB3 MP7543 STB2 STB4 LD1 CLR FROM SYSTEM RESET FROM SYSTEM RESET Figure 1. MP7543 8085 Interface Figure 2. MP7543 MC6800 Interface Digital Input VIN RFB IOUT1 VREF MP7543 IOUT2 – + VOUT Figure 3. Digitally Programmable Gain Amplifier Graph 1. Relative Accuracy vs. Digital Code Rev. 2.00 7 MP7543 16 LEAD PLASTIC DUAL-IN-LINE (300 MIL PDIP) N16 S 16 1 Q1 D 9 8 E1 E A1 Seating Plane A L B e B1 α C INCHES SYMBOL A A1 B B1 (1) C D E E1 e L MIN –– 0.015 0.014 0.038 0.008 0.745 0.295 0.220 MAX 0.200 –– 0.023 0.065 0.015 0.785 0.325 0.310 MILLIMETERS MIN –– 0.38 0.356 0.965 0.203 18.92 7.49 5.59 MAX 5.08 –– 0.584 1.65 0.381 19.94 8.26 7.87 0.100 BSC 0.115 0° 0.055 0.020 (1) 0.150 15° 0.070 0.080 2.54 BSC 2.92 0° 1.40 0.51 3.81 15° 1.78 2.03 α Q1 S Note: The minimum limit for dimensions B1 may be 0.023” (0.58 mm) for all four corner leads only. Rev. 2.00 8 MP7543 16 LEAD CERAMIC DUAL-IN-LINE (300 MIL CDIP) D16 S1 See Note 1 16 1 S 9 8 E1 D Base Plane Seating Plane L e b b1 L1 c Q A E α INCHES SYMBOL A b b1 c D E E1 e L L1 Q S S1 MIN –– 0.014 0.038 0.008 –– 0.220 0.290 MAX 0.200 0.023 0.065 0.015 0.840 0.310 0.320 MILLIMETERS MIN –– 0.356 0.965 0.203 –– 5.59 7.37 MAX 5.08 0.584 1.65 0.381 21.34 7.87 8.13 NOTES –– –– 2 –– 4 4 7 5 –– –– 3 6 6 –– NOTES 1. Index area; a notch or a lead one identification mark is located adjacent to lead one and is within the shaded area shown. 2. The minimum limit for dimension b1 may be 0.023 (0.58 mm) for all four corner leads only. 3. Dimension Q shall be measured from the seating plane to the base plane. 4. This dimension allows for off-center lid, meniscus and glass overrun. 5. The basic lead spacing is 0.100 inch (2.54 mm) between centerlines. 6. Applies to all four corners. 7. This is measured to outside of lead, not center. 0.100 BSC 0.125 0.150 0.015 –– 0.005 0° 0.200 –– 0.060 0.080 –– 15° 2.54 BSC 3.18 3.81 0.381 –– 0.13 0° 5.08 –– 1.52 2.03 –– 15° α Rev. 2.00 9 MP7543 16 LEAD SMALL OUTLINE (300 MIL JEDEC SOIC) S16 D 16 9 E H 8 h x 45° C Seating Plane e B A1 L A α INCHES SYMBOL A A1 B C D E e H h L MIN 0.097 0.0050 0.014 0.0091 0.402 0.292 MAX 0.104 0.0115 0.019 0.0125 0.412 0.299 MILLIMETERS MIN 2.46 0.127 0.356 0.231 10.21 7.42 MAX 2.64 0.292 0.482 0.318 10.46 7.59 0.050 BSC 0.400 0.010 0.016 0° 0.410 0.016 0.035 8° 1.27 BSC 10.16 0.254 0.406 0° 10.41 0.406 0.889 8° α Rev. 2.00 10 MP7543 20 LEAD PLASTIC LEADED CHIP CARRIER (PLCC) P20 D D1 A2 Seating Plane 1 D D1 e1 B D2 D3 A C A1 INCHES SYMBOL A A1 A2 B C D D1 (1) D2 D3 e1 Note: (1) MIN 0.165 0.100 0.148 0.013 0.008 0.385 0.350 0.290 MAX 0.180 0.110 0.156 0.021 0.012 0.395 0.354 0.330 MILLIMETERS MIN 4.19 2.54 3.76 0.330 0.203 9.78 8.89 7.37 MAX 4.57 2.79 3.96 0.533 0.305 10.03 8.99 8.38 0.200 Ref 0.050 BSC 5.08 Ref. 1.27 BSC Dimension D1 does not include mold protrusion. Allowed mold protrusion is 0.254 mm/0.010 in. Rev. 2.00 11 MP7543 NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contains here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright EXAR Corporation Datasheet April 1995 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. Rev. 2.00 12