MP7626KD

MP7626 Microprocessor Compatible Buffered Multiplying 16-Bit Digital-to-Analog Converter FEATURES • • • • • • • • Four Quadrant Multiplication 16-Bit Monotonicity Low Power Consumption TTL/5 V CMOS Compatible Single-Buffered or Transparent Data inputs Decoded DAC Approach Latch-Up Free 8-Bit Bus Version: MP7636A APPLICATIONS • • • • • Digitally Programmable References Programmable Audio Attenuator High Accuracy Process Control Systems Automatic Test Equipment Easy Interface to 8 and 16-Bit Microprocessor Buses GENERAL DESCRIPTION The MP7626 is a CMOS 16-bit Digital-to-Analog Converter (DAC) that is manufactured using advanced thin film resistors on a double metal CMOS process. It incorporates a unique bit decoding technique yielding lower glitch, higher speed and excellent accuracy over temperature and time. 16 bit differential non-linearity is achieved with minimal trimming. Two 8-bit latches (MSB latch and LSB latch) hold the 16-bit data which are converted by the DAC. A 16-bit bus can load both latches in one cycle. An 8-bit bus loads one latch at a time. By making the latches transparent (MSB latch = LSB latch = High) the DAC will continuously convert the BIT1 - BIT16 inputs. SIMPLIFIED BLOCK AND TIMING DIAGRAM VREF VDD DB15-DB8 MSB Latch D Q Latch E 8 16 16 RFB 16-Bit Multiplying DAC DATA LATCH IOUT1 IOUT2 OUTPUT DB7-DB0 LSB Latch D Q Latch E 8 GND Rev. 2.00 1 MP7626 ORDERING INFORMATION Package Type Plastic Dip Plastic Dip PLCC PLCC Ceramic Dip Ceramic Dip Temperature Range –40 to +85°C –40 to +85°C –40 to +85°C –40 to +85°C –40 to +85°C –40 to +85°C Part No. MP7626JN MP7626KN MP7626JP MP7626KP MP7626JD* MP7626KD* INL (LSB) +4 +2 +4 +2 +4 +2 DNL (LSB) +4 +2 +4 +2 +4 +2 Gain Error (% FSR) +0.1 +0.1 +0.1 +0.1 +0.1 +0.1 *Recommend using MP7626KN or JN PIN CONFIGURATION See Packaging Section for Package Dimensions DB6 DB4 N/C DB8 N/C DB7 DB5 4 3 2 1 28 27 26 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DB14 (MSB) DB15 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 DB3 DB2 DB1 DB0 (LSB) MSB LATCH LSB LATCH GND VDD IOUT1 IOUT2 RFB VREF DB9 DB10 DB11 DB12 DB13 DB14 (MSB) DB15 5 6 7 8 9 10 11 12 13 14 15 16 17 18 25 24 23 22 21 20 19 DB3 DB2 DB1 DB0 (LSB) MSB LATCH LSB LATCH GND N/C RFB IOUT1 N/C VREF IOUT2 VDD 24 Pin PDIP, CDIP (0.600”) N24, D24, C24 28 Pin PLCC P28 PIN OUT DEFINITIONS DIP 1 2 3 4 5 6 7 8 9 10 11 12 PLCC 26 27 28 1 2 5 6 7 8 9 10 11 NAME DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 DESCRIPTION Data Input Bit 4 Data Input Bit 5 Data Input Bit 6 Data Input Bit 7 Data Input Bit 8 Data Input Bit 9 Data Input Bit 10 Data Input Bit 11 Data Input Bit 12 Data Input Bit 13 Data Input Bit 14 Data Input Bit 15 (MSB) DIP 13 14 15 16 17 18 19 20 21 22 23 24 PLCC 13 14 15 16 17 19 20 21 22 23 24 25 NAME VREF RFB IOUT2 IOUT1 VDD GND LSB MSB DB0 DB1 DB2 DB3 DESCRIPTION Reference Input Voltage Internal Feedback Resistor Pin Current Output 2 Current Output 1 Power Supply Ground LSB Latch Enable MSB Latch Enable Data Input Bit 0 (LSB) Data Input Bit 1 Data Input Bit 2 Data Input Bit 3 Rev. 2.00 2 MP7626 ELECTRICAL CHARACTERISTICS (VDD = + 15 V, VREF = +10 V unless otherwise noted) Parameter STATIC PERFORMANCE1 Resolution (All Grades) Relative Accuracy J K Differential Non-Linearity J K Gain Error Gain Temperature Coefficient2 Power Supply Rejection Ratio Output Leakage Current DYNAMIC PERFORMANCE2 Current Settling Time AC Feedthrough at IOUT1 REFERENCE INPUT Input Resistance DIGITAL INPUTS3 Logical “1” Voltage Logical “0” Voltage Input Leakage Current Input Capacitance2 Data Control ANALOG OUTPUTS2 Output Capacitance COUT1 COUT1 COUT2 COUT2 POWER SUPPLY Functional Voltage Range5 Supply Current VDD IDD 4.5 16.5 1 5.0 16.5 1 V mA 280 120 100 240 pF pF pF pF DAC Inputs all 1’s DAC Inputs all 0’s DAC Inputs all 1’s DAC Inputs all 0’s VIH VIL ILKG CIN CIN 5 5 3.0 2.4 0.8 +1 3.0 0.8 +1 V V µA pF pF RIN 2.5 7.5 2.5 7.5 kΩ tS FT 2 2 µs mV p-p N INL +4 +2 DNL +4 +2 GE TCGE PSRR IOUT +50 +10 +0.1 +4 +2 +0.1 +2 +50 +200 % FSR ppm/°C ppm/% nA Using Internal RFB ∆Gain/∆Temperature |∆Gain/∆VDD| ∆VDD = + 5% IOUT1 RL=100Ω, CL=13pF Full Scale Change to 0.1% VREF = 10kHz, 20 Vp-p, sinewave +4 +2 LSB 16 16 Bits LSB Best Fit Straight Line Spec. (Max INL – Min INL) / 2 Symbol Min 25°C Typ Max Tmin to Tmax Min Max Units Test Conditions/Comments FSR = Full Scale Range All digital inputs = 0 V or all = 5 V Rev. 2.00 3 MP7626 ELECTRICAL CHARACTERISTICS (CON’T) Parameter SWITCHING CHARACTERISTICS2, 4 Data Valid to Write Set-Up Time Write Strobe Width tDS tSW 250 125 ns ns Symbol Min 25°C Typ Max Tmin to Tmax Min Max Units Test Conditions/Comments NOTES: 1 Full Scale Range (FSR) is 10V for unipolar mode. 2 Guaranteed but not production tested. 3 Digital input levels should not go below ground or exceed the positive supply voltage, otherwise damage may occur. 4 See timing diagram. 5 Specified values guarantee functionality. Refer to other parameters for accuracy. Specifications are subject to change without notice ABSOLUTE MAXIMUM RATINGS (TA = +25°C unless otherwise noted)1, 2 Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +17 VDC Voltage at Any Digital Input . . . . . GND –0.5 to VDD +0.5 V DC Voltage Applied to IOUT1 or IOUT2 . . GND –0.5 to +17 V Voltage at VREF, RFB Inputs . . . . . . . . . . . . . . . . . . . . . . +25 V Storage Temperature Range . . . . . . . . . . . . –65°C to 150°C Package Power Dissipation Rating to 75°C CDIP, PDIP, PLCC . . . . . . . . . . . . . . . . . . . . . . . 1050mW Derates above 75°C . . . . . . . . . . . . . . . . . . . . . 14mW/°C NOTES: 1 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2 Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short transients outside the supplies of less than 100mA for less than 100µs. APPLICATION NOTES Refer to Applications Section for Additional Information LATCH CONTROL MSB LATCH 0 1 0 1 LSB LATCH 0 0 1 1 TIMING DIAGRAM Data Changing Data Stable FUNCTION Data Latched (Held) Transfer (DB15-DB8) to DAC Transfer (DB7-DB0) to DAC Transparent Mode Rev. 2.00 4 ÉÉ ÉÉÉÉÉÉ ÉÉÉ ÉÉ ÉÉÉÉÉÉ ÉÉÉ tS tDS tSW DATA LATCH OUTPUT MP7626 PERFORMANCE CHARACTERISTICS LSB Graph 1. Relative Accuracy vs. Digital Code APPLICATION NOTES Refer to Section 8 for Applications Information Rev. 2.00 5 MP7626 24 LEAD PLASTIC DUAL-IN-LINE (600 MIL PDIP) N24 S 24 13 E1 1 Q1 D 12 E A1 Seating Plane A L B e B1 α C INCHES SYMBOL A A1 B B1 (1) C D E E1 e L MIN –– 0.015 0.014 0.038 0.008 1.160 0.585 0.500 MAX 0.225 –– 0.023 0.065 0.015 1.290 0.625 0.610 MILLIMETERS MIN –– 0.38 0.356 0.965 0.203 29.46 14.86 12.70 MAX 5.72 –– 0.584 1.65 0.381 32.77 15.88 15.49 0.100 BSC 0.115 0° 0.055 0.040 (1) 0.150 15° 0.070 0.098 2.54 BSC 2.92 0° 1.40 1.02 3.81 15° 1.78 2.49 α Q1 S Note: The minimum limit for dimensions B1 may be 0.023” (0.58 mm) for all four corner leads only. Rev. 2.00 6 MP7626 24 LEAD CERAMIC DUAL-IN-LINE (600 MIL CDIP) D24 S1 24 S 13 See Note 1 1 12 E1 D Base Plane Seating Plane L e b b 1 E A Q c L1 α INCHES SYMBOL A b b1 c D E E1 e L L1 Q S S1 MIN –– 0.014 0.038 0.008 –– 0.500 0.590 MAX 0.225 0.023 0.065 0.015 1.290 0.610 0.620 MILLIMETERS MIN –– 0.356 0.965 0.203 –– 12.70 14.99 MAX 5.72 0.584 1.65 0.381 32.77 15.49 15.75 NOTES –– –– 2 –– 4 4 7 5 –– –– 3 6 6 –– NOTES 1. Index area; a notch or a lead one identification mark is located adjacent to lead one and is within the shaded area shown. 2. The minimum limit for dimension b1 may be 0.023 (0.58 mm) for all four corner leads only. 3. Dimension Q shall be measured from the seating plane to the base plane. 4. This dimension allows for off-center lid, meniscus and glass overrun. 5. The basic lead spacing is 0.100 inch (2.54 mm) between centerlines. 6. Applies to all four corners. 7. This is measured to outside of lead, not center. 0.100 BSC 0.120 0.150 0.015 –– 0.005 0° 0.200 –– 0.075 0.098 –– 15° 2.54 BSC 3.05 3.81 0.381 –– 0.13 0° 5.08 –– 1.91 2.49 –– 15° α Rev. 2.00 7 MP7626 24 LEAD CERAMIC SIDE-BRAZED DUAL-IN-LINE (600 MIL S/B DIP) C24 S1 24 S 13 1 12 D Base Plane Seating Plane L e b b1 L1 Q A c E E1 INCHES SYMBOL A b b1 c D E E1 e L L1 Q S S1 MIN –– 0.014 0.038 0.008 –– 0.500 0.590 MAX 0.225 0.023 0.065 0.015 1.290 0.610 0.620 MILLIMETERS MIN –– 0.356 0.965 0.203 –– 12.70 14.99 MAX 5.72 0.584 1.65 0.381 32.77 15.49 15.75 NOTES –– –– 2 –– 4 4 7 5 –– –– 3 6 6 NOTES 1. Index area; a notch or a lead one identification mark is located adjacent to lead one and is within the shaded area shown. 2. The minimum limit for dimension b1 may be 0.023 (0.58 mm) for all four corner leads only. 3. Dimension Q shall be measured from the seating plane to the base plane. 4. This dimension allows for off-center lid, meniscus and glass overrun. 5. The basic lead spacing is 0.100 inch (2.54 mm) between centerlines. 6. Applies to all four corners. 7. E1 shall be measured at the centerline of the leads. 0.100 BSC 0.120 0.150 0.015 –– 0.005 0.200 –– 0.075 0.098 –– 2.54 BSC 3.05 3.81 0.381 –– 0.13 5.08 –– 1.91 2.49 –– Rev. 2.00 8 MP7626 28 LEAD PLASTIC LEADED CHIP CARRIER (PLCC) P28 D D1 A2 Seating Plane 1 B D D1 e1 D2 D3 C A1 A INCHES SYMBOL A A1 A2 B C D D1 (1) D2 D3 e1 Note: (1) MIN 0.165 0.100 0.148 0.013 0.008 0.485 0.450 0.390 MAX 0.180 0.110 0.156 0.021 0.012 0.495 0.454 0.430 MILLIMETERS MIN 4.19 2.54 3.76 0.330 0.203 12.32 11.43 9.91 MAX 4.57 2.79 3.96 0.533 0.305 12.57 11.53 10.92 0.300 Ref 0.050 BSC 7.62 Ref. 1.27 BSC Dimension D1 does not include mold protrusion. Allowed mold protrusion is 0.254 mm/0.010 in. Rev. 2.00 9 MP7626 Notes Rev. 2.00 10 MP7626 Notes Rev. 2.00 11 MP7626 NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contains here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright EXAR Corporation Datasheet April 1995 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. Rev. 2.00 12