MP7628JS

MP7628 5 V CMOS Quad Multiplying 8-Bit Digital-to-Analog Converter FEATURES • • • • • • • • • Readback Capability for all DACs On-Chip Latches for All DACs Linearity Grades to +1/8 LSB Single Supply Voltage (5 Volt) DACs Matched to 1% Four Quadrant Multiplication Microprocessor TTL/CMOS Compatible Latch-Up Free Dual Version: MP7529B APPLICATIONS • Microprocessor Controlled Gain and Attenuation Circuits • Microprocessor Controlled/Programmable Power Supplies • Hardware Redundant Applications Requiring Data Readback GENERAL DESCRIPTION The MP7628 is a quad 8-bit Digital-to-Analog Converter designed using a decoded DAC architecture featuring excellent DAC-to-DAC matching and guaranteed monotonicity. Separate on-chip latches are provided for each DAC to allow easy microprocessor interface. The readback function allows the user to poll or read the data latches, eliminating the need for storing information in RAM. In the event the microprocessor power supply is interrupted, it can poll the DACs to establish the last known system state. Data is transferred into any of the four DAC data latches via common 8-bit TTL/CMOS compatible input port. Control inputs DS1, DS2 and A/B determine which DAC is to be loaded. The MP7628’s load cycle is similar to the write cycle of a random access memory and the device is bus compatible with most 8-bit microprocessors. The device operates at +5 V power supply and dissipates less than 5mW. All DACs offer excellent four quadrant multiplication characteristics with a separate reference input and feedback resistor for each DAC. SIMPLIFIED BLOCK DIAGRAM VDD LATCH A DAC A VREFB VREFA RFB RFBA IOUT1A IOUT2A/ IOUT2B DAC B DB0 (LSB) DATA BUS DB7 (MSB) THREE-STATE BUFFER BIDIRECTIONAL LINE DRIVER LATCH B IOUT1B RFB RFB RFBB RFBC IOUT1C IOUT2C/ IOUT2D THREE-STATE BUFFER LATCH C DAC C THREE-STATE BUFFER A/B R/W DS1 DS2 THREE-STATE BUFFER CONTROL LOGIC LATCH D DAC D IOUT1D RFB RFBD GND VREFC VREFD Rev. 2.00 1 MP7628 ORDERING INFORMATION Package Type Plastic Dip Plastic Dip SOIC SOIC PLCC PLCC Ceramic Dip Ceramic Dip Ceramic Dip Ceramic Dip Temperature Range –40 to +85°C –40 to +85°C –40 to +85°C –40 to +85°C –40 to +85°C –40 to +85°C –40 to +85°C –40 to +85°C –55 to +125°C –55 to +125°C Part No. MP7628JN MP7628KN MP7628JS MP7628KS MP7628JP MP7628KP MP7628AD MP7628BD MP7628SD* MP7628TD* INL (LSB) +1/2 +1/4 +1/2 +1/4 +1/2 +1/4 +1/2 +1/4 +1/2 +1/4 DNL (LSB) +1/2 +1/4 +1/2 +1/4 +1/2 +1/4 +1/2 +1/4 +1/2 +1/4 Gain Error (% FSR) +1.8 +0.9 +1.8 +0.9 +1.8 +0.9 +1.8 +0.9 +1.8 +0.9 *Contact factory for non-compliant military processing PIN CONFIGURATIONS See Packaging Section for Package Dimensions VDD VREFA RFBA IOUT1A IOUT2A/IOUT2B IOUT1B RFBB VREFB (LSB) DB0 DB1 DB2 DB3 DB4 DB5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 GND VREFC RFBC IOUT1C IOUT2C/IOUT2D IOUT1D RFBD VREFD DS2 DS1 R/W A/B DB7 (MSB) DB6 IOUT1A VREFA GND RFBC RFBA VDD VREFC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 4 3 2 1 28 27 26 IOUT2A/ IOUT2B IOUT1B RFBB VREFB DB0 (LSB) DB1 DB2 5 6 7 8 9 10 11 12 13 14 15 16 17 18 25 24 23 22 21 20 19 See Pin Out at Left 23 22 21 20 19 18 17 16 15 IOUT1C IOUT2C/ IOUT2D IOUT1D RFBD VREFD DS2 DS1 DB3 DB5 DB4 DB7 R/W (MSB) DB6 A/B 28 Pin CDIP, PDIP (0.600”) D28, N28 28 Pin SOIC (Jedec, 0.300”) S28 28 Pin PLCC P28 Rev. 2.00 2 MP7628 PIN OUT DEFINITIONS PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 NAME VDD VREFA RFBA IOUT1A IOUT2A/ IOUT2B IOUT1B RFBB VREFB DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 A/B R/W DS1 DS2 VREFD RFBD IOUT1D IOUT2C/ IOUT2D IOUT1C RFBC VREFC GND DESCRIPTION Power Supply Reference Voltage for DAC A Feedback Resistor for DAC A Current Output 1 DAC A Current Output 2 DAC A/DAC B Current Output 1 DAC B Feedback Resistor for DAC B Reference Voltage for DAC B Data Input Bit 0 (LSB) Data Input Bit 1 Data Input Bit 2 Data Input Bit 3 Data Input Bit 4 Data Input Bit 5 Data Input Bit 6 Data Input Bit 7 (MSB) DAC Selection Read/Write Control 1 Control 2 Reference Voltage for DAC D Feedback Resistor for DAC D Current Output 1 DAC D Current Output 2 DAC C/DAC D Current Output 1 DAC C Feedback Resistor for DAC C Reference Voltage for DAC C Ground Rev. 2.00 3 MP7628 ELECTRICAL CHARACTERISTICS (VDD = + 5 V, VREF = +10 V unless otherwise noted) 25°C Typ Tmin to Tmax Min Max Parameter STATIC PERFORMANCE1 Resolution (All Grades) Integral Non-Linearity (Relative Accuracy) J, A, S K, B, T Differential Non-Linearity J, A, S K, B, T Gain Error J, A, S K, B, T Gain Temperature Coefficient2 Power Supply Rejection Ratio Symbol Min Max Units Test Conditions/Comments FSR = Full Scale Range N INL 8 8 Bits LSB End Point Linearity Spec. +1/2 +1/4 DNL +1/2 +1/4 GE +1.5 +0.8 TCGE PSRR +200 +1/2 +1/4 LSB +1/2 +1/4 % FSR +1.8 +0.9 +2 +400 ppm/°C ppm/% All grades monotonic over full temperature range. Using Internal RFB Digital Inputs = VINH ∆Gain/∆Temperature |∆Gain/∆VDD| ∆VDD = + 5% Digital Inputs = VINH Digital Inputs = VINL Output Leakage Current (all) REFERENCE INPUT Voltage Range2 Input Resistance DIGITAL INPUTS3 Logic Thresholds VINH VINL Input Leakage Current Input Capacitance2 DATA BUS OUTPUTS Output Capacitance2 Input Leakage Current ANALOG OUTPUTS Propagation Delay2 Output Capacitance2 IOUT1 +50 +200 nA RIN 12 +20 28 12 +20 28 V kΩ 2.4 ILKG CIN 0.8 +1 3 2.4 0.8 +10 V V µA pF COUT ILKG 7 +1 +10 pF µA 500 750 ns From digital input to 90% of final analog output current DAC Inputs all 1’s DAC Inputs all 0’s Typical for code transition from all 0’s to all 1’s COUT COUT Glitch Energy2 160 120 80 440 pF pF nVs Rev. 2.00 4 MP7628 ELECTRICAL CHARACTERISTICS (CON’T) Parameter POWER SUPPLY5 Functional Voltage Range2 Supply Current SWITCHING CHARACTERISTICS2, 4 Data Write Time Write Strobe Req. Data Hold Time Data Read Time 3-state Hold Time Read Strobe Req. tW tDSW tDHLD tR tTSHD tDSR 320 200 40 480 240 320 400 250 50 600 300 400 ns ns ns ns ns ns VDD IDD 4.5 5.5 50 4.5 5.5 50 V µA Symbol Min 25°C Typ Max Tmin to Tmax Min Max Units Test Conditions/Comments All digital inputs = 0 V or all = 5 V NOTES: 1 2 3 4 5 Full Scale Range (FSR) is 10V for unipolar mode. Guaranteed but not production tested. Digital input levels should not go below ground or exceed the positive supply voltage, otherwise damage may occur. See timing diagrams. Specified values guarantee functionality. Refer to other parameters for accuracy. Specifications are subject to change without notice ABSOLUTE MAXIMUM RATINGS (TA = +25°C unless otherwise noted)1, 2 VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V Digital Input Voltage to GND (2) . GND –0.5 to VDD +0.5 V IOUT1, IOUT2 to GND (2) . . . . . . . . GND –0.5 to VDD +0.5 V VREF to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +25 V VRFB to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +25 V Storage Temperature . . . . . . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 10 seconds) . . . . . . +300°C Package Power Dissipation Rating to 75°C CDIP, PDIP, SOIC, PLCC . . . . . . . . . . . . . . . . . 1050mW Derates above 75°C . . . . . . . . . . . . . . . . . . . . . 14mW/°C NOTES: 1 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2 Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. Rev. 2.00 5 MP7628 TIMING DIAGRAM READ CYCLE A/B R/W DS1 DS2 H tD BUS (D N ) 3-state Data (A) tD 3-state = 40 ns = 320 ns = 120 ns = 200 ns tS tDSR (min) tNR tD Data (B) tS tDSR tNR Set up time for BUS, A/B, R/W Minimum DS = low pulse Minimum time between DS = low pulses Data delay time tR = tDSR + tNR TIMING DIAGRAM WRITE CYCLE DATA (DN ) A/B Data (A) Data (B) A Select tDHLD H L H tD tS tDSW tNW B Select R/W DS1 DS2 DAC A OUT DAC B OUT Last Data Last Data Set up time for BUS, A/B, R/W Minimum DS = low pulse Minimum time between DS = low pulses Data delay time tW = tDSW + tNW Data (A) tS + tD Data (B) = 40 ns = 200 ns = 120 ns = 110 ns tS tDSW (min) tNW tD MODE SELECTION TABLE DS1 L L H H L L H H L L H L L DS2 H H L L H H L L L L H L L A/B H L H L H L H L H L X H L R/W L L L L H H H H L L X H H MODE WRITE WRITE WRITE WRITE READ READ READ READ WRITE WRITE HOLD HOLD HOLD DAC A B C D A B C D A&C B&D A/B/C/D A/B/C/D A/B/C/D L = LOW STATE H = HIGH STATE X = DON’T CARE Rev. 2.00 6 MP7628 INTERFACE LOGIC INFORMATION DAC Selection: All DAC latches share a common 8-bit input port. The control inputs DS1, DS2, A/B select which DAC can accept data from the input port. Mode Selection: Inputs DS and R/W control the operating mode of the selected DAC. See Mode Selection Table on the previous page. Write Mode: When DS and R/W are both low the selected DAC is in the write mode. The input data latches of the selected DAC are transparent and its analog output responds to activity on DB0-DB7. Hold Mode: The selected DAC latch retains the data which was present on DB0-DB7 just prior to DS and R/W assuming a high state. Both analog outputs remain at the values corresponding to the data in their respective latches. Read Mode: When DS is low and R/W is high, the selected DAC is in the read mode and the data held in the appropriate latch is outputed to the data bus. APPLICATION NOTES Refer to Section 8 for Applications Information Rev. 2.00 7 MP7628 28 LEAD CERAMIC DUAL-IN-LINE (600 MIL CDIP) D28 S1 28 S 15 See Note 1 1 14 E1 D Base Plane Seating Plane L e b b1 c L1 Q A E α INCHES SYMBOL A b b1 c D E E1 e L L1 Q S S1 MIN –– 0.014 0.038 0.008 –– 0.500 0.590 MAX 0.232 0.023 0.065 0.015 1.490 0.610 0.620 MILLIMETERS MIN –– 0.356 0.965 0.203 –– 12.70 14.99 MAX 5.89 0.584 1.65 0.381 37.85 15.49 15.75 NOTES –– –– 2 –– 4 4 7 5 –– –– 3 6 6 –– NOTES 1. Index area; a notch or a lead one identification mark is located adjacent to lead one and is within the shaded area shown. 2. The minimum limit for dimension b1 may be 0.023 (0.58 mm) for all four corner leads only. 3. Dimension Q shall be measured from the seating plane to the base plane. 4. This dimension allows for off-center lid, meniscus and glass overrun. 5. The basic lead spacing is 0.100 inch (2.54 mm) between centerlines. 6. Applies to all four corners. 7. This is measured to outside of lead, not center. 0.100 BSC 0.125 0.150 0.015 –– 0.005 0° 0.200 –– 0.060 0.100 –– 15° 2.54 BSC 3.18 3.81 0.381 –– 0.13 0° 5.08 –– 1.52 2.54 –– 15° α Rev. 2.00 8 MP7628 28 LEAD PLASTIC DUAL-IN-LINE (600 MIL PDIP) N28 S 28 15 E1 1 Q1 D 14 E A1 Seating Plane A L B e B1 α C INCHES SYMBOL A A1 B B1 (1) C D E E1 e L MIN –– 0.015 0.014 0.038 0.008 1.380 0.585 0.500 MAX 0.232 –– 0.023 0.065 0.015 1.490 0.625 0.610 MILLIMETERS MIN –– 0.381 0.356 0.965 0.203 35.05 14.86 12.70 MAX 5.893 –– 0.584 1.65 0.381 37.85 15.88 15.49 0.100 BSC 0.115 0° 0.055 0.020 (1) 0.150 15° 0.070 0.100 2.54 BSC 2.92 0° 1.40 1.508 3.81 15° 1.78 2.54 α Q1 S Note: The minimum limit for dimensions B1 may be 0.023” (0.58 mm) for all four corner leads only. Rev. 2.00 9 MP7628 28 LEAD SMALL OUTLINE (300 MIL JEDEC SOIC) S28 D 28 15 E H 14 h x 45° C Seating Plane e B A1 L A α INCHES SYMBOL A A1 B C D E e H h L MIN 0.097 0.0050 0.014 0.0091 0.701 0.292 MAX 0.104 0.0115 0.019 0.0125 0.711 0.299 MILLIMETERS MIN 2.464 0.127 0.356 0.231 17.81 7.42 MAX 2.642 0.292 0.483 0.318 18.06 7.59 0.050 BSC 0.400 0.010 0.016 0° 0.410 0.016 0.035 8° 1.27 BSC 10.16 0.254 0.406 0° 10.41 0.406 0.889 8° α Rev. 2.00 10 MP7628 28 LEAD PLASTIC LEADED CHIP CARRIER (PLCC) P28 D D1 A2 Seating Plane 1 B D D1 e1 D2 D3 C A1 A INCHES SYMBOL A A1 A2 B C D D1 (1) D2 D3 e1 Note: (1) MIN 0.165 0.100 0.148 0.013 0.008 0.485 0.450 0.390 MAX 0.180 0.110 0.156 0.021 0.012 0.495 0.454 0.430 MILLIMETERS MIN 4.19 2.54 3.76 0.330 0.203 12.32 11.43 9.91 MAX 4.57 2.79 3.96 0.533 0.305 12.57 11.53 10.92 0.300 Ref 0.050 BSC 7.62 Ref. 1.27 BSC Dimension D1 does not include mold protrusion. Allowed mold protrusion is 0.254 mm/0.010 in. Rev. 2.00 11 MP7628 NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contains here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright EXAR Corporation Datasheet April 1995 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. Rev. 2.00 12