MP7652AS

MP7652 4-Channel Voltage Output 15 MHz, Input Bandwidth, 8-Bit Multiplying DACs with 3-Wire Serial Digital Port and Independent References FEATURES • Independent References • 4 Independent 2-Quadrant Multiplying 8-Bit DACs • Dual Positive (+10 V and +5 V) Supplies or Dual (+5 V) Supplies Capability • High Speed: – 12.5 MHz Digital Clock Rate – VREF to VOUT Settling Time: 150ns to 8–bit (typ) – Voltage Reference Input Bandwidth: 15 MHz • Low Power: 80mW • Low AC Voltage Reference Feedthrough • Excellent Channel-to-Channel Isolation • DNL = +0.5 LSB, INL = +1 LSB (typ) • DACs Matched to +0.5% (typ) • Very Low Noise • Low Harmonic Distortion: 0.25% typical with VREF = 1 V p-p @ 1 MHz • VREF/2 Output Preset Level • Latch-Up Free • ESD Protection: 2000 V Minimum APPLICATIONS • Direct High-Frequency Automatic Gain Control • Video AGC & CCD Level AGC • Convergence Adjustment for High-Resolution Monitors (Workstations) GENERAL DESCRIPTION The MP7652 is ideal for digital gain control of high frequency analog signals such as video, composite video, CCD and others. The device includes 4-channels of high speed, wide bandwidth, two quadrant multiplying, 8-bit accurate digital-toanalog converter. It includes an output drive buffer per channel capable of driving a +1mA (typ) load. DNL of better than +0.5 LSB is achieved with a channel-to-channel matching of typically 0.5%. Stability, matching, and precision of the DACs are achieved by using MPS’ thin film technology. Also, excellent channel-to-channel isolation is achieved with EXAR’s BiCMOS process which cannot be achieved using a typical CMOS technology. An open loop architecture (patent pending) provides wide small signal bandwidth from VREF to output up to 15 MHz (typ), fast output settling time of 150 ns, and excellent VREF feedthrough isolation. The bottom of each DAC reference string is brought out separately for totally isolated operation. In addition, low distortion in the order of 0.25% with a 1 V p-p, 1 MHz signal is achieved. The combination of a constant input Z and the ability to vary VREFN within VCC –1.8 and VEE +1.5 V allows flexibility for optimum system design. The MP7652 is fabricated on a junction isolated, high speed BiCMOS (BiCMOS IVTM) process with thin film resistors. This process enables precision high speed analog/digital (mixedmode) circuits to be fabricated on the same chip. ORDERING INFORMATION Package Type SOIC Plastic Dip Temperature Range –40 to +85°C –40 to +85°C Part No. MP7652AS MP7652AN INL (LSB) +1 +1 DNL (LSB) +0.5 +0.5 Gain Error (% FSR) +1.5 +1.5 Rev. 1.00 1 MP7652 SIMPLIFIED BLOCK DIAGRAM VDD VCC VEE PRESET LATCH1 VDD DAC1 VREFP1 VOUT1 VREFN1 VREFP2 LATCH2 DAC1 VOUT2 VREFN2 VREFP3 LATCH3 DAC1 VOUT3 VREFN3 VREFP4 LATCH4 DAC1 VOUT4 VREFN4 LD 2 to 4 Decoder SDO SDI CLK EN DQ D Q DB0 to DB7 A0 A1 X X 12-BIT SHIFT REGISTER DGND Rev. 1.00 2 MP7652 PIN CONFIGURATIONS N/C N/C VDD VCC VEE DGND VREFN1 VOUT1 VREFP1 VREFP2 VOUT2 VREFN2 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 N/C PRESET LD CLK SDO SDI VREFN4 VOUT4 VREFP4 VREFP3 VOUT3 VREFN3 N/C N/C VDD VCC VEE DGND VREFN1 VOUT1 VREFP1 VREFP2 VOUT2 VREFN2 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 N/C PRESET LD CLK SDO SDI VREFN4 VOUT4 VREFP4 VREFP3 VOUT3 VREFN3 24 Pin PDIP (0.300”) NN24 24 Pin SOIC (Jedec, 0.300”) S24 PIN OUT DEFINITIONS PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 NAME N/C N/C VDD VCC VEE DGND VREFN1 VOUT1 VREFP1 VREFP2 VOUT2 VREFN2 VREFN3 DESCRIPTION No Connection No Connection Digital Positive Supply Analog Positive Supply Analog Negative Supply Digital Ground DAC 1 Negative Reference Input DAC 1 Output DAC 1 Positive Reference Input DAC 2 Positive Reference Input DAC 2 Output DAC 2 Negative Reference Input DAC 3 Negative Reference Input 24 N/C PIN NO. 14 15 16 17 18 19 20 21 22 23 NAME VOUT3 VREFP3 VREFP4 VOUT4 VREFN4 SDI SDO CLK LD PRESET DESCRIPTION DAC 3 Output DAC 3 Positive Reference Input DAC 4 Positive Reference Input DAC 4 Output DAC 4 Negative Reference Input Serial Data and Address Input Serial Data Output Shift Register Clock Input Load Data to Selected DAC Preset all DACs to 1/2 (VREF – VREFN). PRESET is internally connected to VDD through 300 kΩ. No Connection Rev. 1.00 3 MP7652 ELECTRICAL CHARACTERISTICS TABLE FOR DUAL SUPPLIES Unless Otherwise Noted: VDD = 5 V, VCC = +5 V, VEE = –5 V, VREFP = 3 V and –3 V, T = 25°C, Output Load = Open, DGND=VREFN = 0 V Parameter DC CHARACTERISTICS Resolution (All Grades) Differential Non-Linearity Integral Non-Linearity Monotonicity Gain Error Zero Scale Offset Output Drive Capability REFERENCE/INV INPUTS Impedance of VREF Voltage Range VREFN DC Voltage Range REF VR INV Pos. INV Neg. 6 VEE +1.5 VO VEE + 1 18 VCC –1.8 kΩ V V V N DNL INL GE ZOFS IO +1 8 +0.8 +1 Guaranteed +1.5 +50 % FSR mV mA FSR = Full Scale Range1 Bits LSB LSB Symbol Min 25°C Typ Max Units Test Conditions/Comments VREFP Max Swing is VREFN +3 V DYNAMIC CHARACTERISTICS2 Input to Output Bandwidth Input to Output Settling Time6 Small Signal Voltage Reference Input to Output Bandwidth Small Signal Voltage Reference Input to Output Bandwidth Voltage Settling from VREF to VDAC Out Voltage Settling from Digital Code to VDAC Out VREF Feedthrough Group Delay Harmonic Distortion Channel-to-Channel Crosstalk Digital Feedthrough Power Supply Rejection Ratio POWER CONSUMPTION Positive Supply Current Negative Supply Current Power Dissipation DIGITAL INPUT CHACTERISTICS Logic High3 Logic Low3 Input Current Input Capacitance2 VIH VIL IL CL 2.4 0.8 +10 8 V V µA pF ICC IEE PDISS 12 12 80 mA mA mW 15 150 15 15 275 275 TBD TBD TBD TBD TBD +0.5 MHz ns MHz MHz ns ns dB ns % dB nVs %/% RL = 5 kΩ, CL = 20 pF VREFP=1.6 Vp–p, RL =5kΩ, to VEE VREFP=1.6Vp–p, RL =5kΩ, to VEE VOUT=50mV p-p above code 16 VOUT=50mV p-p for all codes VREFP=0 to VREFP = 3V Step6 to 1 LSB ZS to FS to 1 LSB Codes=0 @ 1 MHz VREFP=1MHz Sine 3V p-p @ 1 MHz, single channel CLK to VOUT ∆V=+5% ƒtr ƒtr tsr tsd FDT GD THD CT Q PSRR VREFP = 0 V VREFP = 0 V VREFP = 0 V, Codes = all 1 Rev. 1.00 4 MP7652 ELECTRICAL CHARACTERISTICS TABLE Description DIGITAL TIMING SPECIFICATIONS2, 4 Input Clock Pulse Width Data Setup Time Data Hold Time CLK to SDO Propagation Delay DAC Register Load Pulse Width PRESET Pulse Width Clock Edge to Load Rising Edge Clock Edge to Load Falling Edge Load Falling Edge to SDO Tri-state Enable Load Rising Edge to SDO Tri-state Disable Load Falling Edge to CLK Disable Load Rising Edge to CLK Enable LD Set-up Time with Respect to CLK tCH, tCL tDS tDH tPD tLD tPR tCKLD1 tCKLD2 tHZ1 tHZ2 tLDCK1 tLDCK2 tLDSU 60 70 0 150 100 50 100 0 80 40 30 60 20 ns ns ns ns ns ns ns ns ns ns ns ns ns Symbol Min 25°C Typ Max Units Conditions NOTES 1 Full Scale Range (FSR) is 3V. 2 Guaranteed but not production tested. 3 Digital input levels should not go below ground or exceed the positive supply voltage, otherwise damage may occur. 4 See Figures 1 and 2. 5 For reference input pulse: tR = tF > 100 ns. Specifications are subject to change without notice ABSOLUTE MAXIMUM RATINGS (TA = +25°C unless otherwise noted)1, 2 VCC to VREFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.5 V VEE to VREFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –6.5 V VCC to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +13.0 V VEE to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –6.5 V VREFP 1-4 to DGND, VREFN . . . . . . . . . . . . . . . . . VCC to VEE Digital Input & Output Voltage to DGND –0.5 to VDD +0.5 V Operating Temperature Range Extended Industrial . . . . . . . . . . . . . . . . . . . –40°C to +85°C Maximum Junction Temperature . . . . . . . . . –65°C to 150°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . +300°C Package Power Dissipation Rating @ 75°C PDIP, SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000mW Derates above 75°C . . . . . . . . . . . . . . . . . . . . . . 6mW/°C NOTES: 1 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2 Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short transients outside the supplies of less than 100mA for less than 100µs. Rev. 1.00 5 MP7652 SDI 1 (Data In) 0 CLK 1 0 LD 1 0 VOUT DAC Register Loaded (PRESET = “High” or open) SDI 1 0 tDH tHZ1 tHZ2 HIGH Z tLDCK2 SDO 1 0 1 tCH tPD tCKLD2 tCKLD1 CLK LD 0 1 0 tCL VOUT tSD + 1/2 LSB BAND (PRESET = “High” or open) VO = VREF VOUT = 1/2 (VREFP – VREFN) + VREFN + 1/2 LSB ERROR BAND Rev. 1.00 6 ÉÉÉ É ÉÉÉÉÉ ÉÉÉ PRESET 1 0 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Figure 1. Serial Data Timing and Loading tDS tLDSU tLDCK1 tLD Figure 2. Detail Serial Data Input Timing tRST tSD Figure 3. PRESET Operation MP7652 THEORY OF OPERATION The MP7652 is a 4-channel multiplying D/A converter that incorporates a novel open loop architecture invented by MPS. The design produces the widest bandwidth, fastest settling time, most constant group delay, and a very low noise operation compared to the conventional R-2R based architectures (given an equal technology platform). This device is particularly useful in applications where analog multipliers are used to perform the gain adjustment function for high frequency analog signal conditioning. Analog multipliers produce much higher noise and. This design allows for digital control of gain with constant and very low noise for all gain settings. going low also disables the serial data input (SDI), output (SDO tri-stated) and the CLK input. This design tremendously reduces digital noise, and glitch transients into the DACs due to free running CLK and SDI. Also, tri-stating the SDO output with LD signal would allow read back of pre-stored digital data of the selected package using one SDO wire for all DAC ICs on the board. When the PRESET signal is low, the output of all DACs are 1/2 of (VREFP + VREFN), regardless of any digital inputs. Note that VREFP is referenced to VREFN. Power Supplies and Voltage Reference DC Voltage Ranges Linearity Characteristics Each DAC achieves DNL  +0.5 LSB (typ), INL  +1 LSB (typ), and gain error  +1.5%. Since all 4 channel D/A converters are fabricated on the same IC, the linearity matching and gain matching of +0.5% (typ) is achieved. For the single supply operation, VCC = +10 V, VDD = +5 V, and VEE = DGND = 0 V. The VO 1-4 and VREFP 1-4 range would be VCC –1.8 V (10 – 1.8 = 8.2 V) to VEE +1.5 V (0 + 1.5 = 1.5 V). VREFN is the equivalent of AGND for this DAC. In this mode VREFN can be set at (VCC + VEE)/2 = (10 + 0)/2 = 5 V. VREFN 1-4 DC range can also be set from VEE +1.5 = 1.5 V to VCC – 1.5 = 8.2 V. Refer to Table 2. for the relationship equations. For the dual supply operation, VCC = +5, VDD = +5, and VEE = –5 V. The VOUT 1-4 and VREFP 1-4 range would be VCC –1.8 V (–1.8 = 3.2 V) to VEE +1.5 V (–5 + 1.5 = –3.5 V). In this mode VREFN can be set to (VCC + VEE)/2 = (5 – 5)/2 = 0 V. Similarly, VREFN 1-4 DC range can be set from VEE +1.5 V = 3.5 V to VCC –1.8 = +3.2 V. Refer to Table 2. for the relationship equations. VCC VREFP 1-4 +1 AC and Low Noise Performance The novel subranging architecture delivers a 15 MHz (type) –3 dB bandwidth. A constant group delay of 70 ns (typ) is achieved to frequencies up to 8 MHz. Analog output settling time for a code change of FS to ZS and ZS to FS with VREFP = 3 V, is typically 150 ns (with RL = 5 k to VEE). Also, with all codes set to FS (all 1s) and a VREFP 3 V step, the analog output will settle to 8 bits in less than 110 ns (typ). Note that the AC performance specifications also match to between all 4 channels. The above AC and transient performance is achieved with each channel consuming only 20 mW (typ) with 10 V p-p supplies. VOUT 1-4 Serial Port MP7652 is equipped with a serial data 3-wire standard µ-processor logic interface to reduce pin count, package size, and board wire (space). This interface consists of LD which controls the transfer of data to the selected DAC channel, SDI (serial data/address input), CLK (shift register clock) and SDO (serial data output). When the LD signal is high, CLK signal loads the digital input bits (SDI) into the 12-bit shift register. The LD signal going low loads this data into the selected DAC. The LD signal DAC Q2 Q1 VREFN 1-4 VEE I1 Figure 4. Simplified Block Diagram Rev. 1.00 7 MP7652 Inputs PRESET 0 1 1 1 1 1 1 1 1 1 Internal Address LD X 1 0 0→1 0 0→1 0 0→1 0 0→1 Output SDO X Last bit of shift reg. Hi-Z Last bit of shift reg. Hi-Z Last bit of shift reg. Hi-Z Last bit of shift reg. Hi-Z Last bit of shift reg. SDI X Data In X X X X X X X X CLK X 0→1 X X X X X X X X A1 X X 0 0 0 0 1 1 1 1 A0 X X 0 0 1 1 0 0 1 1 Operation Preset all DACs to 1/2 (VREFP + VREFN) Shift data in and out DAC 1 Transparent DAC 1 Latched DAC 2 Transparent DAC 2 Latched DAC 3 Transparent DAC 3 Latched DAC 4 Transparent DAC 4 Latched Table 1. Digital Function Truth Table Serial In/Serial Out D7 MSB 0 0 D6 D5 D4 D3 D2 D1 D0 DAC Output Voltage D LSB VOUTi = VREFNi + (VREFPi – VREFNi ) ( 256 ) 0 1 VREFN 1 (VREFP – VREFN) ( 256 ) + VREFN 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 254 (VREFP – VREFN) ( 256 ) + VREFN 255 (VREFP – VREFN) ( 256 ) + VREFN Table 2. DAC Transfer Function Analog Output vs. Digital Code Rev. 1.00 8 MP7652 OPERATION WITH DUAL POSITIVE POWER SUPPLIES For the dual positive supplies operation, VCC = +10 V, VDD = 5 V, VEE = 0 V and analog output zero level is to be referenced to (VCC + VEE) /2 by setting the AGND pin to 5 V. MICROPROCESSOR INTERFACE ADDRESS BUS A0 to A23 AS VMA CS ADDRESS DECODER MC68000 UPA 1/4 7HC125 UDS DB0 DB0 to DB15 16 FROM SYSTEM RESET 16 DATA BUS CLK LD SDI MP7652 PRESET Figure 5. MC68000 Interface (Simplified Diagram) A0 to A15 16 3 E1 A0 to A2 74LS138 ADDRESS DECODER 1 ADDRESS BUS MC6800 02 R/W 8 E3 E2 DB0 to DB7 8 DATA BUS DB7 LD SDI CLK MP7652 PRESET FROM SYSTEM RESET NOTES: 1. Execute consecutive memory write instructions while manipulating the data between WRITEs so that each WRITE presents the next bit 2. The serial data loading is triggered by the CLK pulse which is asserted by a decoded memory WRITE location 2000, R/W, and 02. A WRITE to address 4000 transfers data from the input shift register to the DAC register. Figure 6. MC6800 Interface (Simplified Diagram) Rev. 1.00 9 MP7652 8 ADDRESS BUS 8 3 A0 to A2 74LS138 E3 ADDRESS DECODER 8085 ALE 8212 +5 E1 WR E2 8 DATA BUS SOD LD SDI CLK MP7652 PRESET FROM SYSTEM RESET Figure 7. 8085 Interface (Simplified Diagram) NOTES: 1. Clock generated by WR and decoding address 8000 2. Data is clocked into the DAC shift register by executing memory write instructions. the clock input is generated by decoding address 8000 and WR. Data is then loaded into the DAC register with a memory write instruction to address 4000. 3. Serial data must be present in the right justified format in registers H & L of the microprocessor. Rev. 1.00 10 MP7652 VRP1 4 4 VOI1 VRP2 4 4 VOI2 VRPN 4 4 VOIN VRN1 µPC IC (1) MP7652 SDI LD SDO VRN2 IC (2) MP7652 SDI LD SDO VRNN IC (n) MP7652 SDI LD SDO DATA LD CLK Figure 8. Simplified Diagram Configuration A VRP1 4 4 VOI1 VRP2 4 4 VOI2 VRPN 4 4 VOIN VRN1 µPC DATA OUT DATA CS OR LD CLK n #1 IC (1) MP7652 SDI LD SDO VRN2 IC (2) MP7652 SDI LD SDO VRNN IC (n) MP7652 SDI LD SDO #2 #n Figure 9. Simplified Diagram Configuration B VRP1 4 1 SDO ADDRESS n 2 2n VRN1 4 VOI1 VRP2 4 VRN2 VOI2 4 VRPN 4 VOIN 4 µPC WR (SDI) DATA IN CLK IC (1) MP7652 SDI LD SDO IC (2) MP7652 SDI LD SDO2 VRNN IC (m) MP7652 SDI LD SDOm Figure 10. Simplified Diagram Configuration C Rev. 1.00 11 MP7652 1 0.75 Relative Accuracy (LSB) 0.5 0.25 0 –0.25 –0.5 –0.75 –1 0 64 128 192 256 Digital Code Graph 1. Relative Accuracy vs. Digital Code DACs 1 to 4 Gain (5dB/DIV) Group Delay (20 ns/DIV) MHz Graph 2. Typical Gain and Group Delay vs. Frequency (with 5K Resistor Across Output to VEE) Rev. 1.00 12 MP7652 24 LEAD PLASTIC DUAL-IN-LINE (300 MIL PDIP) NN24 S 24 1 Q1 D 13 12 E1 E A1 Seating Plane A L B e B1 α C INCHES SYMBOL A A1 B B1 (1) C D E E1 e L MIN –– 0.015 0.014 0.038 0.008 1.16 0.295 0.220 MAX 0.200 –– 0.023 0.065 0.015 1.280 0.325 0.310 MILLIMETERS MIN –– 0.38 0.356 0.965 0.203 29.46 7.49 5.59 MAX 5.08 –– 0.584 1.65 0.381 32.51 8.26 7.87 0.100 BSC 0.115 0° 0.055 0.028 (1) 0.150 15° 0.070 0.098 2.54 BSC 2.92 0° 1.40 0.711 3.81 15° 1.78 2.49 α Q1 S Note: The minimum limit for dimensions B1 may be 0.023” (0.58 mm) for all four corner leads only. Rev. 1.00 13 MP7652 24 LEAD SMALL OUTLINE (300 MIL JEDEC SOIC) S24 D 24 13 E H 12 h x 45° C Seating Plane e B A1 L A α INCHES SYMBOL A A1 B C D E e H h L MIN 0.097 0.0050 0.014 0.0091 0.602 0.292 MAX 0.104 0.0115 0.019 0.0125 0.612 0.299 MILLIMETERS MIN 2.464 0.127 0.356 0.231 15.29 7.42 MAX 2.642 0.292 0.483 0.318 15.54 7.59 0.050 BSC 0.400 0.010 0.016 0° 0.410 0.016 0.035 8° 1.27 BSC 10.16 0.254 0.406 0° 10.41 0.406 0.889 8° α Rev. 1.00 14 MP7652 Notes Rev. 1.00 15 MP7652 NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contains here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 1995 EXAR Corporation Datasheet April 1995 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. Rev. 1.00 16