MP8820AQ

MP8820 8-Bit Analog-to-Digital Converter with an 8-Channel MUX FEATURES • • • • • • • Precision 7–Bit Plus Sign ADC 8 Channel Analog Mux Single Reference to GND Input Referenced to User Supplied VMID DNL= ±1/2 LSB, INL=± 1 LSB Single Supply: 5 V ESD Protection: 2000 V APPLICATIONS • Servo Control • Low Cost Audio Control • Voice Acquisition GENERAL DESCRIPTION The MP8820 is a precision 1.6 MHz sampling 7-bit plus sign Analog-to-Digital Converter with an eight channel input mux and µP interface. The device has internal circuitry which receives the user supplied reference voltages VREF(+) and VREF(–), and generates the ADC reference voltages VMID  (VREF(+) – VREF(–)). Since VREF(+) is internally buffered and VREF(–) is generally ground, this structure allows the user to easily generate an input range biased about a user-supplied VMID from a grounded reference source. The internal ADC reference voltages are capable of swinging to within 0.5 V of the supply rails, giving the MP8820 a wide range over which the effective channel gain can be adjusted. The MP8820 uses a two-step flash conversion technique. The first section determines the sign and the 3 MSBs while the second segment converts the 4 LSBs. The ADC conversion begins when WR goes low and the data is valid 500 ns after the rising edge of WR. The MP8820 operates from a single 5V supply and consumes only 175mW of power. Specified for operation over the industrial (–40 to +85°C) temperature range, the MP8820 is available in Surface Mount (SOIC) and Shrunk Small Outline (SSOP) packages. SIMPLIFIED BLOCK DIAGRAM VDD AIN0-AIN7 8 8:1 MUX + 3 A0-A2 T/H G=1 VRT AIN 8 DB0-DB7 VMID VREF(+) VREF(–) + – G=1 – VMID 8-Bit ADC VRB + – G=1 Control GND WR Rev. 1.00 1 MP8820 ORDERING INFORMATION Package Type SOIC SSOP Temperature Range –40 to +85°C –40 to +85°C Part No. MP8820AS MP8820AQ PIN CONFIGURATIONS See Packaging Section for Package Dimensions A1 A2 VDD AIN1 VDD VDD GND AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A0 DB0 DB1 DB2 DB3 WR TEST DB4 DB5 DB6 DB7 VREF(–) VREF(+) VMID 28 Pin SOIC (0.300”) – S28 28 Pin SSOP – A28 PIN OUT DEFINITIONS PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 NAME A1 A2 VDD AIN0 VDD VDD GND AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 VMID DESCRIPTION Analog Input Mux Address Bit 1 Analog Input Mux Address Bit 2 Positive Power Supply (5 V) Analog Input 0 Positive Power Supply (5 V) Positive Power Supply (5 V) Negative power supplies (0V) Analog Input 1 Analog Input 2 Analog Input 3 Analog Input 4 Analog Input 5 Analog Input 6 Analog Input 7 System Reference 17 18 19 20 21 22 23 24 25 26 27 28 VREF(–) DB7 (MSB) DB6 DB5 DB4 TEST WR DB3 DB2 DB1 DB0 A0 PIN NO. 16 NAME VREF(+) DESCRIPTION Reference Voltage + Input Terminal Reference Voltage – Input Terminal. Data Output Bit 7 Data Output Bit 6 Data Output Bit 5 Data Output Bit 4 Test Mode Pin Sample Window Control Data Output Bit 3 Data Output Bit 2 Data Output Bit 1 Data Output Bit 0 Analog Input Mux Address Bit 0 Rev. 1.00 2 MP8820 ELECTRICAL CHARACTERISTICS TABLE FOR DUAL SUPPLIES Unless Otherwise Noted: VDD = 5 V, GND = 0 V, VREF(+) = 1.5 V, VREF(–) = 0 V, VMID = 2.5 V. 25°C Typ Parameter DC CHARACTERISTICS Resolution Differential Non-Linearity Differential Non-Linearity2 Integral Non-Linearity7 Integral Non-Linearity4, 7 Monotonicity Bipolar Zero Error Symbol Min Max Units Test Conditions/Comments N DNL DNL INL INL BZE 8 –1 –1 –1 –1 –25 +1/4 +1/2 +1/2 +1/2 Guaranteed 10 1 1 1 1 25 Bits LSB LSB LSB LSB mV @ VREF(+) – VREF(–) = 0.5 V @ VREF(+) – VREF(–) = 0.5 V Offset is measured as the bipolar zero code transition, 01111111 to 10000000, relative to VMID Zero Scale Drift2, 5 Full Scale Error VMID to VRT VMID to VRB ZSD 50 µV/°C %FS +FSE –FSE –5.0 –5.0 2.5 2.5 5.0 5.0 Full Scale Drift2, 6 DC Input Range1 Aperture Delay Input Capacitance FSD VINp-p tAP CIN 0.025 1 50 25 3 %FS/°C Vpp ns pF This is a measure of the internal reference translation. Ideally VRT – VMID = VMID – VRB = VREF(+) – VREF(–) The analog input is specified as Vpp centered around VMID From rising edge of WR Measured with VIN – DC = 2.5 V and WR = low REFERENCE VOLTAGES Positive Reference Input Voltage VREF(+) Input Resistance Internal Reference Settling Time VREF(+) RVR+ VRSTL 0.5 1 500 1.5 V MΩ ns Reference voltage with respect to VREF(–) Settling time required for ADC to make a proper conversion after (VREF(+) – VREF(–)) has changed Negative Reference Input Voltage VREF(–) Input Resistance VMID Input Current VMID Range VREF(–) RVR– IVM VMID 0 1 0 2.5 VREF(+) –0.5 2 3 V KΩ mA V VMID < VDD –0.5 – [VREF(+) – VREF(–)] VMID < VSS +0.5 + [VREF(–) – VREF(–)] All GNDs are Chip Substrate POWER SUPPLIES Positive Supply Negative Supply Power Supply Rejection Ratio2 Supply Current DIGITAL CHARACTERISTICS3, 4 Digital Input High Voltage Digital Input Low Voltage VIH VIL 4 1 V V VDD GND PSRR IDD 4.75 0 5 0 5.25 0 –48 45 V V dB mA f = 1 kHz. Not tested. Rev. 1.00 3 MP8820 ELECTRICAL CHARACTERISTICS TABLE Description DIGITAL CHARACTERISTICS (CONT’D) VOL VOH IIN-Dig 3-State Leakage Digital Timing Specifications Write time (analog input tracking) Conversion Time Input mux set-up time Input mux hold time VOL VOH IDL ILK 0.5 4.5 –50 –50 50 50 V µA µA @ IOL = 1 mA @ IOH = 1 mA Symbol Min 25°C Typ Max Units Conditions For testing, rise time = fall time = 10 ns. Output loading = 50 pF. tWR tCONV tMSU tMH 150 500 150 50 ns ns ns ns NOTES Maximum input voltage is 1 V less than VDD. 2 Guaranteed but not production tested. 3 Digital input levels should not go below ground or exceed the positive supply voltage, otherwise damage may occur. 4 See timing diagram. 5 Measured as the change in the bipolar zero error over temperature. This error does not include the error introduced by the external reference drift. 6 This error does not include the error introduced by the external reference drift. 7 INL is measured as a 7-bit +sign ADC with 8-bit resolution. 1 Specifications are subject to change without notice ABSOLUTE MAXIMUM RATINGS (TA = +25°C unless otherwise noted)1, 2 VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V All Digital Inputs . . . . . . . . . . . . . VDD +0.5 V to GND –0.5 V Storage Temperature . . . . . . . . . . . . . . . . . . . . –65 to 150°C Lead Temperature (Soldering 10 seconds) . . . . . . . +300°C ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000 V Package Power Dissipation Rating @ 75°C SSOP, SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000mW Derates above 75°C . . . . . . . . . . . . . . . . . . . . . . 6mW/°C NOTES: 1 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2 Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short transients outside the supplies of less than 100mA for less than 100µs. Rev. 1.00 4 MP8820 THEORY OF OPERATION The defining feature of the MP8820 is that it digitizes a bipolar input signal centered around a given voltage, VMID. The peak to peak swing of AIN is defined by the two input reference voltages, VREF(+) and VREF(–). The MP8820 takes in the center voltage and the two reference voltages and moves the resistor ladder endpoints VRT and VRB of the ADC around VMID by (VREF(+) – VREF(–)). In this way, a unipolar to bipolar translation can take place without having to use both a positive and negative supply. The center voltage acts as a bipolar zero and signals that moves below it are considered negative and signals that exceed it are taken to be positive. The block diagram is shown in Figure 1. VDD AIN0-AIN7 8 8:1 MUX + 3 A0-A2 T/H G=1 VRT AIN VMID 8-Bit ADC VRB 8 DB0-DB7 VMID VREF(+) VREF(–) + – G=1 – + – G=1 Control GND WR Figure 1. MP8820 Block Diagram Unlike a unipolar system where one end of the ADC’s resistor ladder is modulated above an offset voltage, both ends of the MP8820’s reference chain expand or contract around a fixed VMID. The maximum positive full scale voltage is VRT = VMID + (VREF(+) – VREF(–)). The maximum negative full scale voltage is VRB = VMID – (VREF(+) – VREF(–)). This type of translation is particularly useful in single supply applications where the input is centered about user specified VMID. The ideal transfer characteristic of the MP8820 is shown in Figure 2. An actual transfer characteristic with associated error terms is shown in Figure 3. VIN VRT = VMID + (VREF(+) – VREF(–)) 00000000 CODE OUT 11111111 VRB = VMID = (VREF(+) – VREF(–)) Figure 2. Ideal Transfer Characteristics Rev. 1.00 5 MP8820 VIN Ideal + Offset Ideal 00000000 curs in the negative half of the transfer function. Table 1. shows the digital codes that result from different input voltages. + INL Error Actual CODE – INL Error Offset 1111111 – Gain Error Figure 3. Transfer Characteristics with Error Terms The sign of the digital output code is determined by whether the input voltage, AIN, exceeds VMID. If AIN is greater than VMID, then the seven bit conversion occurs in the positive half of the transfer function. If AIN is less than VMID, then the translation octAP WR tWR Track AIN for Sample N The MP8820 uses a stand alone µP interface. The user starts a conversion by taking WR low. While WR is low, the input track and hold follows the input voltage, AIN. On the rising edge of WR, the input is sampled. The rising edge of WR enables a state machine which steps the ADC through a conversion. The output port is held in high impedance state during the conversion period. The operating timing diagrams are shown in Figure 4. DB0-DB7 Data Valid for Sample N-1 TMSU TMH A0-A2 Mux Address Valid for Sample N Figure 4. Operating Timing Diagrams Analog To Digital Conversion The MP8820 converts analog voltages into 256 digital codes by encoding the outputs of 15 coarse and 15 fine comparators. When WR goes low, the input sample and hold circuitry is enabled. The track and hold circuit will follow the output of the 8 channel mux. The channel that is to be converted does not need to be selected until a time equal to TMSU, or 150 ns, before the rising edge of WR. So, while WR is low, the track and hold circuit only has to follow the analog input to be converted for 150 ns. Rev. 1.00 6 The analog input is sampled at a time equal to the aperture delay, TAP, after the rising edge of WR. The aperture delay also accounts for internal propagation delays. The mux address lines may also select a new channel at a time equal to TAP following the rising edge of WR. For the analog timing diagram, see Figure 5. Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ CODE AIN 00000000 00000001 . . 10000000 . . 11111110 11111111 –FS –FS + 1LSB . . VMID = BZ . . FS – 2LSB FS – 1LSB + Gain Error Table 1. Digital Codes vs. Input Voltage tCONV TIO Data Valid for Sample N MP8820 tWR tMSU tAP AIN1 VIN AIN2 VTAP φC AIN8 φS φS φC C1 Latch clock phase φc. The voltage stored on the capacitor is then equal to VBAL + (VIN – VTAP). This voltage will force the inverter high or low and the result is latched. Figure 6. Comparator Block Diagram Figure 5. Analog Timing Diagram Inside the ADC is a series of comparators that sample the analog input and compare it against a resistor tap voltage. A state machine generates the internal clocks necessary to control the comparators, φc (CLK high) and φs (CLK low = sample). See Figure 6. The rising edge of the CLK input marks the end of the sampling phase, φs. On φs, the analog input voltage is sampled and stored across capacitor C1. The switches controlled by φs are opened prior to the compare which is done on Sample Compare MSBs Compare LSBs Correction Data Data Sample N-1 φSN φCMSBs φCLSBs φCORR Data Sample N The analog to digital conversion happens in four phases. During the first phase, the analog input is sampled. During the second phase, this input is compared against the reference ladder to determine the MSBs. After the MSBs are determined, a subrange is set for phase three, the conversion of the LSBs. Once all the bits have been derived, the MP8820 performs a correction. The valid data is then ready at the output. The timing diagram is shown in Figure 7. φSN+1 Figure 7. Internal ADC Timing Diagram The input mux operates as a standard 8 to 1 decoder. One of eight analog inputs is selected depending on the condition of the address pins A0, A1, and A2. The mux can change address after a time equal to tAP following the rising edge of WR. The address should be held constant for at least 150 ns before the rising edge of WR. Rev. 1.00 ÁÁÁÁ Á ÁÁÁÁ Á Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ Á Á Á Á ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ Á Á Á Á ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ Function WR ↓ ↑ ↑ XINT 1 1 1 A0 X X X X X 0 0 0 0 1 1 1 1 A1 X X X X X 0 0 1 1 0 0 1 1 A2 X X X X X 0 1 0 1 0 1 0 1 Start AIN tracking Sample AIN Start Convert Conversion Complete Enable Output Data Select Input AIN1 Select Input AIN2 Select Input AIN3 Select Input AIN4 Select Input AIN5 Select Input AIN6 Select Input AIN7 Select Input AIN8 1 X X X X X X X X X ↓ 0 X X X X X X X X Table 2. Truth Table 7 MP8820 Graph 1. Supply Current vs. Temperature Graph 2. Input Resistance vs. Temperature Graph 3. Full Scale Error vs. Temperature Graph 4. Bipolar Zero Error vs. Temperature Graph 5. DNL vs. Temperature Rev. 1.00 8 MP8820 Graph 6. DNL Error Plot Graph 7. INL Error Plot for 7-Bit + Sign ADC Rev. 1.00 9 MP8820 28 LEAD SMALL OUTLINE (300 MIL JEDEC SOIC) S28 D 28 15 E H 14 h x 45° C Seating Plane e B A1 L A α INCHES SYMBOL A A1 B C D E e H h L MIN 0.097 0.0050 0.014 0.0091 0.701 0.292 MAX 0.104 0.0115 0.019 0.0125 0.711 0.299 MILLIMETERS MIN 2.464 0.127 0.356 0.231 17.81 7.42 MAX 2.642 0.292 0.483 0.318 18.06 7.59 0.050 BSC 0.400 0.010 0.016 0° 0.410 0.016 0.035 8° 1.27 BSC 10.16 0.254 0.406 0° 10.41 0.406 0.889 8° α Rev. 1.00 10 MP8820 28 LEAD SHRINK SMALL OUTLINE PACKAGE (SSOP) A28 D 28 15 E H 1 14 C Seating Plane e B A1 L A α MILLIMETERS SYMBOL A A1 B C D E e H L MIN 1.73 0.05 0.20 0.13 10.07 5.20 MAX 2.05 0.21 0.40 0.25 10.40 5.38 MIN INCHES MAX 0.081 0.008 0.016 0.010 0.409 0.212 0.068 0.002 0.008 0.005 0.397 0.205 0.65 BSC 7.65 0.45 0° 8.1 0.95 8° 0.0256 BSC 0.301 0.018 0° 0.319 0.037 8° α Rev. 1.00 11 MP8820 NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contains here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 1995 EXAR Corporation Datasheet April 1995 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. Rev. 1.00 12