SP3508
Rugged 3.3V, 20Mbps, 8 Channel Multiprotocol Transceiver with Programmable DCE/DTE and Termination Resistors
FEATURES • Fast 20Mbps Differential Transmission Rates • Internal Transceiver Termination Resistors for V. & V.35 • Interface Modes:
— RS-232 (V.28) — X.2 (V.) — RS-449/V.36 (V.0 & V.)
Now Available in Lead Free Packaging
Refer to page 9 for pinout
— EIA-530 (V.0 & V.) — EIA-530A (V.0 & V.) — V.35 (V.35 & V.28)
• Protocols are Software Selectable with 3-Bit Word • Eight (8) Drivers and Eight (8) Receivers •Termination Network Disable Option • Internal Line or Digital Loopback for Diagnostic Testing • Certified conformance to NET1/NET2 and TBR-1 TBR-2 by TUV Rheinland (TBR2/3045940.00/04) • Easy Flow-Through Pinout • +3.3V Only Operation • Individual Driver and Receiver Enable/Disable Controls •Operates in either DTE or DCE Mode
APPLICATIONS • Router • Frame Relay • CSU • DSU • PBX • Secure Communication Terminals
DESCRIPTION
The SP3508 is a monolithic device that supports eight (8) popular serial interface standards for Wide Area Network (WAN) connectivity. The SP3508 is fabricated using a low power BiCMOS process technology, and incorporates a regulated charge pump allowing +3.3V only operation. Exar's patented charge pump provides a regulated output of +5.5V, which will provide enough voltage for compliant operation in all modes. Eight (8) drivers and eight (8) receivers can be configured via software for any of the above interface modes at any time. The SP3508 requires no additional external components for compliant operation for all of the eight (8) modes of operation other than six capacitors used for the internal charge pump. All necessary termination is integrated within the SP3508 and is switchable when V.35 drivers and V.35 receivers, or when V. receivers are used. The SP3508 provides the controls and transceiver availability for operating as either a DTE or DCE. Additional features with the SP3508 include internal loopback that can be initiated in any of the operating modes by use of the LOOPBACK pin. While in loopback mode, receiver outputs are internally connected to driver inputs creating an internal signal path bypassing the serial communications controller for diagnostic testing. The SP3508 also includes a latch enable pin with the driver and receiver address decoder. The internal V. or V.35 termination can be switched off using a control pin (TERM_OFF) for monitoring applications. All eight (8) drivers and receivers in the SP3508 include separate enable pins for added convenience. The SP3508 is ideal for WAN serial ports in networking equipment such as routers, access concentrators, network muxes, DSU/CSU's, networking test equipment, and other access devices.
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com SP3508_00_072208
ABSOLUTE MAXIMUM RATINGS
VCC ................................................................................................. +7V Input Voltages: Logic ................................................ -0.3V to (VCC+0.5V) Drivers.............................................. -0.3V to (VCC+0.5V) Receivers ............................................................. ±5.5V Output Voltages: Logic ................................................ -0.3V to (VCC+0.5V) Drivers..................................................................... ±2V Receivers ......................................... -0.3V to (VCC+0.5V) Storage Temperature .................................................. -65°C to +50°C Power Dissipation ................................................................... 520mW (derate 9.0mW/°C above +70°C) Junction Temperature TJ ......................................................... +4°C
Package Derating:
øJA ................................................................... 36.9 °C/W øJC ..................................................................... 6.5 °C/W
These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
STORAGE CONSIDERATIONS
Due to the relatively large package size of the 00-pin quad flat-pack, storage in a low humidity environment is preferred. Large high density plastic packages are moisture sensitive and should be stored in Dry Vapor Barrier Bags. Prior to usage, the parts should remain bagged and stored below 40°C and 60%RH. If the parts are removed from the bag, they should be used within 48 hours or stored in an environment at or below 20%RH. If the above conditions cannot be followed, the parts should be baked for four hours at 25°C in order to remove moisture prior to soldering. Exar ships the 00-pin LQFP in Dry Vapor Barrier Bags with a humidity indicator card and desiccant pack. The humidity indicator should be below 30%RH.
ELECTRICAL SPECIFICATIONS
TA = 0 to 70°C and VCC = 3.3V ± 5% unless otherwise noted. The ♦ denotes the specifications which apply over the full operating tempera-
ture range (-40°C to +85°C), unless otherwise specified.
PARAMETER LOGIC INPUTS VIL VIH LOGIC OUTPUTS VOL VOH
MIN.
TYP.
MAX. 0.8
♦ ♦
UNITS V V V V
CONDITIONS
2.0 0.4 VCC - 0.6 VCC - 0.3 +/-0 +/-5.0 +/-00 300 .5 30 0.5 0.5 20 .0 .0 230 3.0 3.0
♦ ♦
IOUT = -3.2mA IOUT = .0mA
V.28 DRIVER DC Parameters (OUTPUTS) Open Circuit Voltage Loaded Voltage Short-Circuit Current Power-Off Impedance Transition Time Instantaneous Slew Rate Propagation Delay: tPHL Propagation Delay: tPLH Max. Transmission Rate V.28 DRIVER AC Parameters (Outputs)
♦ ♦ ♦ ♦ ♦
V V mA Ω µs V/ µs µs µs kbps
Per Figure Per Figure 2 Per Figure 4 Per Figure 5 VCC = 3.3V for AC parameters Per Figure 6, +3V to -3V Per Figure 3
♦ ♦ ♦
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com
SP3508_00_072208
2
ELECTRICAL SPECIFICATIONS
TA = 0 to 70°C and VCC = 3.3V ± 5% unless otherwise noted. The ♦ denotes the specifications which apply over the full operating tempera-
ture range (-40°C to +85°C), unless otherwise specified.
PARAMETER Input Impedance Open-Circuit Bias HIGH Threshold LOW Threshold Propagation Delay: tPHL Propagation Delay: tPLH Max. Transmission Rate Open Circuit Voltage Test-Terminated Voltage Short-Circuit Current Power-Off Current
MIN. 3
TYP.
MAX. 7 +2.0
UNITS
CONDITIONS Per Figure 7 Per Figure 8
V.28 RECEIVER DC Parameters (Inputs)
♦ ♦ ♦ ♦
kΩ V V V
.7 0.8 .2 00 00 20 +/-4.0 0.9VCC 230
3.0
V.28 RECEIVER AC Parameters 500 500 ns ns kbps +/-6.0 +/-50 +/-00 200 00 00 20 -3.25 4 +/-0.3 20 20 20 250 250 +3.25 500 500
VCC = 3.3V for AC parameters
V.10 DRIVER DC Parameters (Outputs)
♦
V V mA
Per Figure 9 Per Figure 0 Per Figure Per Figure 2 VCC = 3.3V for AC parameters Per Figure 3, 0% to 90%
♦ ♦ ♦ ♦ ♦
µA ns ns ns kbps mA
V.10 DRIVER AC Parameters (Outputs) Transition Time Propagation Delay: tPHL Propagation Delay: tPLH Max. Transmission Rate Input Current Input Impedance Sensitivity V.10 RECEIVER AC Parameters Propagation Delay: tPHL Propagation Delay: tPLH Max. Transmission Rate V.10 RECEIVER DC Parameters (Inputs)
Per Figures 4 and 5
♦ ♦ ♦ ♦ ♦
kΩ V VCC = 3.3V for AC parameters ns ns kbps
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com
SP3508_00_072208
3
ELECTRICAL SPECIFICATIONS
TA = 0 to 70°C and VCC = 3.3V ± 5% unless otherwise noted. The ♦ denotes the specifications which apply over the full operating tempera-
ture range (-40°C to +85°C), unless otherwise specified.
PARAMETER Open Circuit Voltage (VOC) Test Terminated Voltage Balance Offset Short-Circuit Current Power-Off Current
MIN.
TYP.
MAX. +/-6.0
UNITS
CONDITIONS Per Figure 6 Per Figure 7 Per Figure 7 Per Figure 7 Per Figure 8 Per Figure 9 VCC = 3.3V for AC parameters Per Figures 2 and 35, 0% to 90% using CL = 50pF Per Figures 32 and 35 Per Figures 32 and 35 Per Figures 32 and 35
V.11 DRIVER DC Parameters (Outputs)
♦ ♦ ♦
V V V V V mA µA ns ns ns ns Mbps V V mA mA
+/-2.0
0.5(VOC)
+/-0.4 +3.0 +/-50 +/-00 0 30 30 5 20 -7 -3.25 +7 +/-0.2 +3.25 +/-60 4 85 85 0
♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦
V.11 DRIVER AC Parameters (Outputs) Transition Time Propagation Delay: tPHL Propagation Delay: tPLH Differential Skew Max. Transmission Rate Common Mode Range Sensitivity Input Current Current with 100Ω Termination Input Impedance V.11 RECEIVER AC Parameters Propagation Delay: tPHL Propagation Delay: tPLH Skew Max. Transmission Rate 20 30 30 5 85 85 0 ns ns ns Mbps V.11 RECEIVER DC Parameters (Inputs)
Per Figures 20 and 22; Power on or off Per Figures 23 and 24
♦
kΩ VCC = 3.3V for AC parameters using CL = 50pF Per Figures 32 and 37 Per Figures 32 and 37 Per Figure 32
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com
SP3508_00_072208
4
ELECTRICAL SPECIFICATIONS
TA = 0 to 70°C and VCC = 3.3V ± 5% unless otherwise noted. The ♦ denotes the specifications which apply over the full operating tempera-
ture range (-40°C to +85°C), unless otherwise specified.
PARAMETER Open Circuit Voltage Test Terminated Voltage Offset Output Overshoot Source Impedance Short-Circuit Impedance Transition Time Propagation Delay: tPHL Propagation Delay: tPLH Differential Skew Max. Transmission Rate Sensitivity Source Impedance Short-Circuit Impedance Propagation Delay: tPHL Propagation Delay: tPLH Skew Max. Transmission Rate Driver Output 3-State Current Receiver Output 3-State Current
MIN.
TYP.
MAX. +/-.20
UNITS V V
CONDITIONS Per Figure 6 Per Figure 25 Per Figure 25 Per Figure 25; VST = Steady State value Per Figure 26; ZS = V2/V x 50 Per Figure 27 VCC = 3.3V for AC parameters
V.35 DRIVER DC Parameters (Outputs) +/-0.44 -0.2VST 50 35 +/-0.66 +/-0.6 +0.2VST 50 65 20 30 30 20 +/-50 90 35 30 30 5 20 200 0 +/-200 0 65 85 85 0 85 85 5
♦ ♦ ♦
V V Ω Ω
V.35 DRIVER AC Parameters (Outputs)
♦ ♦ ♦ ♦ ♦ ♦
ns ns ns ns Mbps mV Ω Ω ns ns ns Mbps µA µA Per Figure 3; Drivers Disabled DX = Per Figure 29; ZS = V2/V x 50Ω Per Figure 30 VCC = 3.3V for AC parameters Per Figures 32 and 37; CL = 20pF Per Figures 32 and 37; CL = 20pF Per Figure 32; CL = 20pF Per Figures 32 and 35; CL = 20pF Per Figures 32 and 35; CL = 20pF Per Figures 32 and 35; CL = 20pF
V.35 RECEIVER DC Parameters (Inputs)
V.35 RECEIVER AC Parameters
TRANSCEIVER LEAKAGE CURRENTS
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com
SP3508_00_072208
5
ELECTRICAL SPECIFICATIONS
TA = 0 to 70°C and VCC = 3.3V ± 5% unless otherwise noted. The ♦ denotes the specifications which apply over the full operating tempera-
ture range (-40°C to +85°C), unless otherwise specified.
PARAMETER POWER REQUIREMENTS VCC ICC (No Mode Selected) (V.28 / RS-232) (V. / RS-422) (EIA-530 & RS-449) (V.35)
MIN. 3.5
TYP. 3.3 95 230 270 70
MAX. 3.45
UNITS V
CONDITIONS
♦ ♦ ♦ ♦ ♦
µA mA mA mA mA
All ICC values are with VCC = +3.3V fIN = 230kbps; Drivers active and loaded fIN = 20Mbps; Drivers active and loaded fIN = 20Mbps; Drivers active and loaded V.35 @ fIN = 20Mbps, V.28 @ fIN = 230kbps
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com
SP3508_00_072208
6
OTHER AC CHARACTERISTICS
TA = 0 to 70°C and VCC = 3.3V ± 5% unless otherwise noted.
PARAMETER RS-232/V.28 tPZL; Tri-state to Output LOW tPZH; Tri-state to Output HIGH tPLZ; Output LOW to Tri-state tPHZ; Output HIGH to Tri-state RS-423/V.10 tPZL; Tri-state to Output LOW tPZH; Tri-state to Output HIGH tPLZ; Output LOW to Tri-state tPHZ; Output HIGH to Tri-state RS-422/V.11 tPZL; Tri-state to Output LOW tPZH; Tri-state to Output HIGH tPLZ; Output LOW to Tri-state tPHZ; Output HIGH to Tri-state V.35 tPZL; Tri-state to Output LOW tPZH; Tri-state to Output HIGH tPLZ; Output LOW to Tri-state tPHZ; Output HIGH to Tri-state RS-232/V.28 tPZL; Tri-state to Output LOW tPZH; Tri-state to Output HIGH tPLZ; Output LOW to Tri-state tPHZ; Output HIGH to Tri-state RS-423/V.10 tPZL; Tri-state to Output LOW tPZH; Tri-state to Output HIGH tPLZ; Output LOW to Tri-state tPHZ; Output HIGH to Tri-state
MIN.
TYP.
MAX.
Units
CONDITIONS
DRIVER DELAY TIME BETWEEN ACTIVE MODE AND TRI-STATE MODE 0.70 0.40 0.20 0.40 0.5 0.20 0.20 0.5 2.80 0.0 0.0 0.0 2.60 0.0 0.0 0.5 5.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 0.0 2.0 2.0 2.0 0.0 2.0 2.0 2.0 µs µs µs µs µs µs µs µs µs µs µs µs µs µs µs µs CL = 00pF, Fig. 33 & 39; S closed CL = 00pF, Fig. 33 & 39; S2 closed CL = 00pF, Fig. 33 & 39; S closed CL = 00pF, Fig. 33 & 39; S2 closed CL = 00pF, Fig. 33 & 39; S closed CL = 00pF, Fig. 33 & 39; S2 closed CL = 00pF, Fig. 33 & 39; S closed CL = 00pF, Fig. 33 & 39; S2 closed CL = 00pF, Fig. 33 & 36; S closed CL = 00pF, Fig. 33 & 36; S2 closed CL = 5pF, Fig. 33 & 36; S closed CL = 5pF, Fig. 33 & 36; S2 closed CL = 00pF, Fig. 33 & 36; S closed CL = 00pF, Fig. 33 & 36; S2 closed CL = 5pF, Fig. 33 & 36; S closed CL = 5pF, Fig. 33 & 36; S2 closed
RECEIVER DELAY TIME BETWEEN ACTIVE MODE AND TRI-STATE MODE 0.2 0.0 0.0 0.0 0.0 0.0 0.0 0.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 µs µs µs µs µs µs µs µs CL = 00pF, Fig. 34 & 37; S closed CL = 00pF, Fig. 34 & 37; S2 closed CL = 00pF, Fig. 34 & 37; S closed CL = 00pF, Fig. 34 & 37; S2 closed CL = 00pF, Fig. 34 & 37; S closed CL = 00pF, Fig. 34 & 37; S2 closed CL = 00pF, Fig. 34 & 37; S closed CL = 00pF, Fig. 34 & 37; S2 closed
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com
SP3508_00_072208
7
OTHER AC CHARACTERISTICS: Continued
TA = 0 to 70°C and VCC = +3.3V unless otherwise noted.
PARAMETER RS-422/V.11 tPZL; Tri-state to Output LOW tPZH; Tri-state to Output HIGH tPLZ; Output LOW to Tri-state tPHZ; Output HIGH to Tri-state V.35 tPZL; Tri-state to Output LOW tPZH; Tri-state to Output HIGH tPLZ; Output LOW to Tri-state tPHZ; Output HIGH to Tri-state
MIN.
TYP. 0.0 0.0 0.0 0.0
MAX. 2.0 2.0 2.0 2.0
UNITS µs µs µs µs
CONDITIONS CL = 00pF, Fig. 34 & 38; S closed CL = 00pF, Fig. 34 & 38; S2 closed CL = 5pF, Fig. 34 & 38; S closed CL = 5pF, Fig. 34 & 38; S2 closed CL = 00pF, Fig. 34 & 38; S closed CL = 00pF, Fig. 34 & 38; S2 closed CL = 5pF, Fig. 34 & 38; S closed CL = 5pF, Fig. 34 & 38; S2 closed (per Figures 32, 35, 37) [ (tPHL )Tx – (tPHL )Txn ] [ (tPLH )Tx – (tPLH )Txn] [ (tPHL )Rx – (tPHL )Rxn ] [ (tPLH )Rx – (tPLH )Rxn ] [ (tPHL)Tx – (tPHL )Txn ] [ (tPLH )Tx – (tPLH )Txn ] [ (tPHL )Rx – (tPHL: )Rxn ] [ (tPLH )Rx – (tPLH )Rxn ] [ (tPHL )Tx2 – (tPHL )Txn ] [ (tPLH )Tx2 – (tPLH )Txn ] [ (tPHL )Rx2 – (tPHL )Rxn ] [ (tPLH )Rx2 – (tPLH )Rxn ] [ (tPHL )Tx – (tPHL )Txn ] [ (tPLH )Tx – (tPLH )Txn ] [ (tPHL )Rx – (tPHL )Rxn ] [ (tPLH )Rx – (tPLH )Rxn]
0.0 0.0 0.0 0.0
2.0 2.0 2.0 2.0
µs µs µs µs
TRANSCEIVER TO TRANSCEIVER SKEW RS-232 Driver RS-232 Receiver RS-422 Driver RS-422 Receiver RS-423 Driver RS-423 Receiver V.35 Driver V.35 Receiver 00 00 20 20 2 2 3 3 5 5 5 5 4 4 6 6 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com
SP3508_00_072208
8
PINOUT
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com
SP3508_00_072208
9
SP3508 Pin Designation Pin Number 2 3 4 5 6 7 8 9 0 2 3 4 5 6 7 8 9 20 2 22 23 24 25 Pin Name GND SDEN TTEN STEN RSEN TREN RRCEN RLEN LLEN# RDEN# RTEN# TxCEN# CSEN# DMEN# RRTEN# ICEN# TMEN D0 D D2 DLATCH# TERM_OFF VCC C3P GND Description Signal Ground TxD Driver Enable Input TxCE Driver Enable Input ST Driver Enabe Input RTS Driver Enable Input DTR Driver Enable Input DCD Driver Enable Input RL Driver Enable Input LL Driver Enable Input RxD Receiver Enabe Input RxC Receiver Enable Input TxC Receiver Enable Input CTS Receiver Enable Input DSR Receiver Enable Input DCDDTE Receiver Enable Input RI Receiver Enable Input TM Receiver Enable Input Mode Select Input Mode Select Input Mode Select Input Decoder Latch Input Termination Disable Input Power Supply Input Charge Pump Capacitor Signal Ground
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com
SP3508_00_072208
0
SP3508 Pin Designation Pin Number 26 27 28 29 30 3 32 33 34 35 36 37 38 39 40 4 42 43 44 45 46 47 48 49 50 Pin Name C3N VSS2 AGND AVCC LOOPBACK# TxD TxCE ST RTS DTR DCD_DCE RL LL RxD RxC TxC CTS DSR DCD_DTE RI TM GND VCC RD(B) RD(A) Description Charge Pump Capacitor Minus VCC Signal Ground Power Supply Input Loopback Mode Enable Input TxD Driver TTL Input TxCE Driver TTL input ST Driver TTL Input RTS Driver TTL Input DTR Driver TTL Input DCDDCE Driver TTL Input RL Driver TTL Input LL Driver TTL Input RxD Receiver TTL Output RxC Receiver TTL Output TxC Receiver TTL Output CTS Receiver TTL Output DSR Receiver TTL Output DCDDTE Receiver TTL Output RI Receiver TTL Output TM Receiver TTL Output Signal Ground Power Supply Input RxD Non-Inverting Input RxD Inverting Input
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com
SP3508_00_072208
SP3508 Pin Designation Pin Number 5 52 53 54 55 56 57 58 59 60 6 62 63 64 65 66 67 68 69 70 7 72 73 74 75 Pin Name RT(B) RT(A) TxC(B) GND TxC(A) CS(B) CS(A) DM(B) DM(A) GNDV0 RRT(B) RRT(A) IC TM(A) LL(A) VCC RL(A) VSS C2N CN GND C2P VCC CP GND Description RxC Non-Inverting Input RxC Inverting Input TxC Non-Inverting Input Signal Ground TxC Inverting Input CTS Non-Inverting Input CTS Inverting Input DSR Non-Inverting Input DSR Inverting Input V.0 RX Reference Node DCDDTE Non-Inverting Input DCDDTE Inverting Input RI Receiver Input TM Receiver Input LL Driver Output Power Supply Input RL Driver Output -2xVCC Charge Pump Output Charge Pump Capacitor Charge Pump Capacitor Signal Ground Charge Pump Capacitor Power Supply Input Charge Pump Capacitor Signal Ground
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com
SP3508_00_072208
2
SP3508 Pin Designation Pin Number 76 77 78 79 80 8 82 83 84 85 86 87 88 89 90 9 92 93 94 95 96 97 98 99 00 Pin Name VDD RRC(B) VCC RRC(A) GND RS(A) VCC RS(B) GND TR(A) VCC TR(B) GND ST(A) VCC ST(B) GND TT(A) VCC TT(B) GND SD(A) VCC SD(B) VCC Description 2xVCC Charge Pump Output DCDDCE Non-Inverting Output Power Supply Input DCDDCE Inverting Output Signal Ground RTS Inverting Output Power Supply Input RTS Non-Inverting Output Signal Ground DTR Inverting Output Power Supply Input DTR Non-Inverting Output Signal Ground ST Inverting Output Power Supply Input ST Non-Inverting Output Signal Ground TxCE Inverting Output Power Supply Input TxCE Non-Inverting Output Signal Ground TxD Inverting Output Power Supply Input TxD Non-Inverting Output Power Supply Input
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com
SP3508_00_072208
3
SP3508 Driver Table
Driver Output Pin MODE (D0, D1, D2) T 1OUT(a) T 1OUT(b) T 2OUT(a) T 2OUT(b) T 3OUT(a) T 3OUT(b) T 4OUT(a) T 4OUT(b) T 5OUT(a) T 5OUT(b) T 6OUT(a) T 6OUT(b) T 7OUT(a) T 8OUT(a) V.35 Mode 001 V.35 V.35 V.35 V.35 V.35 V.35 V.28 High-Z V.28 High-Z V.28 High-Z V.28 V.28 EIA-530 Mode 010 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.10 V.10 RS-232 Mode (V.28) 011 V.28 High-Z V.28 High-Z V.28 High-Z V.28 High-Z V.28 High-Z V.28 High-Z V.28 V.28 EIA-530A Mode 100 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.10 High-Z V.11 V.11 V.10 V.10 RS-449 Mode (V.36) 101 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.10 V.10 X.21 Mode (V.11) 110 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 High-Z High-Z Shutdown 111 High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z TxD(a) TxD(b) TxCE(a) TxCE(b) TxC_DCE(a) TxC_DCE(b) RTS(a) RTS(b) DTR(a) DTR(b) DCD_DCE(a) DCD_DCE(b) RL LL Suggested Signal
Table . Driver Mode Selection
SP3508 Receiver Table
Receiver Input Pin MODE (D0, D1, D2) R 1IN(a) R 1IN(b) R 2IN(a) R 2IN(b) R 3IN(a) R 3IN(b) R 4IN(a) R 4IN(b) R 5IN(a) R 5IN(b) R 6IN(a) R 6IN(b) R 7IN(a) R 8IN(a) V.35 Mode 001 V.35 V.35 V.35 V.35 V.35 V.35 V.28 High-Z V.28 High-Z V.28 High-Z V.28 V.28 EIA-530 Mode 010 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.10 V.10 RS-232 Mode (V.28) 011 V.28 High-Z V.28 High-Z V.28 High-Z V.28 High-Z V.28 High-Z V.28 High-Z V.28 V.28 EIA-530A Mode 100 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.10 High-Z V.11 V.11 V.10 V.10 RS-449 Mode (V.36) 101 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.10 V.10 X.21 Mode (V.11) 110 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 High-Z High-Z Shutdown 111 High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z RxD(a) RxD(b) RxC(a) RxC(b) TxC_DTE(a) TxC_DTE(b) CTS(a) CTS(b) DSR(a) DSR(b) DCD_DTE(a) DCD_DTE(b) RI TM Suggested Signal
Table 2. Receiver Mode Selection
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com SP3508_00_072208
4
TEST CIRCUITS
A
A
VOC
3kΩ
VT
C
C
Figure . V.28 Driver Output Open Circuit Voltage
Figure 2. V.28 Driver Output Loaded Voltage
A
A
7kΩ
VT
O s c illo s c o pe
Is c
C
Scope used f or sle w r ate measurement.
C
Figure 3. V.28 Driver Output Slew Rate
Figure 4. V.28 Driver Output Short-Circuit Current
V C C = 0V
A
Ix
A
±2V
3 kΩ
2 50 0 pF
O s c illo s c o pe
C
C
Figure 5. V.28 Driver Output Power-Off Impedance
Figure 6. V.28 Driver Output Rise/Fall Times
SP3508_00_072208
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com
5
A A I ia
±15V
voc
C C
Figure 7. V.28 Receiver Input Impedance
Figure 8. V.28 Receiver Input Open Circuit Bias
A
A
3.9kΩ
VOC
450Ω
Vt
C
C
Figure 9. V.0 Driver Output Open-Circuit Voltage
Figure 0. V.0 Driver Output Test Terminated Voltage
V C C = 0V
A
A Ix
±0 .2 5V
Is c
C
C
Figure . V.0 Driver Output Short-Circuit Current
Figure 2. V.0 Driver Output Power-Off Current
SP3508_00_072208
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com
6
A
A
I ia
±10V
450Ω
O s c illo s c o pe
C
C
Figure 3. V.0 Driver Output Transition Time
Figure 4. V.0 Receiver Input Current
V. 1 0 R E C E I V E R +3 . 2 5 mA
A
V OCA
3.9kΩ
VOC
V OCB
-1 0 V
-3 V +3 V +1 0 V
B
Ma ximu m Input C urre nt V e rs us Volta ge -3 . 2 5 mA
C
Figure 5. V.0 Receiver Input IV Graph
Figure 6. V. Driver Output Open-Circuit Voltage
A 50Ω VT 50Ω B
A Is a
V OS
B
Is b
C
C
Figure 7. V. Driver Output Test Terminated Voltage
Figure 8. V. Driver Output Short-Circuit Current
SP3508_00_072208
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com
7
V C C = 0V
A
A Ixa
±0 .2 5V
Iia
±1 0V
B
B
C
C
V C C = 0V
A
A
±0 .2 5V
±1 0V
B
Ixb
B
Iib
C
C
Figure 9. V. Driver Output Power-Off Current
Figure 20. V. Receiver Input Current
A 50Ω
O s c illo s c o pe
V. 11 R E C E IV E R +3 . 2 5 mA
50Ω B
-1 0 V
50Ω VE
-3 V +3 V +1 0 V
C
Ma ximu m Input C urre nt V e rs us Volta ge -3 . 2 5 mA
Figure 2. V. Driver Output Rise/Fall Time
Figure 22. V. Receiver Input IV Graph
SP3508_00_072208
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com
8
A
Iia
±6 V
V. 11 R E C E I V E R
w/ O ptio na l C a ble Te rmin a ti on (1 00 W to 15 0 W)
i [mA ] = V [V ] / 0 . 1
100Ω to 150Ω
i [ mA ] = V [V ] - 3 ) / 4. 0 -6 V -3 V +3 V +6 V
B
i [ mA ] = V [ V ] - 3 ) / 4. 0
C
i [mA ] = V [V ] / 0 . 1
Ma x imu m I np u t C u rr en t ve rs us V o ltag e
Figure 24. V. Receiver Input Graph with Termination
A
±6 V
100Ω to 150Ω
Iib
A 50Ω VT 50Ω B VOS
B
C
C
Figure 23. V. Receiver Input Current w/ Termination
Figure 25. V.35 Driver Output Test Terminated Voltage
V1 A 50Ω
2 4kH z , 55 0 mV p-p S ine W a ve
A
V2
B IS C
B
±2V
C
C
Figure 26. V.35 Driver Output Source Impedance
Figure 27. V.35 Driver Output Short-Circuit Impedance
SP3508_00_072208
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com
9
A
A
V1
50Ω
O s c illo s c o pe
50Ω
2 4k H z , 55 0 mV p-p S ine W a ve
50Ω B
V2
50Ω
C
B
C
Figure 28. V.35 Driver Output Rise/Fall Time
Figure 29. V.35 Receiver Input Source Impedance
An y one of the three conditions f or disab ling the dr iver.
A
V CC = 0V
1
1
1
D2
D1
D0
V CC
A IZ S C ±10V
B
Is c
Logic “1”
±2V
B
I ZS C
±10V
C
Figure 30. V.35 Receiver Input Short-Circuit Impedance
Figure 3. Driver Output Leakage Current Test
C L1 TIN B A C L2
P-P )
B A
R OU T 1 5pF
fIN (50% Duty Cycle, 2.5V
Figure 32. Driver/Receiver Timing Test Circuit
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com
SP3508_00_072208
20
O u tpu t U nde r Te s t
5 00 Ω CL
S1
VCC
R ec e ive r O u tpu t CR L
Te s t P o int S1 1K Ω S2
1K Ω VCC
S2
Figure 33. Driver Timing Test Load Circuit
Figure 34. Receiver Timing Test Load Circuit
f > 10 MH z ; tR < 5n s ; tF < 5n s DR I V E R I NP UT DR I V E R O UT P UT DI F F E R E NT I A L O UT P UT VB – VA +3V 0V A B V O+ 0V VO– V O 1 /2 V O tDPLH tDPHL 1 .5 V tPLH tPHL 1 /2 V O 1 .5 V
tR
tF
tSKEW = | tDPLH - tDPHL |
Figure 35. Driver Propagation Delays
Mx o r T x _ E n ab le
+3V 0V
f = 1 MH z ; tR ≤ 1 0n s ; tF ≤ 1 0n s 1 .5 V tZL 2 .3 V O utp ut no rm all y L O W O utp ut no rm all y H IG H 1 .5 V tLZ 0 .5 V 0 .5 V tHZ
A, B
5V V OL V OH
A, B
0V
2 .3 V tZH
Figure 36. Driver Enable and Disable Times
A–B
V 0D2 + V 0D2 – V OH V OL tPLH
f > 10 MH z ; tR < 5n s ; tF < 5n s 0V I NP UT O UT P UT (V OH - V OL )/2 tPHL (V OH - V OL )/2 0V
R E C E I VE R O UT
tSKEW = | tPHL - tPLH |
Figure 37. Receiver Propagation Delays
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com SP3508_00_072208
2
D E C x +3V R x ENABLE 0V
f = 1 MH z ; tR < 10 ns ; tF < 10 ns 1 .5 V tZL 1 .5 V O utp ut no rm all y L O W O utp ut no rm all y H IG H 1 .5 V tLZ 0 .5 V 0 .5 V tHZ
+3. 3 V R E C E I VE R O UT V IL V IH R E C E I VE R O UT 0V
1 .5 V tZH
Figure 38. Receiver Enable and Disable Times
T x _ E n ab le
+3V 0V 0V
f = 6 0k H z ; tR < 1 0 ns ; tF < 10 ns 1 .5 V tZL V OL - 0 .5 V O utp ut LO W 1 .5 V tLZ V OL - 0 .5 V
T OUT V OL
+3V T x _ E n ab le 0V V OH 0V
f = 6 0k H z ; tR < 1 0 ns ; tF < 10 ns 1 .5 V tZH O utp ut H I G H 1 .5 V tHZ V OH - 0 .5 V
T OUT
Figure 39. V.28 (RS-232) and V.0 (RS-423) Driver Enable and Disable Times
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com
SP3508_00_072208
22
Figure 40. Typical V.0 Driver Output Waveform.
Figure 4. Typical V. Driver Output Waveform.
Figure 42. Typical V.28 Driver Output Waveform.
Figure 43. Typical V.35 Driver Output Waveform.
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com
SP3508_00_072208
23
(See pinout assignments for GND and VCC pins)
+3.3V (decoupling capacitor not shown)
C1 C2
1mF 70 72 69
CVDD
1mF 74
1mF
+3.3V
VCC
76
C1+
C1-
C2+
C2-
C3+ C3VSS1
24 26 68 1mF 1mF
C3
VDD
Regulated Charge Pump
CVSS1 CVSS2
29
AVCC
Inverter
VSS2
27 1mF
RD(a) RxD RDEN RD(b) RT(a) RxC RTEN RT(b) TxC(a) TxC TxCEN TxC(b) CS(a) CTS CSEN CS(b) DM(a) DSR DMEN DM(b) RRT(a) DCD_DTE RRTEN RRT(b) IC RI ICEN TM(a) TM TMEN
50
31 97
TxD
39 10 49 52 40 11 51 55 41 12 53 57 91 4 34 81 42 13 56 59 83 5 35 85 43 14 58 62 87 6 36 79 95 3 33 89 99 2 32 93
SD(a) SD(b) SDEN TxCE
TT(a) TT(b) TTEN ST
ST(a) ST(b) STEN RTS
RS(a) RS(b) RSEN DTR
TR(a) TR(b) TREN DCD_DCE RRC(a) RRC(b) RRCEN RL RL(a) RLEN LL LL(a) LLEN
44 15 61 63
77 7 37
45 16
67
8 64 38
46 17
65 9
18 19 20 21 22 30
D0 D1 D2 D-LATCH TERM-OFF LOOPBACK
SP3508
V.10-GND AGND
60 28
RECEIVER TERMINATION NETWORK
V.35 MODE V.11 MODE RX ENABLE 51ohms 51ohms 124ohms
GND
V.35 DRIVER TERMINATION NETWORK
51ohms V.35 MODE TX ENABLE 51ohms 124ohms
Figure 44. Functional Diagram
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com SP3508_00_072208
24
FEATURES The SP3508 contains highly integrated serial transceivers that offer programmability between interface modes through software control. The SP3508 offers the hardware interface modes for RS-232 (V.28), RS449/V.36 (V. and V.0), EIA-530 (V. and V.0), EIA-530A (V. and V.0), V.35 (V.35 and V.28) and X.2(V.). The interface mode selection is done via three control pins, which can be latched via microprocessor control. The SP3508 has eight drivers, eight receivers, and a patented on-board charge pump (5,306,954) that is ideally suited for wide area network connectivity and other multiprotocol applications. Other features include digital and line loopback modes, individual enable/disable control lines for each driver and receiver, fail-safe when inputs are either open or shorted. THEORY OF OPERATION The SP3508 device is made up of ) the drivers 2) the receivers 3) charge pumps 4) DTE/DCE switching algorithm 5) control logic. Drivers The SP3508 has eight enhanced independent drivers. Control for the mode selection is done via a three-bit control word into D0, D, and D2. The drivers are prearranged such that for each mode of operation, the relative position and functionality of the drivers are set up to accommodate the selected interface mode. As the mode of the drivers is changed, the electrical characteristics will change to support the required signal levels. The mode of each driver in the different interface modes that can be selected is shown in Table . There are four basic types of driver circuits – ITU-T-V.28 (RS-232), ITU-T-V.0 (RS-423), ITU-T-V. (RS-422), and CCITT-V.35. The V.28 (RS-232) drivers output singleended signals with a minimum of +5V (with 3kΩ & 2500pF loading), and can operate over 20kbps. Since the SP3508 uses a charge pump to generate the RS-232 output rails, the driver outputs will never exceed +0V. The V.28 driver architecture is similar to Sipex's standard line of RS-232 transceivers. The RS-423 (V.0) drivers are also singleended signals which produce open circuit VOL and VOH measurements of +4.0V to +6.0V. When terminated with a 450Ω load to ground, the driver output will not deviate more than 0% of the open circuit value. This is in compliance of the ITU V.10 specification. The V.10 (RS-423) drivers are used in RS-449/V.36, EIA-530, and EIA-530A modes as Category II signals from each of their corresponding specifications. The V.10 driver can transmit over 20Kbps if necessary. The third type of drivers are V. (RS-422) differential drivers. Due to the nature of differential signaling, the drivers are more immune to noise as opposed to single-ended transmission methods. The advantage is evident over high speeds and long transmission lines. The strength of the driver outputs can produce differential signals that can maintain +2V differential output levels with a load of 100Ω. The strength allows the SP3508 differential driver to drive over long cable lengths with minimal signal degradation. The V. drivers are used in RS-449, EIA-530, EIA-530A and V.36 modes as Category I signals which are used for clock and data. Exar's new driver design over its predecessors allow the SP3508 to operate over 20Mbps for differential transmission. The fourth type of drivers are V.35 differential drivers. There are only three available on the SP3508 for data and clock (TxD, TxCE, and TxC in DCE mode).
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com
SP3508_00_072208
25
FEATURES These drivers are current sources that drive loop current through a differential pair resulting in a 550mV differential voltage at the receiver. These drivers also incorporate fixed termination networks for each driver in order to set the VOH and VOL depending on load conditions. This termination network is basically a “Y” configuration consisting of two 51Ω resistors connected in series and a 124Ω resistor connected between the two 50Ω resistors to GND. Filtering can be done on these pins to reduce common mode noise transmitted over the transmission line by connecting a capacitor to ground. The drivers also have separate enable pins which simplifies half-duplex configurations for some applications, especially programmable DTE/DCE. The enable pins will either enable or disable the output of the drivers according to the appropriate active logic illustrated on Figure 44. The enable pins have internal pull-up and pull-down devices, depending on the active polarity of the receiver, that enable the driver upon power-on if the enable lines are left floating. During disabled conditions, the driver outputs will be at a high impedance 3-state. The driver inputs are both TTL or CMOS compatible. All driver inputs have an internal pull-up resistor so that the output will be at a defined state at logic LOW (“0”). Unused driver inputs can be left floating. The internal pull-up resistor value is approximately 500kΩ. Receivers The SP3508 has eight enhanced independent receivers. Control for the mode s election is done via a three-bit control word that is the same as the driver control word. Therefore, the modes for the drivers and receivers are identical in the application. Like the drivers, the receivers are prearranged for the specific requirements of the synchronous serial interface. As the operating mode of the receivers is changed, the electrical characteristics will change to support the required serial interface protocols of the receivers. Table shows the mode of each receiver in the different 26 interface modes that can be selected. There are two basic types of receiver circuits—ITU-T-V .28 (RS-232) and ITU-T-V., (RS-422). The RS-232 (V.28) receiver is single-ended and accepts RS-232 signals from the RS232 driver. The RS-232 receiver has an operating input voltage range of +5V and can receive signals downs to +3V. The input sensitivity complies with RS-232 and V.28 at +3V. The input impedance is 3kΩ to 7kΩ in accordance to RS-232 and V.28. The receiver output produces a TTL/CMOS signal with a +2.4V minimum for a logic “” and a +0.4V maximum for a logic “0”. The RS-232 (V.28) protocol uses these receivers for all data, clock and control signals. They are also used in V.35 mode for control line signals: CTS, DSR, LL, and RL. The RS-232 receivers can operate over 20kbps. The second type of receiver is a differential type that can be configured internally to s upport ITU-T-V.0 and CCITT-V.35 depending on its input conditions. This receiver has a typical input impedance of 10kΩ and a differential threshold of less than +200mV, which complies with the ITU-T-V.11 (RS-422) specifications. V. receivers are used in RS-449/V.36, EIA-530, EIA-530A and X.2 as Category I signals for receiving clock, data, and some control line signals not covered by Category II V.0 circuits. The differential V. transceiver has improved architecture that allows over 20Mbps transmission rates. Receivers dedicated for data and clock (RxD, RxC, TxC) incorporate internal termination for V.. The termination resistor is typically 120Ω connected between the A and B inputs. The termination is essential for minimizing crosstalk and signal reflection over the transmission line . The minimum value is guaranteed to exceed 100Ω, thus complying with the V. and RS-422 specifications. This resistor is invoked when the receiver is operating as a V. receiver, in modes EIA-530, EIA-530A, RS-449/V.36, and X.2.
SP3508_00_072208
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com
FEATURES The same receivers also incorporate a termination network internally for V.35 applications. For V.35, the receiver input termination is a “Y” termination consisting of two 51Ω resistors connected in series and a 124Ω resistor connected between the two 50Ω resistors and GND. The receiver itself is identical to the V. receiver. The differential receivers can be configured to be ITU-T-V.0 single-ended receivers by internally connecting the non-inverting input to ground. This is internally done by default from the decoder. The non-inverting input is rerouted to V0GND and can be grounded separately. The ITU-T-V.0 receivers can operate over 20Kbps and are used in RS449/V.36, EA-530, EA-530A and X.2 modes as Category II signals as indicated by their corresponding specifications. All receivers include an enable/disable line for disabling the receiver output allowing convenient half-duplex configurations. The enable pins will either enable or disable the output of the receivers according to the appropriate active logic illustrated on Figure 44. The receiver’s enable lines include an internal pull-up or pull-down device, depending on the active polarity of the receiver, that enables the receiver upon power up if the enable lines are left floating. During disabled conditions, the receiver outputs will be at a high impedance state. If the receiver is disabled any associated termination is also disconnected from the inputs. All receivers include a fail-safe feature that outputs a logic high when the receiver inputs are open, terminated but open, or shorted together. For single-ended V.28 and V.0 receivers, there are internal 5kΩ pull-down resistors on the inputs which produces a logic high (“”) at the receiver outputs. The differential receivers have a proprietary circuit that detect open or shorted inputs and if so, will produce a logic HIGH (“”) at the receiver output.
CHARGE PUMP
SP3508 uses an internal capacitive charge pump to generate Vdd and Vss. The design is a patented (5,306,954) four-phased voltage shifting charge pump converters that converts the input voltage of 3.3V to nominal output voltages of +/-6V (Vdd & Vss). SP3508 also includes an inverter block that inverts Vcc to -Vcc (Vss2). There is a free-running oscillator that controls the four phases of the voltage shifting. A description of each phase follows. 4-phased doubler pump Phase 1 -VSS charge storage -During this phase of the clock cycle, the positive side of capacitors C and C2 are initially charged to VCC. C+ is then switched to ground and the charge in C- is transferred to C2-. Since C2+ is connected to VCC, the voltage potential across capacitor C2 is now 2xVCC.
V CC = +3V C VDD
+ – – +
+ 3V C1
+ –
C2
+ –
V DD S tora ge C a p a c ito r V SS1 S tora ge C a p a c ito r
–3 V
–3 V
C VSS1
Figure 45. Charge Pump - Phase .
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com SP3508_00_072208
27
FEATURES Phase 2 -VSS transfer -Phase two of the clock connects the negative terminal of C2 to the VSS storage capacitor and the positive terminal of C2 to ground, and transfers the negative generated voltage to CVSS. This generated voltage is regulated to -5.5V. Simultaneously, the positive side of the capacitor C is switched to VCC and the negative side is connected to ground.
V CC = +3V C VDD C1
+ –
C2
+ –
+ –
– +
V DD S tora ge C a p a c ito r V SS S tora ge C a p a c ito r
–6 V
C VSS1
Figure 46. Charge Pump - Phase 2.
Phase 3
-VDD charge storage -The third phase of the clock is identical to the first phase-the charge transferred in C produces -VCC in the negative terminal of C which is applied to the negative side of the capacitor C2. Since C2+ is at VCC, the voltage potential across C2 is 2xVCC.
V CC = +3V C VDD
+ – – +
+ 3V C1
+ –
C2
+ –
V DD S tora ge C a p a c ito r V SS1 S tora ge C a p a c ito r
–3 V
–3 V
C VSS1
Figure 47.Charge Pump - Phase 3.
Phase 4 -VDD transfer -The fourth phase of the clock connects the negative terminal of C2 to ground, and transfers the generated 5.5V across C2 to CVDD, the VDD storage capacitor. This voltage is regulated to +5.5V. At the regulated voltage, the internal oscillator is disabled and simultaneously with this, the positive side of capacitor C is switched to VCC and the negative side is connected to ground, and the cycle begins again. The charge pump cycle will continue as long as the operational conditions for the internal oscillator are present. Since both V+ and V- are separately generated from VCC; in a no-load condition V+ and V- will be symmetrical. Older charge pump approaches that generate V- from V+ will show a decrease in the magnitude of V- compared to V+ due to the inherent inefficiencies in the design. The clock rate for the charge pump typically operates at 250kHz. The external capacitors can be as low as µF with a 6V breakdown voltage rating.
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com SP3508_00_072208
28
FEATURES
V CC = +3V C VDD
+ – – +
+ 6V C1
+ –
C2
+ –
V DD S tora ge C a p a c ito r V SS1 S tora ge C a p a c ito r
C VSS1
Figure 48. Charge Pump - Phase 4.
2-phased inverter pump Phase 1 Please refer to figure below: In the first phase of the clock cycle, switches S2 and S4 are opened and S1 and S3 closed. This connects the flying capacitor, C3, from Vin to ground. C3 charge up to the input voltage applied at Vcc. Phase 2 In the second phase of the clock cycle, switches S2 and S4 are closed and S and S3 are opened. This connects the flying capacitor, C3, in parallel with the output capacitor, CVSS2. The Charge stored in C3 is now transferred to CVSS2. Simultaneously, the negative side of CVSS2 is connected to VSS2 and the positive side is connected to ground. With the voltage across CVSS2 smaller than the voltage across C3, the charge flows from C3 to CVSS2 until the voltage at the VSS2 equals -VCC.
V SS2 = -V CC V CC S1 C3
+
S2
+
C VSS2 S3
Figure 49. Circuit for an Ideal Voltage Inverter.
S4
V SS2
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com
SP3508_00_072208
29
V.28 V.28 V.28 V.28 V.28 V.28 V.28 V.28 V.28 CF CE TM BA DA CC 6 8 22 25 2 24 CB 5 DB 15
DD
17
V.28 V.28 V.28 V.10 V.11 V.11 V.11 V.11 TM BA(A) BA(B) DA(A) DA(B) 25 2 12 24 11 V.10 V.11 V.11 V.11 V.11 TM SD(A) SD(B) TT(A) TT(B) 18 4 22 17 35 V.28 V.35 V.35 V.35 V.35
107 109 125 142 103 103 113 113
E
F
Driver_7
J
Receiver_1 Receiver_2 Receiver_3 Receiver_4 Receiver_5 Receiver_6 Receiver_7 Receiver_8
RD(A) RD(B) RT(A) RT(B) TxC(A) TxC(B) CS(A) CS(B) DM(A) DM(B) RRT(A) RRT(B) IC TM(A) 64
50 49 52 51 55 53 57 56 59 58 62 61 63
P S U W V.28 V.28 CA CD 4 20 V.11 V.11 V.11 V.11 V.28 V.28 RL LL 21 18 V.10 V.10 CA(A) CA(B) CD(A) CD(B) RL LL 4 19 20 23 21 18 V.11 V.11 V.11 V.11 V.10 V.10 RS(A) RS(B) TR(A) TR(B) RL LL 7 25 12 30 14 10 V.28 V.28 105 108
V.11 V.11 V.11 V.11
T(A) T(B) X(A) X(B)
2 9 7** 14**
C
H
V.11 V.11
C(A) C(B)
3 10
V.28 V.28 Pin assignments and signal functions are subject to national or regional variation and proprietary / non-standard implementations
140 141
N
L
Spare drivers and receivers may be used for optional signals (Signal Quality, Rate Detect, Standby) or may be disabled using individual enable pins for each driver and receiver
** X.21 use either B() or X(), not both
30
Driver_8
LL(A)
65
NN
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com
Interface to System Logic Pin Number Pin Mnemonic 31 TxD 2 SDEN 32 TxCE 3 TTEN 33 ST 4 STEN 34 RTS 5 RSEN 35 DTR 6 TREN 36 DCD_DCE 7 RRCEN 37 RL 8 RLEN 38 LL 9 LLEN# 39 RxD 10 RDEN# 40 RxC 11 RTEN# 41 TxC 12 TxCEN# 42 CTS 13 CSEN# 43 DSR 14 DMEN# 44 DCD_DTE 15 RRTEN# 45 RI 16 ICEN# 46 TM 17 TMEN Pin Mnemonic SD(A) SD(B) TT(A) TT(B) ST(A) ST(B) RS(A) RS(B) TR(A) TR(B) RRC(A) RRC(B) RL(A) RS-232 or V.24 Signal Mnemo DB-25 Type nic Pin(F) V.28 BB 3 Signal Type V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11
SP3508 Multiprotocol Configured as DCE Interface to PortConnector Pin Circuit Number Driver_1 97 99 Driver_2 93 95 Driver_3 89 91 Driver_4 81 83 Driver_5 85 87 Driver_6 79 77 67 EIA-530 Mnemo DB-25 nic Pin(F) BB(A) 3 BB(B) 16 DD(A) 17 DD(B) 9 DB(A) 15 DB(B) 12 CB(A) 5 CB(B) 13 CC(A) 6 CC(B) 22 CF(A) 8 CF(B) 10
Recommended Signals and Port Pin Assignments Signal Type V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 RS-449 Mnemo DB-37 nic Pin(F) RD(A) 6 RD(B) 24 RT(A) 8 RT(B) 26 ST(A) 5 ST(B) 23 CS(A) 9 CS(B) 27 DM(A) 11 DM(B) 29 RR(A) 13 RR(B) 31 Signal Type V.35 V.35 V.35 V.35 V.35 V.35 V.28
V.35 Mnemo M34 nic Pin(F) 104 R 104 T 115 V 115 X 114 Y 114 AA 106 D
Signal Type V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11
X.21 Mnemo DB-15 nic Pin(F) R(A) 4 R(B) 11 B(A) 7** B(B) 14** S(A) 6 S(B) 13 I(A) 5 I(B) 12
SP3508_00_072208
DCE CONFIGURATION
DTE CONFIGURATION
Interface to System Logic RS-232 or V.24 Signal Mnemo DB-25 Type nic Pin(M) V.28 BA 2 V.28 DA 24 Signal Type V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 20 21 LL BB V.28 V.28 V.28 V.28 V.28 V.28 TM(A) 64 V.28 DD DB CB CC CF CE TM 18 3 17 15 5 6 8 22 25 V.10 V.10 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.10 CA(A) CA(B) CD(A) CD(B) RL LL BB(A) BB(B) DD(A) DD(B) DB(A) DB(B) CB(A) CB(B) CC(A) CC(B) CF(A) CF(B) TM 4 19 20 23 21 18 3 16 17 9 15 12 5 13 6 22 8 10 25 Mnemo DB-25 nic Pin(M) BA(A) 2 BA(B) 12 DA(A) 24 DA(B) 11 EIA-530 Signal Type V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.10 V.10 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.10 Pin Number 31 2 32 3 33 4 34 5 35 6 36 7 37 8 38 9 39 10 40 11 41 12 42 13 43 14 44 15 45 16 46 17 Pin Mnemonic TxD SDEN TxCE TTEN ST STEN RTS RSEN DTR TREN DCD_DCE RRCEN RL RLEN LL LLEN# RxD RDEN# RxC RTEN# TxC TxCEN# CTS CSEN# DSR DMEN# DCD_DTE RRTEN# RI ICEN# TM TMEN Driver_2 Driver_3 Driver_4 Driver_5 Driver_6 Driver_7 Driver_8 Receiver_1 Receiver_2 Receiver_3 Receiver_4 Receiver_5 Receiver_6 Receiver_7 Receiver_8 RD(A) RD(B) RT(A) RT(B) TxC(A) TxC(B) CS(A) CS(B) DM(A) DM(B) RRT(A) RRT(B) IC 50 49 52 51 55 53 57 56 59 58 62 61 63 V.28 LL(A) 65 V.28 V.28 RL V.28 CD V.28 CA 4 Circuit Driver_1 Pin Mnemonic SD(A) SD(B) TT(A) TT(B) ST(A) ST(B) RS(A) RS(B) TR(A) TR(B) RRC(A) RRC(B) RL(A) Spare drivers and receivers may be used for optional signals (Signal Quality, Rate Detect, Standby) or may be disabled using individual enable pins for each driver and receiver Pin Number 97 99 93 95 89 91 81 83 85 87 79 77 67 SP3508 Multiprotocol Configured as DTE Interface to PortConnector Recommended Signals and Port Pin Assignments RS-449 Mnemo DB-37 nic Pin(M) SD(A) 4 SD(B) 22 TT(A) 17 TT(B) 35 RS(A) RS(B) TR(A) TR(B) RL LL RD(A) RD(B) RT(A) RT(B) ST(A) ST(B) CS(A) CS(B) DM(A) DM(B) RR(A) RR(B) TM 7 25 12 30 14 10 6 24 8 26 5 23 9 27 11 29 13 31 18 Signal Type V.35 V.35 V.35 V.35 V.28 V.28
V.35
X.21
105
C
108
H
V.11 V.11
C(A) C(B)
3 10
V.28 V.28 V.35 V.35 V.35 V.35 V.35 V.35 V.28 V.28 V.28 V.28 V.28
140
N
141
L
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com
Mnemo M34 nic Pin(M) 103 P 103 S 113 U 113 W
Signal Type V.11 V.11 V.11 V.11
Mnemo DB-15 nic Pin(M) T(A) 2 T(B) 9 X(A) 7** X(B) 14**
SP3508_00_072208
104 104 115 115 114 114 106
R T V X Y AA D
107
E
V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11
R(A) R(B) B(A) B(B) S(A) S(B) I(A) I(B)
4 11 7** 14** 6 13 5 12
109
F
125
J
142 Pin assignments and signal functions are subject to national or regional variation and proprietary / non-standard implementations
NN
** X.21 use either B() or X(), not both
3
FEATURES TERM_OFF FUNCTION The SP3508 contains a TERM_OFF pin that disables all three receiver input termination networks regardless of mode. This allows the device to be used in monitor mode applications typically found in networking test equipment. The TERM_OFF pin internally contains a pull-down device with an impedance of over 500kΩ, which will default in a "ON" condition during power-up if V.35 receivers enable line and the SHUTDOWN mode from the decoder will disable the termination regardless of TERM_OFF. LOOPBACK FUNCTION The SP3508 contains a LOOPBACK pin that invokes a loopback path. This loopback path is illustrated in Figure 50. LOOPBACK has an internal pull-up resistor that defaults to normal mode during power up or if the pin is left floating. During loopback, the driver output and receiver input characteristics will still adhere to its appropriate specifications. DECODER AND D_LATCH FUNCTION The SP3508 contains a D_LATCH pin that latches the data into the D0, D and D2 decoder inputs. If tied to a logic LOW ("0"), the latch is transparent, allowing the data at the decoder inputs to propagate through and program the SP3508 accordingly. If tied to a logic HIGH ("1"), the latch locks out the data and prevents the mode from changing until this pin is brought to a logic LOW. There are internal pull-up devices on D0, D and D2, which allow the device to be in SHUTDOWN mode ("111") upon power up. However, if the device is powered-up with the D_LATCH at a logic HIGH, the decoder state of the SP3508 will be undefined. CTR1/CTR2 EUROPEAN COMPLIANCY As with all of Exar's previous multi-protocol serial transceiver IC's the drivers and receivers have been designed to meet all the requirements to NET/NET2 and TBR2 in order to meet CTR/CTR2 compliancy. The SP3508 is also tested in-house at Exar and adheres to all the NET/2 physical layer testing and the ITU Series V specifications before shipment. Please note that although the SP3508, as with its predecessors, adhere to CRT/CTR2 compliancy testing, any complex or usual configuration should be double-checked to ensure CTR/CTR2 compliance. Consult the factory for details.
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com
SP3508_00_072208
32
97 TxD 31 99 50 RxD 39 49 93 TxCE 32 95 52 RxC 40 51 89 ST 33 91 55 TxC 41 53 81 R TS 34 83 57 CTS 42 56 85 DTR 35 87 59 DSR 43 58 79 DCD_DCE 36 77 62 DCD_DTE 44 61
SD(a) SD(b) RD(a) RD(b) TT(a) TT(b) R T(a) R T(b) ST(a) ST(b) TxC(a) TxC(b) RS(a) RS(b) CS(a) CS(b) TR(a) TR(b) DM(a) DM(b) RRC(a) RRC(b) RR T(a) RR T(b)
RL
37
67
RL(a)
RI
45
63
IC
LL
38
65
LL(a)
TM
46
64
TM(a)
Figure 50. Loopback Path
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com SP3508_00_072208
33
CVDD
C1 1mF
C2 1mF
+3.3V
10mF
VCC
1mF
VDD
76 74
C1+
C1- C2+ C2-C3+ 24 C3- 26 VSS1
70 72
69
68
1mF C3 CVSS1 CVSS2
+3.3V
29 AV CC 31 32 33 34 35 TxD TxCE ST RTS DTR
Charge Pump Section
Transceiver Section SD(a) 97
VSS2
27
mDB-26 Serial Port Connector Pins
2 (V.11, V.35, V.28) 14 (V.11, V.35) 24 (V.11, V.35, V.28) 11 (V.11, V.35) 4 (V.11, V.28) 19 (V.11) 20 (V.11, V.28) 23 (V.11) 21 (V.10, V.28) 18 (V.10, V.28) 3 (V.11, V.35, V.28) 16 (V.11, V.35) 17 (V.11, V.35, V.28) 9 (V.11, V.35) 15 (V.11, V.35, V.28) 12 (V.11, V.35) 5 (V.11, V.28) 13 (V.11) 6 (V.11, V.28) 22 (V.11) 8 (V.11, V.28) 10 (V.11) 22 (V.10, V.28) 25 (V.10, V.28) TXD_RXD_A TXD_RXD_B TXCE_TXC_A TXCE_TXC_B RTS_CTS_A RTS_CTS_B DTR_DSR_A DTR_DSR_B RL_RI LL_TM RXD_TXD_A RXD_TXD_B RXC_TXCE_A RXC_TXCE_B *TXC_RXC_A *TXC_RXC_B CTS_RTS_A CTS_RTS_B DSR_DTR_A DSR_DTR_B DCD_DCD_A DCD_DCD_B RI_RL LL_TM
Signal (DTE_DCE)
SD(b) 99 TT(a) 93 TT(b) 95 ST(a) 89 ST(b) 91
RS(a) 81 RS(b) 83 TR(b) 87 RRC(a) 79 RRC(b) 77 RL(a) 67 LL(a)65 RD(a) 50 RD(b) 49 RT(a) 52 RT(b) 51 TxC(a) 55 TxC(b) 53 CS(a) 57 CS(b) 56 DM(a) 59 DM(b) 58 TR(a) 85
36 DCD_DCE 37 38 39 40 41 42 43 RL LL RxD RxC TxC CTS DSR
44 DCD_DTE 45 46 RI TM
SDEN TTEN STEN RSEN TREN RRCEN RLEN LLEN RDEN RTEN TxCEN CSEN DMEN RRTEN ICEN TMEN Logic Section
RRT(a) 62 RRT(b) 61 IC 63 TM(a) 64
D0 D2 18 19 20 21 22 30
+3.3V
DCE/DTE
2 3 4 5 6 7 8 9 11 12 13 14 15 16 17 10
SP3508CF D1
TERM_OFF D_LATCH LOOPBACK
+3.3V
AGND GND
28
* - Driver applies for DCE only on pins Receiver applies for DTE only on pins Driver applies for DCE only on pins 8 Receiver applies for DTE only on pins
15 and 12. 15 and 12. and 10. 8 and 10.
Input Line Output Line I/O Lines represented by double arrowhead signifies a bi-directional bus.
Figure 51. SP3508 Typical Operating Configuration to Serial Port Connector with DCE/DTE programmability
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com
SP3508_00_072208
34
PACKAGE: 100 PIN LQFP
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com
SP3508_00_072208
35
ORDERING INFORMATION
Part Number Temperature Range Package Types SP3508CF-L........................................... 0°C to +70°C .................................................. 00–pin JEDEC LQFP SP3508EF-L ........................................ -40°C to +85°C .................................................. 00–pin JEDEC LQFP
REVISION HISTORY
Date /2/04 2/27/04 3/3/04 6/03/04 0/2/04 0/29/04 7/7/08 Revision A B C D E F .0.0 Description Implemented Tracking revision Included Diamond column in spec table inidcating which specs apply over full operating temperature range. Correct typo to Fig. 5 pin 6 and 62. Corrected max dimension for symbol c on LQFP package outline Added table to page 27 and 28 Certified conformance to NET1/NET2 and TBR-1/TBR-2 TUV by TUV Rheinland (Test report # TBR2/3045940.00/04) Corrected V.28 Driver Open circuit values, pages 27 and 28 -- both for DCE and DTE that BA(B) should connect to pin 4. Change Revision format from letter code to number code. Change Logo, footnote and notice statement from Sipex to Exar. Add TJ limits to Absolute Maximum Ratings. Change propagation delay limit specification for V.11 and V.35 Driver/Receiver from 60ns Maximum to 85ns Maximum. Update ordering information to show only RoHS packaging (-L) is available.
Notice EXAR Corporation reserves the right to make changes to any products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no representation that the circuits are free of patent infringement. Charts and schedules contained herein are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writting, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized ; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2008 EXAR Corporation Datasheet July 2008 Send your Interface technical inquiry with technical details to: uarttechsupport@exar.com Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (50)668-707 • www.exar.com
SP3508_00_072208
36
工商网监
湘ICP备2023018690号
