SP510CM

SP510 ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER DECEMBER 2009 REV. 1.0.0 GENERAL DESCRIPTION The SP510 is a highly integrated physical layer solution that is configurable to support multiple serial standards. It incorporates eight (8) drivers and eight (8) receivers, configurable for either differential (V.11 or V.35) or single ended (V.28 and V.10) signaling. The device architecture is designed to support the data and clock signals used in HDLC or SDLC serial ports as either a DTE or DCE. SP510 enables a Serial Communications Controller (SCC) to implement a variety of serial port types including V.24, V.25, V.36, EIA-530, EIA-530-A, X.21, RS-232. Operating configuration is in-system programmable using the mode-select pins. The V.11 and V.35 modes contain built in bus termination that may be switched in or out using the TERM_OFF pin. SP510 is ideal for space constrained applications. It requires only a single 5V supply for full operation. The VL pin determines the receiver output voltage (VOH). For single supply operation at 5V the VL pin may be connected to VCC. Fully compliant V.28 and V.10 driver output voltages are generated using onboard charge pumps. Special power sequencing is not required during system startup. Charge pump outputs are internally regulated to minimize power consumption. The SP510 requires only four 1µF capacitors for complete functionality. The device may be put into a 1µA low power shutdown mode when not in active use. All receivers have fail-safe protection to put outputs into a known state when inputs are open, terminated but open or shorted. TYPICAL APPLICATIONS FEATURES • 52Mbps Differential Transmission Rates • Adjustable Logic Level Pin (Down to 1.65V) • +/-15kV ESD Tolerance for Analog I/O’s • Internal Transceiver Termination Resistors for V.11/ V.35 • Interface Modes: ■ ■ ■ ■ ■ RS-232 (V.28) EIA-530 (V.10 & V.11) X.21 (V.11) EIA-530A (V.10 & V.11) RS-449/V.36 • Software Selectable Protocols with 3-Bit Word • Eight Drivers and Eight Receivers • V.35/V.11 Receiver Termination Network Disable Option • Internal Line or Digital Loopback Testing • Adheres to NET1/NET2 and TBR2 Requirements • Easy Flow-Through Pinout • Single +5V Supply Voltage • Individual Driver/Receiver Enable/Disable Controls • Operates in DTE or DCE Mode • Data Communication Networks • Telecommunication Equipment • Secured Data Communication • CSU and DSU • Data Routers • Network Switches • WAN Access Equipment • VoIP-PBX Gateways ORDERING INFORMATION PART NUMBER SP510EM SP510CM PACKAGE 100-pin LQFP 100-pin LQFP OPERATING TEMPERATURE RANGE -40°C to +85°C 0°C to +70°C DEVICE STATUS Active Active Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com SP510 ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER ABSOLUTE MAXIMUM RATINGS These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. Supply Voltage (Vcc)……………...+ 7.0V Logic-Interface Voltage (VL)………. VL ≤ Vcc Input voltage at TTL input pins ... - 0.3V to VL+0.5V Receiver Input voltage….. ………..±15.5V Driver output (from Ground)…… -7.5V to +12.5V Short Circuit Duration, TxOUT to GND, Continuous RECOMMENDED OPERATING CONDITIONS Supply Voltage (Vcc)... 4.75V to 5.25V Logic-Interface Supply Voltage (VL)…..1.65V to 5.25V Operating Temperature Range……-40° C to +85° C REV. 1.0.0 Continuous Power Dissipation at Ta = +70° C 100-Pin QFP…………………….…1520 mW (derate 19.0 mW / °C above 70° C) ΘJA 52.7 °C/W, ΘJC 6.5 °C/W Storage Temperature………...-65°C to +150°C Lead Temperature (soldering, 10s)….. 300° C 2 SP510 REV. 1.0.0 ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER TABLE 1: DC ELECTRICAL CHARACTERISTICS DC ELECTRICAL CHARACTERISTICS Vcc = +4.75V to +5.25V, C1-C4 = 1µF. TAMB = TMIN to TMAX, unless otherwise noted. Typical values are at TAMB = +25°C PARAMETERS Vcc Supply Voltage Logic Interface Voltage ICC Shutdown ICC Supply Current SYMBOL VCC VL ICCSD ICC DRIVER INPUT AND LOGIC INPUT PINS Logic Input High Logic Input Low VIH VIL RECEIVER OUTPUTS Receiver Logic Output Low Receiver Logic Output High Receiver Output Short-Circuit Current Receiver Output Leakage Current VOL VOH IOSS IOZ IOUT = -3.2 mA IOUT = 1 mA 0V < VO < VCC Receivers disabled. 0.4V < VO < 5.25V V.28 / RS-232 DRIVERS Output Voltage Swing VT VOC Short Circuit Current Power-Off Impedance ISC Output load = 3kΩ to GND Fig. 3 Output load = Open Circuit Fig.2 VOUT = 0V, Fig 5 Fig. 6 V.28 / RS-232 RECEIVERS Input Voltage Range Input Threshold Low Input Threshold High Input Hysteresis Input Resistance Open Circuit Bias VOC Fig. 8 Fig. 9 3 -15 0.8 1.2 1.7 500 5 7 ±2.0 3.0 15 V V V mV kΩ V 300 ±5.0 ±6.0 ±15.0 ±15.0 ±100 V V mA Ω VL - 0.3 ±20 ±0.05 0.4 VL + 0.3 ±60 ±1 V V mA 2.0 0.4 V V VCC ≥ VL TEST CONDITIONS MIN. 4.75 1.65 200 300 TYP MAX 5.25 5.25 UNIT V V µA mA µA 3 SP510 ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER DC ELECTRICAL CHARACTERISTICS Vcc = +4.75V to +5.25V, C1-C4 = 1µF. TAMB = TMIN to TMAX, unless otherwise noted. Typical values are at TAMB = +25°C PARAMETERS SYMBOL TEST CONDITIONS V.10 / RS-423 DRIVERS Open Circuit Voltage Test Terminated Voltage Short Circuit Current Power-Off Current VOC VT ISC Fig.10 Fig. 11 Fig. 12 Fig. 13 V.10 / RS-423 RECEIVERS Input Current Input Impedance Sensitivity V.11 / RS-422 DRIVERS Open Circuit Voltage VOC, VOCA, VOCB VT ∆VT VOS ∆VOS ISA, ISB Fig. 17 ±6.0 V IIA Fig. 15 and 16 -3.25 4 15 ±0.2 +3.25 mA kΩ V ±4.0 0.9 VOC ±150 ±100 ±6.0 V V mA MIN. TYP MAX UNIT REV. 1.0.0 µA Test Terminated Voltage Balance Driver DC Offset Offset Balance Short Circuit Output Current Power-Off Current Fig. 18 Fig. 18 Fig. 18 Fig. 18 Fig. 19 Fig. 20 V.11 / RS-422 RECEIVERS ±2.0 ±0.4 +3.0 ±0.4 ±150 ±100 V V V V mA µA Receiver Input Range Input Current Input Current with Termination Receiver Input Impedance Receiver Sensitivity Receiver Input Hysteresis VCM IIA, IIB IIA, IIB RIN VTH ∆VTH VCM = 0 V Fig. 21 and 23 Fig. 24 and 25 -10V ≤ VCM ≤ +10V -7 +7 ±3.25 ±60.75 V mV mA kΩ 4 15 ±200 15 mV mV V.35 DRIVERS (ALL VALUES MEASURE WITH TERM_OFF = ’0’) Test Terminated Voltage Offset Output Overshoot Source Impedance VT VOS Fig. 26 Fig. 26 Fig. 26, VST = Steady State Voltage Fig. 29, ZS = V2 / V1 x 50Ω -0.2VST 50 ±0.44 ±0.66 ±0.6 +0.2VST 150 V V V Ω 4 SP510 REV. 1.0.0 ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER DC ELECTRICAL CHARACTERISTICS Vcc = +4.75V to +5.25V, C1-C4 = 1µF. TAMB = TMIN to TMAX, unless otherwise noted. Typical values are at TAMB = +25°C PARAMETERS Short Circuit Impedance SYMBOL TEST CONDITIONS Fig. 28 MIN. 135 TYP MAX 165 UNIT Ω V.35 RECEIVERS (ALL VALUES MEASURE WITH TERM_OFF = ’0’) Sensitivity Source Impedance Short-Circuit Impedance Fig. 30, ZS = V2 / V1 x 50Ω Fig. 31 TRANSCEIVER LEAKAGE CURRENT Driver Output 3-state Current Receiver Output 3-state Current Drivers disabled, per Fig. 32 Tx and Rx Disabled, 0.4V - Vo - 2.4V 500 1 10 90 135 ±100 ±200 110 165 mV Ω Ω µA µA 5 SP510 ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER TABLE 2: AC TIMING CHARACTERISTICS TIMING CHARACTERISTICS VCC = +4.75 to 5.25V, C1-C4 = 1µF; TAMB = TMIN to TMAX, unless noted. Typical values are at TAMB = +25°C. PARAMETERS SYMBOL TEST CONDITIONS V.28 / RS-232 Maximum Transmission Rate Driver Propagation Delay tDPHL, tDPLH +3V to -3V, -3V to +3V per Fig. 7 +3V to -3V, -3V to +3V per Fig. 4 Fig. 7 250 0.5 1 5 kbps MIN. TYP MAX UNIT REV. 1.0.0 µs µs V/µs ns Transition Time Instantaneous Slew Rate Driver Skew 0.2 4 100 1.5 30 800 | tDPHL - tDPLH| at zero crossing Driver Channel to Channel Skew Driver Output Enable Time Tri-state to output Low Driver Output Enable Time Tri-state to output High Driver Output Disable Time Output Low to Tri-state Driver Output Disable Time Output High to Tri-state Receiver Propagation Delay Receiver Skew Receiver Output Rise / Fall Time Receiver Output Enable Time Tri-state to output Low Receiver Output Enable Time Tri-state to output High Receiver Output Disable Time Output Low to Tri-state Receiver Output Disable Time Output High to Tri-state Charge Pump Rise Time tR, tF tZL tZH tLZ tHZ tZL tZH tLZ tHZ tPHL, tPLH CL = 100 pF, Fig. 34 and 40, S1 closed CL = 100 pF, Fig. 34 and 40, S2 closed CL = 15 pF, Fig. 34 and 40, S1 closed CL = 15 pF, Fig. 34 and 40, S2 closed R_IN to R_OUT, CL = 15 pF 50 20 2.0 2.0 2.0 20 100 50 15 2.0 2.0 2.0 500 ns µs µs µs µs ns ns ns | tPHL - tPLH| at 1.5V CL = 15 pF CL = 100 pF, Fig. 35 and 40, S1 closed CL = 100 pF, Fig. 35 and 40, S2 closed CL = 15 pF, Fig. 35 and 40, S1 closed CL = 15 pF, Fig. 35 and 40, S2 closed Shutdown to normal operation V.10 / RS-423 µs µs µs µs ms 2.0 2 Maximum Transmission Rate 250 kbps 6 SP510 REV. 1.0.0 ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER TIMING CHARACTERISTICS VCC = +4.75 to 5.25V, C1-C4 = 1µF; TAMB = TMIN to TMAX, unless noted. Typical values are at TAMB = +25°C. PARAMETERS Driver Propagation Delay Driver Rise / Fall Time Driver Skew SYMBOL tPHL, tPLH tR, tF 10% to 90% - Fig. 14 TEST CONDITIONS MIN. 30 TYP 150 MAX 500 500 100 UNIT ns ns ns | tDPHL - tDPLH| at zero crossing tZL tZH tLZ tHZ tPHL, tPLH tZL tZH tLZ tHZ tR, tF CL = 100 pF, Fig. 35 and 40, S1 closed CL = 100 pF, Fig. 35 and 40, S2 closed CL = 15 pF, Fig. 35 and 40, S1 closed CL = 15 pF, Fig. 35 and 40, S1 closed CL = 15 pF 15 5 CL = 100 pF, Fig. 34 and 40, S1 closed CL = 100 pF, Fig. 34 and 40, S2 closed CL = 15 pF, Fig. 34 and 40, S1 closed CL = 15 pF, Fig. 34 and 40, S2 closed 100 Driver Output Enable Time Tri-state to Output Low Driver Output Enable Time Tri-state to Output High Driver Output Disable Time Output Low to Tri-state Driver Output Disable Time Output High to Tri-state Receiver Propagation Delay Receiver Output Enable Time Tri-state to output Low Receiver Output Enable Time Tri-state to output High Receiver Output Disable Time Output Low to Tri-state Receiver Output Disable Time Output High to Tri-state Receiver Output Rise / Fall Time Receiver Skew 2 2 2 2 500 2 2 2 µs µs µs µs ns µs µs µs ns ns | tPHL - tPLH| at 1.5V HIGH SPEED V.11 / RS-422 (DRIVERS 1, 2 & 3, RECEIVERS 1, 2 & 3) NRZI Encoding tR, tF tDPHL, tDPLH Fig. 22 and 36, 10-90% Fig. 33 and 36, CL = 50 pF 52 0.5 Maximum Bit Rate Driver Rise and Fall Time Propagation Delay Time Mbps 6 5 25 ns ns Differential Skew Driver Output Enable Time Tri-state to Output Low Driver Output Enable Time Tri-state to Output High Driver Output Disable Time Output Low to Tri-state tZL tZH tLZ | tDPHL - tDPLH| CL = 100 pF, Fig. 34 and 37, S1 closed CL = 100 pF, Fig. 34 and 37, S2 closed CL = 15 pF, Fig. 34 and 37, S1 closed 3.8 100 100 100 ns ns ns ns 7 SP510 ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER TIMING CHARACTERISTICS VCC = +4.75 to 5.25V, C1-C4 = 1µF; TAMB = TMIN to TMAX, unless noted. Typical values are at TAMB = +25°C. PARAMETERS Driver Output Disable Time Output High to Tri-state Receiver Propagation Delay SYMBOL tHZ tPHL, tPLH TEST CONDITIONS CL = 15 pF, Fig. 34 and 37, S2 closed Fig. 33, 36 CL = 50 pF 20 MIN. TYP MAX 100 50 UNIT ns ns REV. 1.0.0 Receiver Skew | tPHL - tPLH| Fig. 33, 36 CL = 50 pF tZL tZH tLZ tHZ tR, tF CL = 100 pF, Fig. 35 and 39, S1 closed CL = 100 pF, Fig. 35 and 39, S2 closed CL = 15 pF, Fig. 35 and 39, S1 closed CL = 15 pF, Fig. 35 and 39, S2 closed 3.0 V < VL < 5.5V 1.65 V < VL < 3.0V CL = 50 pF 0.5 3.8 ns Receiver Output Enable Time Tri-state to Output Low Receiver Output Enable Time Tri-state to Output High Receiver Output Disable Time Output Low to Tri-state Receiver Output Disable Time Output High to Tri-state Receiver Output Rise / Fall Time 100 100 100 100 6 ns ns ns ns ns Channel to channel Skew 2 ns V.11 / RS-422 HANDSHAKE SIGNALS (DRIVERS 4, 5 & 6, RECEIVERS 4, 5 & 6) Maximum Transmission Rate Driver Rise and Fall Time Propagation Delay Time tR, tF tDPHL, tDPLH Fig. 33 Fig. 22 and 36 Fig. 33 and 36, CL = 50 pF 10 2 20 10 50 Mbps ns ns Driver Propagation Delay Skew Driver Channel to Channel Skew Driver Output Enable Time Tri-state to Output Low Driver Output Enable Time Tri-state to Output High Driver Output Disable Time Output Low to Tri-state Driver Output Disable Time Output High to Tri-state Receiver Propagation Delay tZL tZH tLZ tHZ tPHL, tPLH | tDPHL - tDPLH | 2 CL = 100 pF, Fig. 34 and 37, S1 closed CL = 100 pF, Fig. 34 and 37, S2 closed CL = 15 pF, Fig. 34 and 37, S1 closed CL = 15 pF, Fig. 34 and 37, S2 closed Fig. 33, 36 CL = 50 pF 20 10 ns ns 100 100 100 100 50 ns ns ns ns ns 8 SP510 REV. 1.0.0 ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER TIMING CHARACTERISTICS VCC = +4.75 to 5.25V, C1-C4 = 1µF; TAMB = TMIN to TMAX, unless noted. Typical values are at TAMB = +25°C. PARAMETERS Receiver Skew SYMBOL TEST CONDITIONS MIN. TYP MAX 10 UNIT ns | tPHL tZL tZH tLZ tHZ tR , tF tPLH| Fig. 33, 36 CL = 50 pF Receiver Output Enable Time Tri-state to Output Low Receiver Output Enable Time Tri-state to Output High Receiver Output Disable Time Output Low to Tri-state Receiver Output Disable Time Output Low to Tri-state Receiver Output Rise / Fall Time Channel to Channel Skew V.35 (DRIVERS 1, 2 & 3, RECEIVERS 1, 2 & 3) Maximum Transmission Rate Driver Rise and Fall Time Propagation Delay Time tR , tF tDPHL , tDPLH Fig. 33, fMAX = 20 MHz Fig. 29 Fig. 33 and 36, CL = 50 pF 20 40 10 50 Mbps ns ns CL = 100 pF, Fig. 35 and 39, S1 closed CL = 100 pF, Fig. 35 and 39, S2 closed CL = 15 pF, Fig. 35 and 39, S1 closed CL = 15 pF, Fig. 35 and 39, S2 closed 1 2 100 100 100 100 20 ns ns ns ns ns ns Driver Differential Skew | tDPHL 36 tDPLH| Fig. 33 and 2 5.0 ns Driver Channel to Channel Skew Driver Output Enable Time Tri-state to Output Low Driver Output Enable Time Tri-state to Output High Driver Output Disable Time Output Low to Tri-state Driver Output Disable Time Output High to Tri-state Receiver Propagation Delay tZL tZH tLZ tHZ tPHL , tPLH CL = 100 pF, Fig. 34 and 37, S1 closed CL = 100 pF, Fig. 34 and 37, S2 closed CL = 15 pF, Fig. 34 and 37, S1 closed CL = 15 pF, Fig. 34 and 37, S2 closed Fig. 33, 38 CL = 50 pF ns 200 200 200 200 ns ns ns ns ns 18 30 Receiver Skew | tPHL tZL tPLH| Fig. 33 and 38 5.0 ns CL = 50 pF Receiver Output Enable Time Tri-state to Output Low CL = 100 pF, Fig. 35 and 39, S1 closed 200 ns 9 SP510 ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER TIMING CHARACTERISTICS VCC = +4.75 to 5.25V, C1-C4 = 1µF; TAMB = TMIN to TMAX, unless noted. Typical values are at TAMB = +25°C. PARAMETERS Receiver Output Enable Time Tri-state to Output High Receiver Output Disable Time Output Low to Tri-state Receiver Output Disable Time Output High to Tri-state SYMBOL tZH tLZ tHZ TEST CONDITIONS CL = 100 pF, Fig. 35 and 39, S2 closed CL = 15 pF, Fig. 35 and 39, S1 closed CL = 15 pF, Fig. 35 and 39, S2 closed MIN. TYP MAX 200 200 200 UNIT ns ns ns REV. 1.0.0 10 SP510 REV. 1.0.0 ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER FIGURE 1. PIN OUT DIAGRAM TR(a) GND VDD C1P VCC C2P C1N GND C2N VSS1 RL(a) VCC LL(a) TM(a) IC RRT(a) RRT(b) GNDV10 DM(a) DM(b) CS(a) CS(b) TXC(a) GND TXC(b) NC VCC TR(b) RRC(b) VCC RRC(a) GND RS(a) VCC RS(b) GND ST(a) VCC V35TGND3 ST(b) GND TT(a) VCC V35TGND2 TT(b) GND SD(a) VCC V35TGND1 SD(b) 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 SP510 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 VL GND SDEN TTEN STEN RSEN TREN RRCEN RLEN LLEN# RDEN# RTEN# TXCEN# CSEN# DMEN# RRTEN# ICEN# TMEN D0 D1 D2 TERM_OFF D_LATCH# NC GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 RT(a) RT(b) RD(a) RD(b) V35RGND VL GND TM RI DCD_DTE DSR CTS TXC RXC RXD LL RL DCD_DCE DTR RTS ST TX_CE TXD LOOPBACK# VCC 11 SP510 ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER TABLE 3: PIN DESCRIPTIONS BY FUNCTION Pin Name Pin Number I/O DIFFERENTIAL DRIVERS TxD SD(b) / SD(a) V35TGND1 SDEN TxCE TT(b) / TT(a) V35TGND2 TTEN ST ST(b) / ST(a) V35TGND3 STEN RTS RS(b) / RS(a) RSEN DTR TR(b) / TR(a) TREN DCD_DCE RRC(b) / RRC(a) RRCEN 28 100, 97 99 3 29 95, 92 94 4 30 90, 87 89 5 31 85, 83 6 32 78, 75 7 33 79, 81 8 I O I I I O I I I O I I I O I I O I I O I TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TxD Driver Input Differential Transmit data non-inverting (b) and inverting (a) outputs SD Termination Reference TxD Driver Enable TxCE Driver Input Differential TxCE non-inverting (b) and inverting (a) outputs TT Termination Reference TxCE Driver Enable ST Driver Input Differential ST non-inverting (b) and inverting (a) outputs ST Termination Reference ST Driver Enable RTS Driver Input Differential RTS non-inverting (b) and inverting (a) outputs RTS Driver Enable DTR Driver Input Differential DTR non-inverting (b) and inverting (a) outputs DTR Driver Enable DCD_DCE Driver Input Differential DCD non-inverting (b) and inverting (a) outputs DCD Driver Enable DESCRIPTION REV. 1.0.0 SINGLE ENDED DRIVERS RL RL(a) RLEN LL LL(a) LLEN# 34 65 9 35 63 10 I O I I O I TTL TTL TTL TTL TTL TTL RL Driver Input RL Driver Output RL Driver Enable LL Driver Input LL Driver Output LL Driver Enable, active low 12 SP510 REV. 1.0.0 ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER Pin Number I/O DIFFERENTIAL RECEIVERS DESCRIPTION Pin Name RxD RD(b) / RD(a) RDEN# RxC RT(b) / RT(a) RTEN# TxC TxC(b) / TxC(a) TxCEN# CTS CS(b) / CS(a) CSEN# DSR DM(b) / DM(a) DMEN# DCD_DTE RRT(b) / RRT(a) RRTEN# 36 47, 48 11 37 49, 50 12 38 51, 53 13 39 54, 55 14 40 56, 57 15 41 59, 60 16 O I I O I I O I I O I I O I I O I I TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL RxD Receiver Output Differential RXD non-inverting (b) and inverting (a) inputs RxD Receiver Enable, active low RxC Receiver Output Differential RXC non-inverting (b) and inverting (a) inputs RxC Receiver Enable, active low TxC Receiver Output Differential TxC non-inverting (b) and inverting (a) inputs TxC Receiver Enable, active low CTS Receiver Output Differential CTS non-inverting (b) and inverting (a) inputs CTS Receiver Enable, active low DSR Receiver Output Differential DSR non-inverting (b) and inverting (a) inputs DSR Receiver Enable, active low DCD_DTE Receiver Output Differential DCD_DTE non-inverting (b) and inverting (a) inputs DCD_DTE Receiver Enable, active low SINGLE ENDED RECEIVERS IC RI ICEN# TM(a) TM TMEN 61 42 17 62 43 18 I O I I O I TTL TTL TTL TTL TTL TTL RI Receiver Input RI Receiver Output RI Receiver Enable, active low TM Receiver Input TM Receiver Output TM Receiver Enable PROTOCOL MODE SELECTION SIGNALS D2, D1, D0 21, 20, 19 I TTL Mode Select - Refer to Table 5 and Table 6 13 SP510 ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER Pin Name Pin Number I/O Charge Pump Signals C1P, C1N C2P, C2N VSS1 VDD 72, 69 70, 67 66 73 I I I I Charge Pump Capacitor 1 +/- inputs. Connect a 1 µF capacitor between C1P and C1N pins. Charge Pump Capacitor 2 +/- inputs. Connect a 1 µF capacitor between C2P and C2N pins. -2xVCC Charge Pump 2xVCC Charge Pump GENERAL CONTROL SIGNALS LOOPBACK# D_LATCH# TERM_OFF 27 23 22 I I I TTL Loopback mode enable, active low Decoder Latch, active low Termination disable RESERVED PINS NC 24, 76 No Connect POWER AND GROUND SIGNALS VCC VL GND 26, 64, 71, 77, 80, 84, 88, 98 1, 45 2, 25, 44, 52, 68, 74, 82, 86, 91, 96 58 46 I I I 5V supply. Logic I/O Power Supply Input Ground. DESCRIPTION REV. 1.0.0 GNDV10 V35RGND I O V.10 Receiver Ground Reference Receiver Termination Reference NOTE: Pin type: I = Input, O = Output, I/O = Input/output. 14 SP510 REV. 1.0.0 ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER TABLE 4: PIN DESCRIPTIONS BY PIN NUMBER PIN DESCRIPTIONS BY PIN NUMBER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 VL GND SDEN TTEN STEN RSEN TREN RRCEN RLEN LLEN# RDEN# RTEN# TxCEN# CSEN# DMEN# RRTEN# ICEN# TMEN D0 D1 D2 Logic I/O Power Supply Input Ground TxD Driver Enable Input TxCE Driver Enable Input ST Driver Enable Input RTS Driver Enable Input DTR Driver Enable Input DCD Driver Enable Input RL Driver Enable Input LL Driver Enable Input RxD Receiver Enable Input RxC Receiver Enable Input TxC Receiver Enable Input CTS Receiver Enable Input DSR Receiver Enable Input DCD_DTE Receiver Enable Input RI Receiver Enable Input TM Receiver Enable Input Mode Select Input - Bit 0 Mode Select Input - Bit 1 Mode Select Input - Bit 2 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 DTR DCD_DCE RL LL RxD RxC TxC CTS DSR DCD_DTE RI TM GND VL V35RGND RD(b) RD(a) RT(b) RT(a) TxC(b) GND TxC(a) CS(b) CS(a) DM(b) DM(a) GNDV10 RRT(b) RRT(a) IC TM(a) DTR Driver TTL Input DCD_DCE Driver TTL Input RL Driver TTL Input LL Driver TTL Input RxD Receiver TTL Output RxC Receiver TTL Output TxC Receiver TTL Output CTS Receiver TTL Output DSR Receiver TTL Output DCD_DTE Receiver TTL Output RI Receiver TTL Output TM Receiver TTL Output Ground Logic I/O Power Supply Input Receiver Termination Reference RXD Non-Inverting Input RXD Inverting Input RxC Non-Inverting Input RxC Inverting Input TxC Non-Inverting Input Ground TxC Inverting Input CTS Non-Inverting Input CTS Inverting Input DSR Non-Inverting Input DSR Inverting Input V.10 Rx Ground Reference DCD_DTE Non-Inverting Input DCD_DTE Inverting Input RI Receiver Input TM Receiver Input TERM_OFF Termination Disable Input D_LATCH# NC GND Vcc LOOPBACK# TxD TxCE ST RTS Decoder Latch Input No Connect Ground Power Supply Input Loopback Mode Enable Input TxD Driver TTL Input TxCE Driver TTL Input ST Driver TTL Input RTS Driver TTL Input 15 SP510 ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER PIN DESCRIPTIONS BY PIN NUMBER 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 LL(a) VCC RL(a) VSS1 C2N GND C1N C2P VCC C1P VDD GND TR(a) NC VCC TR(b) RRC(b) VCC RRC(a) LL Driver Output Power Supply Input RL Driver Output -2xVCC Charge Pump Charge Pump Capacitor Ground Charge Pump Capacitor Charge Pump Capacitor Power Supply Input Charge Pump Capacitor 2xVCC Charge Pump Ground DTR Inverting Output No Connect Power Supply Input DTR Non-Inverting Output DCD Non-Inverting Output Power Supply Input DCD Inverting Output 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 GND RS(a) VCC RS(b) GND ST(a) VCC Ground RTS Inverting Output Power Supply Input RTS Non-Inverting Output Ground ST Inverting Output Power Supply Input REV. 1.0.0 V35TGND3 ST Termination Reference ST(b) GND TT(a) VCC ST Non-Inverting Output Ground TxCE Inverting Output 5V Power Supply V35TGND2 TT Termination Reference TT(b) GND SD(a) VCC TxCE Non-Inverting Output Ground TxD Inverting Output 5V Power Supply V35TGND1 SD Termination Reference SD(b) TxD Non-Inverting Output 16 SP510 REV. 1.0.0 ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER TABLE 5: DRIVER MODE SELECTION DRIVER OUTPUT PIN MODE (D2, D1, D0) T1OUT(a) T1OUT(b) T2OUT(a) T2OUT(b) T3OUT(a) T3OUT(b) T4OUT(a) T4OUT(b) T5OUT(a) T5OUT(b) T6OUT(a) T6OUT(b) T7OUT(a) T8OUT(a) V.35 MODE EIA-530 MODE RS-232 MODE (V.28) 011 V.28 High-Z V.28 High-Z V.28 High-Z V.28 High-Z V.28 High-Z V.28 High-Z V.28 V.28 EIA530A MODE RS-449 MODE (V.36) X.21 MODE (V.11) 110 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 High-Z High-Z SHUTDOWN SUGGESTED SIGNAL 001 V.35 V.35 V.35 V.35 V.35 V.35 V.28 High-Z V.28 High-Z V.28 High-Z V.28 V.28 010 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.10 V.10 100 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.10 High-Z V.11 V.11 V.10 V.10 101 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.10 V.10 111 High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z TxD(a) TxD(b) TxCE(a) TxCE(b) TxC_DCE(a) TxC_DCE(b) RTS(a) RTS(b) DTR(a) DTR(b) DCD_DCE(a) DCD_DCE(b) RL LL 17 SP510 ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER TABLE 6: RECEIVER MODE SELECTION RECEIVER INPUT PIN MODE (D2, D1, D0) R1IN(a) R1IN(b) R2IN(a) R2IN(b) R3IN(a) R3IN(b) R4IN(a) R4IN(b) R5IN(a) R5IN(b) R6IN(a) R6IN(b) R7IN(a) R8IN(a) V.35 MODE EIA-530 MODE RS-232 MODE (V.28) 011 V.28 High-Z V.28 High-Z V.28 High-Z V.28 High-Z V.28 High-Z V.28 High-Z V.28 V.28 EIA530A MODE RS-449 MODE (V.36) X.21 MODE (V.11) 110 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 High-Z High-Z SHUTDOWN REV. 1.0.0 SUGGESTED SIGNAL 001 V.35 V.35 V.35 V.35 V.35 V.35 V.28 High-Z V.28 High-Z V.28 High-Z V.28 V.28 010 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.10 V.10 100 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.10 High-Z V.11 V.11 V.10 V.10 101 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.10 V.10 111 High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z RxD(a) RxD(b) RxCE(a) RxCE(b) TxC_DTE(a) TxC_DTE(b) CTS(a) CTS(b) DSR(a) DSR(b) DCD_DTE(a) DCD_DTE(b) RI TM 18 SP510 REV. 1.0.0 ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER TABLE 7: V.11 & V.35 DRIVERS INPUTS TX_EN# 1 1 TX_IN 1 0 TX(A) 0 1 OUTPUTS TX(B) 1 0 TABLE 11: V.10 DRIVERS INPUTS TX_EN# 1 1 TX_IN 1 0 TX(A) < -4V > +4V OUTPUTS TX(B) > 30 kΩ > 30 kΩ TABLE 8: V.11 & V.35 RECEIVERS INPUTS RX(A) - RX(B) ≥ 200 mV ≤ −200 mV Open / shorted OUTPUTS RO 1 0 1 TABLE 12: V.10 RECEIVERS INPUTS RX(A) - RX(B) OUTPUTS RO 0 1 1 TABLE 9: V.28 DRIVERS INPUTS TX_EN# 1 1 TX_IN 1 0 TX(A) < -5V > +5V OUTPUTS TX(B) > 30 kΩ > 30 kΩ ≥ +0.3V ≤ −0.3V Open / ground TABLE 10: V.28 RECEIVERS INPUTS RX(A) - RX(B) ≥ +3V ≤ −3V Open / ground OUTPUTS RO 0 1 1 19 SP510 ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER FIGURE 2. V.28 DRIVER OUTPUT OPEN CIRCUIT VOLTAGE RENT REV. 1.0.0 FIGURE 5. V.28 DRIVER OUTPUT SHORT CIRCUIT CUR- FIGURE 6. V.28 DRIVER OUTPUT POWER-OFF IMPEDFIGURE 3. V.28 DRIVER OUTPUT LOADED VOLTAGE ANCE FIGURE 4. V.28 DRIVER OUTPUT SLEW RATE FIGURE 7. V.28 DRIVER OUTPUT RISE/FALL TIME 20 SP510 REV. 1.0.0 ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER FIGURE 11. V.10 DRIVER OUTPUT TEST TERMINATED VOLTAGE FIGURE 8. V.28 RECEIVER INPUT IMPEDANCE FIGURE 9. V.28 RECEIVER INPUT OPEN-CIRCUIT BIAS FIGURE 12. V.10 DRIVER OUTPUT SHORT-CIRCUIT CURRENT FIGURE 10. V.10 DRIVER OUTPUT OPEN-CIRCUIT VOLTAGE FIGURE 13. V.10 DRIVER OUTPUT POWER-OFF IMPEDANCE 21 SP510 ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER FIGURE 14. V.10 DRIVER OUTPUT TRANSITION TIME REV. 1.0.0 FIGURE 17. V.11 DRIVER OUTPUT TEST TERMINATED VOLTGE FIGURE 15. V.10 RECEIVER INPUT CURRENT FIGURE 18. V.11 DRIVER OUTPUT TEST TERMINATED VOLTAGE FIGURE 16. V.10 RECEIVER INPUT IV GRAPH FIGURE 19. V.11 DRIVER OUTPUT SHORT-CIRCUIT CURRENT 22 SP510 REV. 1.0.0 ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER FIGURE 21. V.11 RECEIVER INPUT CURRENT FIGURE 20. V.11 DRIVER OUTPUT POWER-OFF CURRENT VCC = 0V A Iia ±10V A Ixa ±0.25V B B C C VCC = 0V A ±10V A ±0.25V B Iib B Ixb C C 23 SP510 ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER MINATION REV. 1.0.0 FIGURE 24. V.11 RECEIVER INPUT CURRENT WITH TER- FIGURE 22. V.11 DRIVER OUTPUT RISE/FALL TIME A Iia ±6V 100 to 150 B C FIGURE 23. V.11 RECEIVER INPUT IV GRAPH A ±6V 100 to 150 B Iib C 24 SP510 REV. 1.0.0 ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER FIGURE 25. V.11 RECEIVER INPUT IV GRAPH WITH TERMINATION FIGURE 26. V.35 DRIVER OUTPUT TEST TERMINATED VOLTAGE FIGURE 27. V.35 DRIVER OUTPUT SOURCE IMPEDANCE 25 SP510 ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER FIGURE 28. V.35 DRIVER OUTPUT SHORT-CIRCUIT IMPEDANCE REV. 1.0.0 FIGURE 29. V.35 DRIVER OUTPUT RISE/FALL TIME FIGURE 30. V.35 RECEIVER INPUT SOURCE IMPEDANCE 26 SP510 REV. 1.0.0 ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER FIGURE 31. V.35 RECEIVER INPUT SHORT-CIRCUIT IMPEDANCE FIGURE 32. DRIVER OUTPUT CURRENT LEAKAGE TEST FIGURE 33. DRIVER / RECEIVER TIMING TEST CIRCUIT 27 SP510 ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER FIGURE 34. DRIVER TIMING TEST LOAD CIRCUIT REV. 1.0.0 FIGURE 35. RECEIVER TIMING TEST LOAD CIRCUIT FIGURE 36. DRIVER PROPAGATON DELAYS 28 SP510 REV. 1.0.0 ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER FIGURE 37. DRIVER ENABLE AND DISABLE TIMES FIGURE 38. RECEIVER PROPAGATION DELAYS FIGURE 39. RECEIVER ENABLE AND DISABLE TIMES 29 SP510 ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER FIGURE 40. V.28 (RS-232) AND V.10 (RS-423) DRIVER ENABLE AND DISABLE TIMES REV. 1.0.0 FIGURE 41. TYPICAL V.28 DRIVER OUTPUT WAVEFORM 30 SP510 REV. 1.0.0 ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER FIGURE 42. TYPICAL V.10 DRIVER OUTPUT WAVEFORM FIGURE 43. TYPICAL V.11 DRIVER OUTPUT WAVEFORM FIGURE 44. TYPICAL V.35 DRIVER OUTPUT WAVEFORM 31 SP510 ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER FIGURE 45. FUNCTIONAL DIAGRAM VCC pins (26, 64, 71, 77, 80, 84, 88, 93, 98) GND pins (2, 25, 44, 52, 68, 74, 82, 86, 91, 96) VL pins (1 and 46) N.C. pins (24 and 76) REV. 1.0.0 +5V (decoupling capacitor not shown) Logic Voltage 1µF 1µF 1µF 72 VCC VL C1+ 69 C1- 70 C2+ 67 C2- 73 VDD V35RGND RD(a) RxD RDEN RD(b) RT(a) RxC RTEN RT(b) TxC(a) TxC TxCEN TxC(b) CS(a) CTS CSEN CS(b) DM(a) DSR DMEN DM(b) RRT(a) DCD_DTE RRTEN RRT(b) IC RI ICEN VSS Regulated Charge Pump 66 1µF 46 48 36 11 47 50 37 12 49 53 38 13 51 55 39 14 54 57 40 15 56 60 41 16 59 61 42 17 62 28 97 99 100 3 29 92 94 95 4 30 87 89 90 5 31 83 85 6 32 75 78 7 33 81 79 8 34 65 9 35 63 10 TxD SD(a) V35TGND1 SD(b) SDEN TxCE TT(a) V35TGND2 TT(b) TTEN ST ST(a) V35TGND3 ST(b) STEN RTS RS(a) RS(b) RSEN DTR TR(a) TR(b) TREN DCD_DCE RRC(a) RRC(b) RRCEN RL RL(a) RLEN LL LL(a) LLEN TM(a) TM TMEN 43 18 19 20 21 23 22 27 D0 D1 D2 D-LATCH TERM-OFF SP510 V.10-GND 58 LOOPBACK GND RECEIVER TERMINATION NETWORK V.35 MODE V.11 MODE RX ENABLE 51ohms 51ohms 124ohms V.35 DRIVER TERMINATION NETWORK 51ohms V.35 MODE TX ENABLE 51ohms 124ohms 32 SP510 REV. 1.0.0 ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER FIGURE 46. SP510 LOOPBACK PATH SD(a) TxD SD(b) RD(a) RxD RD(b) TT(a) TxCE TT(b) RT(a) RxC RT(b) ST(a) ST ST(b) TxC(a) TxC TxC(b) RS(a) RTS RS(b) CS(a) CTS CS(b) TR(a) DTR TR(b) DM(a) DSR DM(b) RRC(a) DCD_DCE RRC(b) RRT(a) DCD_DTE RRT(b) RL RL(a) RI IC LL LL(a) TM TM(a) 33 ITY SP510 Logic Voltage +5V 10µ F VCC VDD VL C1+ C1- C2+ C2VSS 1µ F 1µ F 1µ F 1µ F Charge Pump Section Transceiver Section µ DB-26 Serial Port Connector Pins Signal (DTE_DCE) #103 (TxD) #113 (TXCE) ST RTS DTR DCD_DCE RL TxCE TxD 2 (V.11,V.35,V.28) 14 (V.11,V.35) 24 (V.11,V.35,V.28) 11 (V.11,V.35) TXD_RXD_A TXD_RXD_B TXCE_TXC_A TXCE_TXC_B #105 (RTS) #108 (DTR) #109 (DCD) DCE 4 (V.11,V.28) 19 (V.11) 20 (V.11,V.28) 23 (V.11) RTS_CTS_A RTS_CTS_B DTR_DSR_A DTR_DSR_B #140 (RL) #141 (LL) #105 (RXD) #115 (RXC) #114 (TxC) #106 (CTS) #107 (DSR) #109 (DCD) DTE 21 (V.10,V.28) 18 (V.10,V.28) LL_TM RL_RI LL RxD RxC TxC CTS DSR DCD_DTE RI TM Logic Section D0 D1 D2 ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER FIGURE 47. TYPICAL OPERATING CONFIGURATION TO SERIAL PORT CONNECTOR WITH DCE/DTE PROGRAMMABIL- 34 #125 (RI) #142 (TM) 3 (V.11,V.35,V.28) 16 (V.11,V.35) 17 (V.11,V.35,V.28) 9 (V.11,V.35) 15 (V.11,V.35,V.28) 12 (V.11,V.35) 5 (V.11,V.28) 13 (V.11) 6 (V.11,V.28) 22 (V.11) 8 (V.11,V.28) 10 (V.11) 22 (V.10,V.28) 25 (V.10,V.28) RXD_TXD_A RXD_TXD_B RXC_TXCE_A RXC_TXCE_B *TXC_RXC_A *TXC_RXC_B CTS_R S_A T CTS_R S_B T DSR_DTR_A DSR_DTR_B DCD_DCD_A DCD_DCD_B RI_RL LL_TM VL DCE/DTE D_LATCH TERM_OFF LOOPBACK V35TGND1 V35TGND2 V35TGND3 V35RGND V10_GND GND SP510 SDEN TTEN STEN TREN RSEN RRCEN RLEN LLEN RDEN RTEN TxCEN DMEN CSEN RRTEN ICEN TMEN VL * - Driver applies f or DCE only on pins 15 and 12. Receiver applies for DTE only on pins 15 and 12. Driver applies f or DCE only on pins 8 and 10. Receiver applies for DTE only on pins 8 and 10. SIGNAL GND (10 Pins) Reference Design Schematic Customer: Title : Date: Input Line Output Line I/O Lines represented by double arrowhead signifies a bi-directional bus. Typical SP510 DB-26 Serial Port Configuration Doc. #: Rev. REV. 1.0.0 0 SP510 REV. 1.0.0 ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER Thermal Considerations High speed devices like the SP510 dissipate heat during normal operation. Actual power dissipation is a function of the switching frequency and loading. For maximum system performance and reliability designers should ensure sufficient air flow. Other commonly used methods for managing heat include heat sinks for higher powered devices, forced air flow (fans) and lower density board stuffing. PCB Design The use of multi layer printed circuit boards is recommended to provide both a better ground plane and a thermal path for heat dissipation. If possible, the ground plane should face the bottom of the package to form the thermal conduction plane. Two-sided printed circuit boards may be used where board dimensions and package count are small, but multi-layer boards allow for improved signal routing as well as improved signal integrity. A multi layer board allows the use of microstrip line techniques to provide for high speed signal interconnections. On multi-layer boards route the high speed signal lines on the inner layers. 35 SP510 ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER REV. 1.0.0 36 SP510 REV. 1.0.0 ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER REVISION HISTORY DATE December 2009 REVISION Rev 1.0.0 Final datasheet. DESCRIPTION NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2009 EXAR Corporation Datasheet December 2009. Send your UART technical inquiry with technical details to hotline: uarttechsupport@exar.com. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. 37