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ST16C554DCJ68TR-F

ST16C554DCJ68TR-F

  • 厂商:

    SIPEX(迈凌)

  • 封装:

    68-LCC(J形引线)

  • 描述:

    IC UART FIFO 16B QUAD 68PLCC

  • 数据手册
  • 价格&库存
ST16C554DCJ68TR-F 数据手册
ST16C554 / ST16C554D / ST68C554 Data Sheet 2.97V to 5.5V Quad UARTs with 16-Byte FIFO General Description Features ■ The ST16C554, ST16C554D and ST68C554 are each quad Universal Asynchronous Receivers and Transmitters (UARTs) with 16 bytes of transmit and receive FIFOs, selectable receive FIFO trigger levels, and data rates of up to 1.5Mbps. Each UART has a set of registers that provide the user with operating status and control, receiver error indications, and modem serial interface controls. An internal loopback capability allows onboard diagnostics. The ST16C554 is available in a 64-pin LQFP package, the ST16C554D is available in both a 64-pin LQFP and a 68-pin PLCC package, and the ST68C554 is available in a 68-pin PLCC package. The 64-pin package only offers the 16 mode interface, but the 68-pin package offers an additional 68 mode interface which allows easy integration with Motorola processors. The ST16C554CQ64 (64-pin) offers three-state interrupt output while the ST16C554DCQ64 provides continuous interrupt output. The ST16C554 and ST16C554D combine the package interface modes of the 16C554 and 68C554 on a single integrated chip. ■ ■ ■ ■ Pin-to-pin compatible with the industry standard ST16C454, ST68C454, ST68C554, TI’s TL16C554A and Philips’ SC16C554B Intel or Motorola data bus interface select Four independent UART channels  Register set compatible to 16C550  Data rates of up to 1.5Mbps at 5V  Data rates of up to 500kbps at 3.3V  16 byte transmit FIFO  16 byte receive FIFO with error tags  4 selectable RX FIFO trigger levels  Full modem interface 2.97V to 5.5V supply operation Crystal oscillator or external clock input Applications ■ ■ ■ ■ ■ Ordering Information - page 32 Portable appliances Telecommunication network routers Ethernet network routers Cellular data devices Factory automation and process controls Block Diagram 2.97 V to 5.5 V VCC GND A2:A0 D7:D0 IOR# IOW# CSA# UART Regs CSB# BRG CSC# CSD# INTA INTB INTC INTD Data Bus Interface UART Channel A 16 Byte TX FIFO TX & RX IR ENDEC 16 Byte RX FIFO UART Channel B (same as Channel A) TXB, RXB, IRTXB, DTRB#, DSRB#, RTSB#, CTSB#, CDB#, RIB# UART Channel C (same as Channel A) TXC, RXC, IRTXC, DTRC#, DSRC#, RTSC#, CTSC#, CDC#, RIC# UART Channel D (same as Channel A) TXD, RXD, IRTXD, DTRD#, DSRD#, RTSD#, CTSD#, CDD#, RID# TXRDY# A-D RXRDY# A-D Reset 16/68# INTSEL Crystal Osc / Buffer Figure 1: ST16C554 Block Diagram • www.maxlinear.com• Rev 4.0.2 TXA, RXA, IRTXA, DTRA#, DSRA#, RTSA#, CTSA#, CDA#, RIA# XTAL1 XTAL2 ST16C554 / ST16C554D / ST68C554 2.97V to 5.5V Quad UART with 16-Byte FIFO Data Sheet Revision History Revision History Document No. Release Date Change Description 3.3.0 August 2004 Added Revision History and Device Status. 3.3.1 August 2005 Updated the 1.4mm-thick Quad Flat Pack package description from "TQFP" to "LQFP" to be consistent with JEDEC and Industry norms. 4.0.0 April 2006 New datasheet format. Changed active low signal designator from "-" in front of signal name to "#" after signal name. Updated AC Electrical Characteristics. 4.0.1 June 2006 Corrected Part Numbers in Ordering Information. 4.0.2 9/4/19 Update to MaxLinear format. Update Ordering Information and moved to end. Correct pin configuration with selectable 16/68# pin from ST16C554 to ST16C554D. 9/4/19 Rev 4.0.2 ii ST16C554 / ST16C554D / ST68C554 2.97V to 5.5V Quad UARTs with 16-Byte FIFO Data Sheet Table of Contents Table of Contents General Description............................................................................................................................................. i Features............................................................................................................................................................... i Applications ......................................................................................................................................................... i Block Diagram...................................................................................................................................................... i 1.0 Pin Information ............................................................................................................................................. 1 1.1 Pin Descriptions ......................................................................................................................................................2 2.0 Product Description ..................................................................................................................................... 5 2.1 Enhanced FIFO ...................................................................................................................................................... 5 2.2 Intel or Motorola Data Bus Interface....................................................................................................................... 5 2.3 Data Rate ............................................................................................................................................................... 5 2.4 Enhanced Features ................................................................................................................................................ 5 3.0 Functional Descriptions............................................................................................................................... 6 3.1 CPU Interface..........................................................................................................................................................6 3.2 Device Reset .......................................................................................................................................................... 7 3.3 Channel Selection .................................................................................................................................................. 7 3.4 Internal Registers of Channels A - D...................................................................................................................... 7 3.5 INT Outputs for Channels A - D ............................................................................................................................. 7 3.6 DMA Mode ..............................................................................................................................................................8 3.7 Crystal Oscillator or External Clock Input ................................................................................................................8 3.8 Programmable Baud Rate Generator..................................................................................................................... 9 3.9 Transmitter ............................................................................................................................................................10 3.9.1 Transmit Holding Register (THR) - Write Only ..........................................................................................10 3.9.2 Transmitter Operation in Non-FIFO Mode.................................................................................................10 3.9.3 Transmitter Operation in FIFO Mode ........................................................................................................10 3.10 Receiver ............................................................................................................................................................. 10 3.10.1 Receive Holding Register (RHR) - Read Only ........................................................................................11 3.11 Internal Loopback................................................................................................................................................12 4.0 UART Internal Registers ............................................................................................................................ 13 5.0 Internal Register Descriptions................................................................................................................... 15 5.1 Receive Holding Register (RHR) - Read-Only ..................................................................................................... 15 5.2 Transmit Holding Register (THR) - Write-Only ..................................................................................................... 15 5.3 Interrupt Enable Register (IER) - Read and Write ................................................................................................ 15 5.3.1 IER Versus Receive FIFO Interrupt Mode Operation................................................................................15 5.3.2 IER Versus Receive and Transmit FIFO Polled Mode Operation ............................................................. 15 9/4/19 Rev 4.0.2 iii ST16C554 / ST16C554D / ST68C554 2.97V to 5.5V Quad UARTs with 16-Byte FIFO Data Sheet Table of Contents 5.4 Interrupt Status Register (ISR) ............................................................................................................................. 16 5.4.1 Interrupt Generation ..................................................................................................................................16 5.4.2 Interrupt Clearing.......................................................................................................................................16 5.5 FIFO Control Register (FCR) - Write-Only ............................................................................................................ 17 5.6 Line Control Register (LCR) - Read and Write ..................................................................................................... 17 5.7 Modem Control Register (MCR) or General Purpose Output Control - Read and Write ...................................... 18 5.8 Line Status Register (LSR) - Read and Write....................................................................................................... 19 5.9 Modem Status Register (MSR) - Read and Write .................................................................................................20 5.10 Scratch Pad Register (SPR) - Read and Write................................................................................................... 20 5.11 Baud Rate Generator Registers (DLL and DLM) - Read and Write ................................................................... 21 6.0 Specifications ............................................................................................................................................. 22 6.1 Absolute Maximum Ratings...................................................................................................................................22 6.2 Electrical Characteristics .......................................................................................................................................22 6.2.1 DC Electrical Characteristics.....................................................................................................................22 6.2.2 AC Electrical Characteristics .....................................................................................................................23 7.0 Mechanical Dimensions ............................................................................................................................. 30 7.1 LQFP64 .................................................................................................................................................................30 7.2 PLCC68 .................................................................................................................................................................31 8.0 Ordering Information.................................................................................................................................. 32 9/4/19 Rev 4.0.2 iv ST16C554 / ST16C554D / ST68C554 2.97V to 5.5V Quad UARTs with 16-Byte FIFO Data Sheet List of Figures List of Figures Figure 1: ST16C554 Block Diagram ...................................................................................................................... i Figure 2: PLCC68 Pinout, Intel Mode ................................................................................................................... 1 Figure 3: PLCC68 Pinout, Motorola Mode............................................................................................................ 1 Figure 4: LQFP64 Pinout, Intel Mode Only........................................................................................................... 1 Figure 5: PLCC68 Pinout, Motorola Mode Only ................................................................................................... 1 Figure 6: ST16C554D Typical Intel and Motorola Data Bus Interconnections ..................................................... 6 Figure 7: Typical Crystal Connections .................................................................................................................. 8 Figure 8: Baud Rate Generator ............................................................................................................................ 9 Figure 9: Transmitter Operation in Non-FIFO Mode........................................................................................... 10 Figure 10: Transmitter Operation in FIFO Mode................................................................................................. 10 Figure 11: Receiver Operation in Non-FIFO Mode............................................................................................. 11 Figure 12: Receiver Operation in FIFO Mode..................................................................................................... 11 Figure 13: Internal Loopback in Channels A and B ............................................................................................ 12 Figure 14: Clock Timing...................................................................................................................................... 24 Figure 15: Modem Input and Output Timing for Channels A - D ........................................................................ 24 Figure 16: 16 Mode (Intel) Data Bus Read Timing for Channels A - D............................................................... 25 Figure 17: 16 Mode (Intel) Data Bus Write Timing for Channels A - D............................................................... 25 Figure 18: 68 Mode (Motorola) Data Bus Read Timing for Channels A - D ....................................................... 26 Figure 19: 68 Mode (Motorola) Data Bus Write Timing for Channels A - D........................................................ 26 Figure 20: Receive Ready and Interrupt Timing (Non-FIFO Mode) for Channels A - D ..................................... 27 Figure 21: Transmit Ready and Interrupt Timing (Non-FIFO Mode) for Channels A - D .................................... 27 Figure 22: Receive Ready and Interrupt Timing (FIFO Mode, DMA Disabled) for Channels A - D.................... 28 Figure 23: Receive Ready and Interrupt Timing (FIFO Mode, DMA Enabled) for Channels A - D..................... 28 Figure 24: Transmit Ready and Interrupt Timing (FIFO Mode, DMA Disabled) for Channels A - D................... 29 Figure 25: Transmit Ready and Interrupt Timing (FIFO Mode, DMA Enabled) for Channels A - D.................... 29 Figure 26: Mechanical Dimension, LQFP64 (10 x 10 x 1.4mm Low-Profile Quad Flat Pack) ............................ 30 Figure 27: Mechanical Dimensions, PLCC68 (Plastic Leaded Chip Carrier)...................................................... 31 9/4/19 Rev 4.0.2 v ST16C554 / ST16C554D / ST68C554 2.97V to 5.5V Quad UARTs with 16-Byte FIFO Data Sheet List of Tables List of Tables Table 1: ST16C554D Pin Descriptions ................................................................................................................. 2 Table 2: Channel A - D Select in 16 Mode ........................................................................................................... 7 Table 3: Channel A - D Select in 68 Mode ........................................................................................................... 7 Table 4: INT Pin Operation for Channel A - D Transmitters ................................................................................. 7 Table 5: INT Pin Operation for Channel A - D Receivers ..................................................................................... 8 Table 6: TXRDY# and RXRDY# Outputs in FIFO and DMA Mode for Channels A - D........................................ 8 Table 7: Typical Data Rates with a 14.7456MHz Crystal or External Clock ......................................................... 9 Table 8: Internal Registers of UART Channels A and B..................................................................................... 13 Table 9: Internal Register Descriptions............................................................................................................... 14 Table 10: Interrupt Source and Priority Level ..................................................................................................... 16 Table 11: Receive FIFO Trigger Level Selection................................................................................................ 17 Table 12: TX and RX Word Length..................................................................................................................... 17 Table 13: TX and RX Stop-Bit Length ................................................................................................................ 17 Table 14: Parity Selection................................................................................................................................... 18 Table 15: INT Output Modes .............................................................................................................................. 19 Table 16: UART Reset Conditions for Channels A - D ....................................................................................... 21 Table 17: Absolute Maximum Ratings ................................................................................................................ 22 Table 18: Typical Package Thermal Resistance Data........................................................................................ 22 Table 19: Electrical Characteristics .................................................................................................................... 22 Table 20: AC Electrical Characteristics .............................................................................................................. 23 Table 21: Ordering Information........................................................................................................................... 32 9/4/19 Rev 4.0.2 vi ST16C554 / ST16C554D / ST68C554 2.97V to 5.5V Quad UARTs with 16-Byte FIFO Data Sheet Pin Information 1.0 Pin Information 1.1 Pin Configurations D D 38 CSC# 12 37 INTC RTSB# 13 36 RTSC# 26 27 28 29 30 31 32 XTAL2 GND RXC RIC# CDC# DSRC# 25 XTAL1 RESET 23 24 A0 A2 A1 21 22 VCC CTSC # 20 33 RXB 16 19 CTSB# RIB# DTRC# 17 VCC 34 18 35 15 CDB# 14 DSRB# GND DTRB# CDA# RIA# RXA GND D7 D6 D5 D4 D3 D2 D1 D0 GND VCC RXD RID# CDD# 7 6 5 4 3 2 1 68 67 66 65 64 63 62 63 A4 N.C. N.C. 21 49 RTSB# 22 48 RTSC# GND 23 47 VCC DTRB# 24 46 DTRC# CTSB# 25 45 CTSC# DSRB# 26 44 DSRC# Figure 5: PLCC68 Pinout, Motorola Mode Only Figure 4: LQFP64 Pinout, Intel Mode Only 9/4/19 8 50 43 11 INTB 20 CDC# CSB# TXC A3 42 TXC RIC# 39 51 41 10 19 RXC TXB N.C. TXB 40 IOR# 52 GND 40 18 39 9 TXD R/W# TXRDY# IOW# N.C. 53 ST68C554 68-pin PLCC Motorola Mode Only 38 TXD 54 17 RXRDY# 41 16 TXA 37 8 CS# RESET TXA N.C. 36 CSD# RTSD# 55 XTAL2 INTD 42 56 15 35 43 ST16C554/554D 64-pin LQFP Intel Mode Only 14 IRQ# XTAL1 7 RTSA# 34 6 GND A0 INTA CSA# 57 33 RTSD# 13 A1 GND 44 DTRD# VCC 32 45 5 58 A2 4 12 31 VCC RTSA# CTSD# DTRA# GND DTRD # DSRD# 59 30 46 60 11 VCC 3 10 CTSA# 29 DTRA# DSRA# RXB CTSD# 28 DSRD # 47 27 48 2 RIB# CDD# 49 1 CTSA# CDB# RXD 52 RID# VCC 53 50 D0 54 51 D2 D1 55 D4 D3 56 D5 58 57 D7 D6 60 59 RXA GND 61 RIA# 62 CDA# 64 63 DSRA# 9 Figure 3: PLCC68 Pinout, Motorola Mode Figure 2: PLCC68 Pinout, Intel Mode Rev 4.0.2 1 ST16C554 / ST16C554D / ST68C554 2.97V to 5.5V Quad UART with 16-Byte FIFO Data Sheet Pin Descriptions 1.2 Pin Descriptions Table 1: Name Pin Descriptions LQFP64 PLCC68 Type Description I Address data lines [2:0]. These 3 address lines select one of the internal registers in UART channel A - D during a data bus transaction. I/O Data bus lines [7:0] (bidirectional). I When the 16/68# pin is HIGH, the Intel bus interface is selected and this input becomes a read strobe (active low). The falling edge instigates an internal read cycle and retrieves the data byte from an internal register pointed to by the address lines [A2:A0], puts the data byte on the data bus to allow the host processor to read it on the rising edge. When the 16/68# pin is LOW, the Motorola bus interface is selected and this input is not used and should be connected to VCC. I When the 16/68# pin is HIGH, it selects the Intel bus interface and this input becomes a write strobe (active low). The falling edge instigates the internal write cycle and the rising edge transfers the data byte on the data bus to an internal register pointed to by the address lines. When the 16/68# pin is LOW, the Motorola bus interface is selected and this input becomes read (HIGH) and write (LOW) signal. I When the 16/68# pin is HIGH, this input is chip select A (active low) to enable channel A in the device. When the 16/68# pin is LOW, this input becomes the chip select (active low) for the Motorola bus interface. I When the 16/68# pin is HIGH, this input is chip select B (active low) to enable channel B in the device. When the 16/68# pin is LOW, this input becomes address line A3 which is used for channel selection in the Motorola bus interface. I When the 16/68# pin is HIGH, this input is chip select C (active low) to enable channel C in the device. When the 16/68# pin is LOW, this input becomes address line A4 which is used for channel selection in the Motorola bus interface. I When the 16/68# pin is HIGH, this input is chip select D (active low) to enable channel D in the device. When the 16/68# pin is LOW, this input is not used and should be connected to VCC. Data Bus Interface A2 22 32 A1 23 33 A0 24 34 D7 60 5 D6 59 4 D5 58 3 D4 57 2 D3 56 1 D2 55 68 D1 54 67 D0 53 66 IOR# (VCC) IOW# (R/W#) CSA# (CS#) CSB# (A3) CSC# (A4) CSD# (VCC) 9/4/19 40 9 7 11 38 42 52 18 16 20 50 54 Rev 4.0.2 2 ST16C554 / ST16C554D / ST68C554 2.97V to 5.5V Quad UART with 16-Byte FIFO Data Sheet Pin Descriptions Table 1: (Continued) Pin Descriptions Name LQFP64 PLCC68 INTA (IRQ#) 6 15 INTB (N.C.) 12 21 INTC (N.C.) 37 49 INTD (N.C.) 43 55 Type Description O (OD) When the 16/68# pin is HIGH for Intel bus interface, this output becomes the channel A interrupt output. The output state is defined by the user and through the software setting of MCR[3]. INTA is set to the active mode when MCR[3] is set to a logic 1. INTA is set to the three state mode when MCR[3] is set to a logic 0 (default). See MCR[3]: INT Output Enable. When the 16/68# pin is LOW for Motorola bus interface, this output becomes the device interrupt output (active low, open drain). An external pull-up resistor is required for proper operation. O When the 16/68# pin is HIGH for Intel bus interface, these outputs become the interrupt outputs for channels B, C, and D. The output state is defined by the user through the software setting of MCR[3]. The interrupt outputs are set to the active mode when MCR[3] is set to a logic 1 and are set to the three state mode when MCR[3] is set to a logic 0 (default). See MCR[3]: INT Output Enable. When 16/68# pin is LOW for Motorola bus interface, these outputs are unused and will stay at logic zero level. Leave these outputs unconnected. INTSEL - 65 I Interrupt Select (active high, input with internal pull-down). When the 16/68# pin is HIGH for Intel bus interface, this pin can be used in conjunction with MCR bit-3 to enable or disable the INT A - D pins or override MCR bit-3 and enable the interrupt outputs. Interrupt outputs are enabled continuously when this pin is HIGH. MCR bit-3 enables and disables the interrupt output pins. In this mode, MCR bit-3 is set to a logic 1 to enable the continuous output. See MCR[3]: INT Output Enable description for full detail. This pin must be LOW in the Motorola bus interface mode. For the 64 pin packages, this pin is bonded to VCC internally in the ST16C554DCQ64-F so the INT outputs operate in the continuous interrupt mode. This pin is bonded to GND internally in the ST16C554CQ64 and therefore requires setting MCR bit-3 for enabling the interrupt output pins. TXRDY# - 39 O Transmitter Ready (active low). This output is a logically ANDed status of TXRDY# A - D. See Table 6. If this output is unused, leave it unconnected. RXRDY# - 38 O Receiver Ready (active low). This output is a logically ANDed status of RXRDY# A - D. See Table 6. If this output is unused, leave it unconnected. O UART channels A - D transmit data and infrared transmit data. In this mode, the TX signal will be HIGH during reset, or idle (no data). I UART channel A - D receive data. Normal receive data input must idle HIGH. O UART channels A - D Request-to-Send (active low) or general purpose output. If these outputs are not used, leave them unconnected. I UART channels A - D Clear-to-Send (active low) or general purpose input. These inputs should be connected to VCC when not used. Modem or Serial I/O Interface TXA 8 17 TXB 10 19 TXC 39 51 TXD 41 53 RXA 62 7 RXB 20 29 RXC 29 41 RXD 51 63 RTSA# 5 14 RTSB# 13 22 RTSC# 36 48 RTSD# 44 56 CTSA# 2 11 CTSB# 16 25 CTSC# 33 45 CTSD# 47 59 9/4/19 Rev 4.0.2 3 ST16C554 / ST16C554D / ST68C554 2.97V to 5.5V Quad UART with 16-Byte FIFO Data Sheet Pin Descriptions Table 1: (Continued) Pin Descriptions Name LQFP64 PLCC68 DTRA# 3 12 DTRB# 15 24 DTRC# 34 46 DTRD# 46 58 DSRA# 1 10 DSRB# 17 26 DSRC# 32 44 DSRD# 48 60 CDA# 64 9 CDB# 18 27 CDC# 31 43 CDD# 49 61 RIA# 63 8 RIB# 19 28 RIC# 30 42 RID# 50 62 Type Description O UART channels A - D Data-Terminal-Ready (active low) or general purpose output. If these outputs are not used, leave them unconnected. I UART channels A - D Data-Set-Ready (active low) or general purpose input. This input should be connected to VCC when not used. This input has no effect on the UART. I UART channels A-D Carrier-Detect (active low) or general purpose input. This input should be connected to VCC when not used. This input has no effect on the UART. I UART channels A-D Ring-Indicator (active low) or general purpose input. This input should be connected to VCC when not used. This input has no effect on the UART. Ancillary Signals XTAL1 25 35 I Crystal or external clock input. XTAL2 26 36 O Crystal or buffered clock output. I Intel or Motorola bus select (input with internal pull-up). When the 16/68# pin is HIGH for 16 or Intel Mode, the device will operate in the Intel bus type of interface. When the 16/68# pin is LOW for 68 or Motorola Mode, the device will operate in the Motorola bus type of interface. Motorola bus interface is not available on the 64 pin package. 16/68# - 31 RESET (RESET#) 27 37 I When the 16/68# pin is HIGH for Intel bus interface, this input becomes the Reset pin (active high). In this case, a 40ns minimum HIGH pulse on this pin will reset the internal registers and all outputs. The UART transmitter output will be held HIGH, the receiver input will be ignored, and outputs are reset during the reset period (Table 16). When the 16/68# pin is at LOW for Motorola bus interface, this input becomes the Reset# pin (active low). This pin functions similarly, but instead of a HIGH pulse, a 40ns minimum LOW pulse will reset the internal registers and outputs. Motorola bus interface is not available on the 64 pin package. VCC 4, 21, 35, 52 13, 30, 47, 64 Pwr 2.97V to 5.5V power supply. GND 14, 28, 45, 61 6, 23, 40, 57 Pwr Power supply common, ground. N.C. - - No connection. These pins are not used in either the Intel or Motorola bus modes. Pin type: I = Input, O = Output, I/O = Input / Output, OD = Output, Open Drain. 9/4/19 Rev 4.0.2 4 ST16C554 / ST16C554D / ST68C554 2.97V to 5.5V Quad UART with 16-Byte FIFO Data Sheet Product Description 2.0 Product Description The ST16C554 integrates the functions of 4 enhanced 16C550 Universal Asynchronous Receiver and Transmitters (UARTs). Each UART is independently controlled and has its own set of device configuration registers. The configuration registers set is 16550 UART compatible for control, status, and data transfer. Additionally, each UART channel has 16 bytes of transmit and receive FIFOs, a programmable baud rate generator and data rate up to 1.5Mbps at 5V. The ST16C554 can operate from 2.97 to 5.5 volts. The ST16C554 is fabricated with an advanced CMOS process. 2.1 Enhanced FIFO The ST16C554 QUART provides a solution that supports 16 bytes of transmit and receive FIFO memory, instead of one byte in the ST16C454. The ST16C554 is designed to work with high performance data communication systems that require fast data processing time. Increased performance is realized in the ST16C554 by the larger transmit and receive FIFOs and receiver FIFO trigger level control. This allows the external processor to handle more networking tasks within a given time. This increases the service interval giving the external CPU additional time for other applications and reducing the overall UART interrupt servicing time. 2.3 Data Rate The ST16C554 is capable of operation up to 1.5 Mbps at 5V. The device can operate at 5V with a crystal or external clock of up to 24MHz. With a typical crystal of 14.7456MHz and through a software option, the user can set the sampling rate for data rates of up to 921.6kbps. 2.4 Enhanced Features The rich feature set of the ST16C554 is available through the internal registers. Selectable receive FIFO trigger levels, programmable baud rates, infrared encoder and decoder interface, and modem interface controls are all standard features. In the 16 mode, INTSEL and MCR bit-3 can be configured to provide a software controlled or continuous interrupt capability. For backward compatibility to the ST16C554, the 64-pin LQFP does not have the INTSEL pin. Instead, the ST16C554DIQ and ST16C554DCQ operate in the continuous interrupt enable mode by internally bonding INTSEL to VCC. The ST16C554CQ operates in conjunction with MCR bit-3 by internally bonding INTSEL to GND. 2.2 Intel or Motorola Data Bus Interface The ST16C554 provides a single host interface for all 4 UARTs and supports Intel or Motorola microprocessor (CPU) data bus interfaces. The Intel bus compatible interface allows direct interconnect to Intel compatible type of CPUs using IOR#, IOW# and CSA#, CSB#, CSC# and CSD# inputs for data bus operation. The Motorola bus compatible interface instead uses the R/W#, CS#, A3 and A4 signals for data bus transactions. Few data bus interface signals change their functions depending on the user’s selection, see pin description for details. The Intel or Motorola bus interface selection is made through the 16/68# (pin 31 of the PLCC package). 9/4/19 Rev 4.0.2 5 ST16C554 / ST16C554D / ST68C554 2.97V to 5.5V Quad UART with 16-Byte FIFO Data Sheet Functional Descriptions 3.0 Functional Descriptions 3.1 CPU Interface The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and write transactions. The ST16C554 data interface supports the Intel compatible types of CPUs and it is compatible to the industry standard 16C550 UART. No clock (oscillator nor external clock) is required for a data bus transaction. Each bus cycle is asynchronous using CS# A - D, IOR# and IOW# or CS#, R/W#, A4 and A3 inputs. All four UART channels share the same data bus for host operations. A typical data bus interconnection for Intel and Motorola Modes is shown in Figure 6. D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 A0 A1 A2 TXA RXA UART Channel A DTRA# RTSA# CTSA# DSRA# CDA# IOW# UART_CSA# UART_CSB# UART_CSC# UART_CSD# CSA# CSB# CSC# CSD# UART_INTA INTA UART_INTB INTB UART_INTC INTC UART_INTD INTD UART_RESET Serial Interface of RS-232 RIA# IOR# IOR# IOW# VCC VCC UART Channel B UART Channel C UART Channel D Similar to Ch A Serial Interface of RS-232 Similar to Ch A Similar to Ch A RESET VCC GND 16/68# Intel Data Bus (16 Mode) Interconnections D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 A0 A1 A3 A4 CSB# CSC# CSD# VCC RXA UART Channel A DTRA# RTSA# CTSA# Serial Interface of RS-232 DSRA# CDA# RIA# UART Channel B Similar to Ch A IOW# R/W# CSA# VCC UART_IRQ# (no connect) (no connect) (no connect) UART_RESET# IOR# VCC TXA A2 VCC UART_CS# VCC INTA INTB INTC INTD RESET# 16/68# UART Channel C UART Channel D Similar to Ch A Serial Interface of RS-232 Similar to Ch A GND Motorola Data Bus (68 Mode) Interconnections Figure 6: ST16C554D Typical Intel and Motorola Data Bus Interconnections 9/4/19 Rev 4.0.2 6 ST16C554 / ST16C554D / ST68C554 2.97V to 5.5V Quad UART with 16-Byte FIFO Data Sheet 3.2 Device Reset The RESET input resets the internal registers and the serial interface outputs in all channels to their default state (see Table 16). An active high pulse of longer than a 40ns duration will be required to activate the reset function in the device. Following a power-on reset or an external reset, the ST16C554 is software compatible with previous generation of UARTs, the 16C454 and 16C554. 3.3 Channel Selection The UART provides the user with the capability to bidirectionally transfer information between an external CPU and an external serial communication device. During Intel Bus Mode (16/68# pin is connected to VCC), a logic 0 on chip select pins CSA#, CSB#, CSC#, or CSD# allows the user to select UART channel A, B, C, or D to configure, send transmit data and unload receive data to and from the UART. Selecting all four UARTs can be useful during power up initialization to write to the same internal registers, but do not attempt to read from all four UARTs simultaneously. Individual channel select functions are shown in Table 2. Table 2: Channel A - D Select in 16 Mode CSA# CSB# CSC# CSD# Function 1 1 1 1 UART de-selected 0 1 1 1 Channel A selected 1 0 1 1 Channel B selected 1 1 0 1 Channel C selected 1 1 1 0 Channel D selected 0 0 0 0 Channels A - D selected Device Reset During Motorola Bus Mode (16/68# pin is connected to GND), the package interface pins are configured for connection with Motorola, and other popular microprocessor bus types. In this mode, the ST16C554 decodes two additional addresses, A3 and A4, to select one of the four UART ports. The A3 and A4 address decode function is used only in the Motorola Bus Mode. See Table 3. Table 3: Channel A - D Select in 68 Mode CS# A4 A3 Function 1 X X UART de-selected 0 0 0 Channel A selected 0 0 1 Channel B selected 0 1 0 Channel C selected 0 1 1 Channel D selected 3.4 Internal Registers of Channels A - D Each UART channel in the ST16C554 has a set of enhanced registers for controlling, monitoring and data loading and unloading. The configuration register set is compatible to those already available in the standard single 16C550. These registers function as data holding registers (THR / RHR), interrupt status and control registers (ISR / IER), a FIFO control register (FCR), receive line status and control registers (LSR / LCR), modem status and control registers (MSR / MCR), programmable data rate (clock) divisor registers (DLL / DLM), and a user accessible scratchpad register (SPR). All the register functions are discussed in full detail later in UART Internal Registers. 3.5 INT Outputs for Channels A - D The interrupt outputs change according to the operating mode and enhanced features setup. Table 4 and Table 5 summarize the operating behavior for the transmitter and receiver. Also see Figure 20 through Figure 25. Table 4: INT Pin Operation for Channel A - D Transmitters INT Pin FCR Bit-0 = 0 (FIFO Disabled) LOW HIGH 9/4/19 FCR Bit-0 = 1 (FIFO Enabled) FCR Bit-3 = 0 (DMA Mode Disabled) FCR Bit-3 = 1 (DMA Mode Enabled) A byte in THR FIFO above trigger level FIFO above trigger level THR empty FIFO below trigger level or FIFO empty FIFO below trigger level or FIFO empty Rev 4.0.2 7 ST16C554 / ST16C554D / ST68C554 2.97V to 5.5V Quad UART with 16-Byte FIFO Data Sheet DMA Mode Table 5: INT Pin Operation for Channel A - D Receivers INT Pin FCR Bit-0 = 0 (FIFO Disabled) LOW HIGH FCR Bit-0 = 1 (FIFO Enabled) FCR Bit-3 = 0 (DMA Mode Disabled) FCR Bit-3 = 1 (DMA Mode Enabled) No data FIFO below trigger level FIFO below trigger level 1 byte FIFO above trigger level FIFO above trigger level 3.6 DMA Mode The device does not support direct memory access. The DMA Mode (a legacy term) in this document does not mean “direct memory access”, but refers to data block transfer operation. The DMA mode affects the state of the RXRDY# A - D and TXRDY# A - D output pins. The transmit and receive FIFO trigger levels provide additional flexibility to the user for block mode operation. The LSR bits 5-6 provide an indication when the transmitter is empty or has empty locations for more data. The user can optionally operate the transmit and receive FIFO in the DMA mode (FCR bit-3 = 1). When the transmit and receive FIFOs are enabled and the DMA mode is disabled (FCR bit-3 = 0), the ST16C554 is placed in Single-Character Mode for data transmit or receive operation. When DMA Mode is enabled (FCR bit-3 = 1), the user takes advantage of block mode operation by loading or unloading the FIFO in a block sequence determined by the programmed trigger level. The following table shows their behavior. Also see Figure 20 through Figure 25. Table 6: TXRDY# and RXRDY# Outputs in FIFO and DMA Mode for Channels A - D FCR Bit-0 = 0 (FIFO Disabled) Pins RXRDY# TXRDY# FCR Bit-0 = 1 (FIFO Enabled) FCR Bit-3 = 0 (DMA Mode Disabled) FCR Bit-3 = 1 (DMA Mode Enabled) LOW 1 byte At least 1 byte in FIFO HIGH No data FIFO empty HIGH to LOW transition when FIFO reaches the trigger level, or timeout occurs. LOW to HIGH transition when FIFO empties. LOW THR empty FIFO empty FIFO has at least 1 empty location HIGH Byte in THR At least 1 byte in FIFO FIFO is full 3.7 Crystal Oscillator or External Clock Input The ST16C554 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for both UART sections in the device. The CPU data bus does not require this clock for bus operation. The crystal oscillator provides a system clock to the Baud Rate Generators (BRG) section found in each of the UARTs. XTAL1 is the input to the oscillator or external clock buffer input with XTAL2 pin being the output. For programming details, see Programmable Baud Rate Generator. Alternatively, an external clock can be connected to the XTAL1 pin to clock the internal baud rate generator for standard or custom rates. For further reading on oscillator circuit please see Application Note DAN108 on MaxLinear’s web site. The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant, fundamental frequency with 10 - 22pF capacitance load, ESR of 20 - 120Ω and 100ppm frequency tolerance) connected externally between the XTAL1 and XTAL2 pins. Typical oscillator connections are shown in Figure 7. R=300K to 400K XTAL1 C1 22-47pF 14.7456 MHz XTAL2 C2 22-47pF Figure 7: Typical Crystal Connections 9/4/19 Rev 4.0.2 8 ST16C554 / ST16C554D / ST68C554 Data Sheet Programmable Baud Rate Generator 3.8 Programmable Baud Rate Generator divisor is unknown (DLL = 0xXX and DLM = 0xXX) and should be initialized after power up. Programming the Baud Rate Generator Registers DLL and DLM provide the capability for selecting the operating data rate. Table 7 shows the standard data rates available with a 14.7456MHz crystal or external clock. Each UART has its own Baud Rate Generator (BRG) for the transmitter and receiver. The BRG further divides this clock by a programmable divisor between 1 and (216 - 1) to obtain a 16X sampling rate clock of the serial data rate. The sampling rate clock is used by the transmitter for data bit shifting and the receiver for data sampling. The BRG To Other Channels DLL and DLM Registers XTAL1 XTAL2 Crystal Osc / Buffer Programmable Baud Rate Generator Logic 16 X Sampling Rate Clock to Transmitter and Receiver Figure 8: Baud Rate Generator Table 7: Typical Data Rates with a 14.7456MHz Crystal or External Clock Output Data Rate MCR Bit-7=1 Output Data Rate MCR Bit-7=0 (Default) Divisor for 16x Clock (Decimal) Divisor for 16x Clock (HEX) DLM Program Value (HEX) DLL Program Value (HEX) Data Rate Error (%) 100 400 2304 900 09 00 0 600 2400 384 180 01 80 0 1200 4800 192 C0 00 C0 0 2400 9600 96 60 00 60 0 4800 19.2k 48 30 00 30 0 9600 38.4k 24 18 00 18 0 19.2k 76.8k 12 0C 00 0C 0 38.4k 153.6k 6 06 00 06 0 57.6k 230.4k 4 04 00 04 0 115.2k 460.8k 2 02 00 02 0 230.4k 921.6k 1 01 00 01 0 9/4/19 Rev 4.0.2 9 ST16C554 / ST16C554D / ST68C554 2.97V to 5.5V Quad UART with 16-Byte FIFO Data Sheet Transmitter 3.9 Transmitter The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 16 bytes of FIFO which includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X internal sampling clock. A bit time is 16X clock periods. The transmitter sends the startbit followed by the number of data bits, inserts the proper parity-bit if enabled, and adds the stop-bit(s). The status of the FIFO and TSR are reported in the Line Status Register (LSR bit-5 and bit-6). 3.9.3 Transmitter Operation in FIFO Mode The host may fill the transmit FIFO with up to 16 bytes of transmit data. The THR empty flag (LSR bit-5) is set whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the FIFO becomes empty. The transmit empty interrupt is enabled by IER bit-1. The TSR flag (LSR bit-6) is set when TSR and the FIFO becomes empty. 3.9.1 Transmit Holding Register (THR) - Write Only The transmit holding register is an 8-bit register providing a data interface to the host processor. The host writes a transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits, parity-bit and stopbit(s). The least-significant-bit (bit-0) becomes the first data bit to go out. The THR is the input register to the transmit FIFO of 16 bytes when FIFO operation is enabled by FCR bit-0. Every time a write operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data location. 3.9.2 Transmitter Operation in Non-FIFO Mode The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the data byte is transferred to TSR. The THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty. Data Byte 16X Clock Transmit Holding Register (THR) Transmit Shift Register (TSR) THR Interrupt (ISR bit-1) Enabled by IER bit-1 M S B L S B TXNOFIFO1 Figure 9: Transmitter Operation in Non-FIFO Mode 9/4/19 Transmit FIFO Transmit Data Byte 16X Clock THR Interrupt (ISR bit-1) when the TX FIFO becomes empty. FIFO is enabled by FCR bit-0 =1. Transmit Data Shift Register ( TSR) TXFIFO1 Figure 10: Transmitter Operation in FIFO Mode 3.10 Receiver The receiver section contains an 8-bit Receive Shift Register (RSR) and 16 bytes of FIFO which includes a bytewide Receive Holding Register (RHR). The RSR uses the 16X clock for timing. It verifies and validates every bit on the incoming character in the middle of each data bit. On the falling edge of a start or false start bit, an internal receiver counter starts counting at the 16X clock rate. After 8 clocks, the start bit period should be at the center of the start bit. At this time the start bit is sampled, and if it is still LOW it is validated. Evaluating the start bit in this manner prevents the receiver from assembling a false character. The rest of the data bits and stop bits are sampled and validated in this same manner to prevent false framing. If there were any error(s), they are reported in the LSR register bits 2 - 4. Upon unloading the receive data byte from RHR, the receive FIFO pointer is bumped and the error tags are immediately updated to reflect the status of the data byte in the RHR register. RHR can generate a receive data ready interrupt upon receiving a character or delay, until it reaches the FIFO trigger level. Furthermore, data delivery to the host is guaranteed by a receive data ready time-out interrupt when data is not received for 4 word lengths as defined by LCR[1:0] plus 12 bits time. This is equivalent to 3.7 - 4.6 character times. The RHR interrupt is enabled by IER bit-0. See Figure 11 and Figure 12. Rev 4.0.2 10 ST16C554 / ST16C554D / ST68C554 2.97V to 5.5V Quad UART with 16-Byte FIFO Data Sheet Receiver 3.10.1 Receive Holding Register (RHR) - Read Only The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift Register. It provides the receive data interface to the host processor. The RHR register is part of the receive FIFO of 16 bytes by 11-bit wide; the 3 extra bits are for the 3 error tags to be reported in LSR register. When the FIFO is enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After the RHR is read, the next character byte is loaded into the RHR and the errors associated with the current data byte are immediately updated in the LSR bits 2 - 4. 16X Clock Receive Data Shift Register (RSR) Error Tags in LSR bits 4:2 Receive Data Byte and Errors Data Bit Validation Receive Data Holding Register (RHR) Receive Data Characters RHR Interrupt (ISR bit-2) RXFIFO1 Figure 11: Receiver Operation in Non-FIFO Mode 1 6X C lo ck R eceive D ata S hift R eg iste r (R S R ) D ata B it V a lida tion E xample : - RX FIF O trigger level s elec ted at 8 bytes (S ee Note B elow ) 16 by tes by 11-bit w ide F IFO Error Tags (16-sets) Data falls to 4 Re ceive Data FIFO Error Tags in LSR bits 4:2 A skin g for send ing data w h en d ata falls b elow th e flo w con trol trigge r leve l to re start re m ote transm itte r. F IFO T rigger= 8 D ata fills to 14 R eceive D ata B yte a nd E rro rs R e ceive D a ta C ha ra cters R HR In terrup t (IS R bit-2) pro gram m ed for de sire d FIFO trigg er level. FIFO is E na ble d by FC R bit-0=1 Askin g for stopping d ata w he n da ta fills ab ove the flow co ntrol trigge r level to susp end rem o te tran sm itter. R ece ive Da ta R XFIFO 1 Figure 12: Receiver Operation in FIFO Mode 9/4/19 Rev 4.0.2 11 ST16C554 / ST16C554D / ST68C554 2.97V to 5.5V Quad UART with 16-Byte FIFO Data Sheet Internal Loopback 3.11 Internal Loopback The ST16C554 UART provides an internal loopback capability for system diagnostic purposes. The internal loopback mode is enabled by setting MCR register bit-4 to a logic 1. All regular UART functions operate normally. Figure 13 shows how the modem port signals are reconfigured. Transmit data from the Transmit Shift Register output is internally routed to the Receive Shift Register input, allowing the system to receive the same data that it was sending. The TX pin is held HIGH or at mark condition while RTS# and DTR# are de-asserted, and CTS#, DSR# CD# and RI# inputs are ignored. Important: The RX input must be held HIGH during the loopback test, else upon exiting the loopback test the UART may detect and report a false “break” signal. VCC TX A-D Transmit Shift Register (THR/FIFO) Receive Shift Register (RHR/FIFO) RX A-D VCC RTS# A-D Modem / General Purpose Control Logic Internal Data Bus Lines and Control Signals MCR bit-4=1 RTS# CTS# CTS# A-D VCC DTR# A-D DTR# DSR# DSR# A-D OP1# RI# OP2# CD# RI# A-D CD# A-D Figure 13: Internal Loopback in Channels A and B 9/4/19 Rev 4.0.2 12 ST16C554 / ST16C554D / ST68C554 2.97V to 5.5V Quad UART with 16-Byte FIFO Data Sheet UART Internal Registers 4.0 UART Internal Registers Each UART channel in the ST16C554 has its own set of configuration registers selected by address lines A0, A1, and A2 with a specific channel selected (see Table 2 and Table 3). The complete register set is shown in Table 8 and Table 9. Table 8: Internal Registers of UART Channels A and B A2, A1, A0 Addresses Register Read and Write Comments 16C550 Compatible Registers RHR - Receive Holding Register Read-only THR - Transmit Holding Register Write-only 0 0 DLL - Divisor LSB Read and write 0 0 1 DLM - Divisor MSB Read and write 0 0 1 IER - Interrupt Enable Register Read and write 0 1 0 ISR - Interrupt Status Register Read-only FCR - FIFO Control Register Write-only 0 1 1 LCR - Line Control Register Read and write 1 0 0 MCR - Modem Control Register Read and write 0 0 0 0 1 0 1 LSR - Line Status Register Read-only 1 1 0 MSR - Modem Status Register Read-only 1 1 1 SPR - Scratch Pad Register Read and write 9/4/19 Rev 4.0.2 LCR[7] = 0 LCR[7] = 1 LCR[7] = 0 LCR[7] = 0 13 ST16C554 / ST16C554D / ST68C554 2.97V to 5.5V Quad UART with 16-Byte FIFO Data Sheet UART Internal Registers Table 9: Internal Register Descriptions Address A2 - A0 Register Name Read / Write Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 Comment 16C550 Compatible Registers 000 RHR RD Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 000 THR WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 0 Modem Stat. Int. Enable RX Line Stat. Int. Enable TX Empty Int Enable RX Data Int. Enable 001 IER RD / WR 0 0 0 010 ISR RD FIFOs FIFOs 0 Enabled Enabled 0 INT Source Bit-3 INT INT Source Source Bit-2 Bit-1 INT Source Bit-0 010 FCR WR RX FIFO Trigger RX FIFO Trigger 0 0 DMA Mode Enable TX FIFO Reset RX FIFO Reset FIFOs Enable 011 LCR RD / WR Divisor Enable Set TX Break Set Parity Even Parity Parity Enable Stop Bits Word Length Bit-1 Word Length Bit-0 RTS# Rsvd Output (OP1#) Control DTR# Output Control 100 MCR RD / WR 0 0 0 INT Internal Output Loopback Enable Enable (OP2#) THR, TSR Empty THR Empty RX RX RX Break Framing Parity Error Error RX RX Overrun Data Error Ready 101 LSR RD / WR RX FIFO Global Error 110 MSR RD / WR CD# Input RI# Input DSR# Input CTS# Input Delta CD# Delta RI# Delta DSR# Delta CTS# 111 SPR RD / WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 LCR[7] = 0 LCR[7] = 0 Baud Rate Generator Divisor 000 DLL RD / WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 001 DLM RD / WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 9/4/19 Rev 4.0.2 LCR[7]=1 LCR0xBF 14 ST16C554 / ST16C554D / ST68C554 Data Sheet Internal Register Descriptions 5.0 Internal Register Descriptions 5.1 Receive Holding Register (RHR) - Read-Only LSR, either or both can be used in the polled mode by selecting the respective transmit or receive control bit(s). See Receiver on page 10. B. LSR bit-1 indicates an overrun error has occurred and that data in the FIFO may not be valid. 5.2 Transmit Holding Register (THR) - Write-Only See Transmitter on page 10. 5.3 Interrupt Enable Register (IER) Read and Write A. LSR bit-0 indicates there is data in RHR or RX FIFO. C. LSR bits 2 - 4 provide the type of receive data errors encountered for the data byte in RHR, if any. D. LSR bit-5 indicates THR is empty. E. LSR bit-6 indicates both the transmit FIFO and TSR are empty. F. LSR bit-7 indicates a data error in at least one character in the RX FIFO. The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status, and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR). IER[0]: RHR Interrupt Enable 5.3.1 IER Versus Receive FIFO Interrupt Mode Operation ■ The receive data ready interrupt will be issued when RHR has a data character in the non-FIFO mode or when the receive FIFO has reached the programmed trigger level in the FIFO mode. ■ When the receive FIFO (FCR bit-0 = 1) and receive interrupts (IER bit-0 = 1) are enabled, the RHR interrupts (see ISR bits 2 and 3) status will reflect the following: Logic 1 = Enable the receiver data ready interrupt. IER[1]: THR Interrupt Enable A. The receive data available interrupts are issued to the host when the FIFO has reached the programmed trigger level. It will be cleared when the FIFO drops below the programmed trigger level. B. FIFO level will be reflected in the ISR register when the FIFO trigger level is reached. Both the ISR register status bit and the interrupt will be cleared when the FIFO drops below the trigger level. C. The receive data ready bit (LSR bit-0) is set as soon as a character is transferred from the shift register to the receive FIFO. It is reset when the FIFO is empty. 5.3.2 IER Versus Receive and Transmit FIFO Polled Mode Operation When FCR bit-0 equals a logic 1 for FIFO enable, resetting IER bits 0 - 3 enables the FIFO polled mode of operation. Since the receiver and transmitter have separate bits in the 9/4/19 Logic 0 = Disable the receive data ready interrupt (default). This bit enables the Transmit Ready Interrupt which is issued whenever the THR becomes empty. If the THR is empty when this bit is enabled, an interrupt will be generated. ■ ■ Logic 0 = Disable Transmit Ready interrupt (default). Logic 1 = Enable Transmit Ready interrupt. IER[2]: Receive Line Status Interrupt Enable If any of the LSR register bits 1, 2, 3, or 4 is a logic 1, it will generate an interrupt to inform the host controller about the error status of the current data byte in FIFO. LSR bit-1 generates an interrupt immediately when an overrun occurs. LSR bits 2 - 4 generate an interrupt when the character in the RHR has an error. ■ ■ Rev 4.0.2 Logic 0 = Disable the receiver line status interrupt (default). Logic 1 = Enable the receiver line status interrupt. 15 ST16C554 / ST16C554D / ST68C554 Data Sheet Interrupt Status Register (ISR) 5.4.2 Interrupt Clearing IER[3]: Modem Status Interrupt Enable ■ ■ Logic 0 = Disable the modem status register interrupt (default). Logic 1 = Enable the modem status register interrupt. IER[7:4]: Reserved (Default 0) 5.4 Interrupt Status Register (ISR) The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the ISR will give the user the current highest pending interrupt level to be serviced, others are queued up to be serviced next. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt Source Table, Table 10, shows the data values (bit 0 - 3) for the interrupt priority levels and the interrupt sources associated with each of these interrupt levels. ■ ■ LSR interrupt is cleared by a read to the LSR register. ■ ■ RXRDY time-out interrupt is cleared by reading RHR. ■ RXRDY interrupt is cleared by reading data until the FIFO falls below the trigger level. TXRDY interrupt is cleared by a read to the ISR register or by writing to THR. MSR interrupt is cleared by a read to the MSR register. ISR[0]: Interrupt Status ■ ■ Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt service routine. Logic 1 = No interrupt pending (default condition). ISR[3:1]: Interrupt Status These bits indicate the source for a pending interrupt at interrupt priority levels (see Interrupt Source Table 10). 5.4.1 Interrupt Generation ISR[5:4]: Reserved (Default 0) ■ ■ ■ LSR is by any of the LSR bits 1, 2, 3, and 4. ISR[7:6]: FIFO Enable Status ■ TXRDY is by THR empty (non-FIFO mode) or TX FIFO empty (FIFO mode). ■ RXRDY is by RX trigger level. RXRDY time-out is by a 4-character plus 12 bits delay timer. These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are enabled. MSR is by any of the MSR bits 0, 1, 2, and 3. Table 10: Interrupt Source and Priority Level Priority Level ISR Register Status Bits Bit-3 Bit-2 Bit-1 Bit-0 1 0 1 1 0 LSR (Receiver Line Status Register) 2 1 1 0 0 RXRDY (Receive Data Time-out) 3 0 1 0 0 RXRDY (Received Data Ready) 4 0 0 1 0 TXRDY (Transmit Empty) 5 0 0 0 0 MSR (Modem Status Register) - 0 0 0 1 None (default) 9/4/19 Source of Interrupt Rev 4.0.2 16 ST16C554 / ST16C554D / ST68C554 Data Sheet FIFO Control Register (FCR) - Write-Only 5.5 FIFO Control Register (FCR) - Write-Only This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO trigger levels, and select the DMA mode. The DMA and FIFO modes are defined as follows: FCR[0]: TX and RX FIFO Enable ■ ■ Logic 0 = Disable the transmit and receive FIFO (default). Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are written or they will not be programmed. FCR[1]: RX FIFO Reset This bit is only active when FCR bit-0 is a ‘1’. ■ ■ Logic 0 = No receive FIFO reset (default). Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not cleared or altered). This bit will return to a logic 0 after resetting the FIFO. FCR[2]: TX FIFO Reset FCR Bit-7 FCR Bit-6 Receive Trigger Level 0 0 1 0 1 4 1 0 8 1 1 14 5.6 Line Control Register (LCR) - Read and Write The Line Control Register is used to specify the asynchronous data communication format. The word or character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. LCR[1:0]: TX and RX Word Length Select These two bits specify the word length to be transmitted or received. Table 12: TX and RX Word Length This bit is only active when FCR bit-0 is a ‘1’. ■ ■ p Table 11: Receive FIFO Trigger Level Selection LCR Bit-1 LCR Bit-0 Word Length Logic 0 = No transmit FIFO reset (default). 0 0 5 (default) Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not cleared or altered). This bit will return to a logic 0 after resetting the FIFO. 0 1 6 1 0 7 1 1 8 FCR[3]: DMA Mode Select LCR[2]: TX and RX Stop-bit Length Select Controls the behavior of the TXRDY# and RXRDY# pins. See DMA operation section for details. The length of stop bit is specified by this bit in conjunction with the programmed word length. ■ ■ Table 13: TX and RX Stop-Bit Length Logic 0 = Normal Operation (default). Logic 1 = DMA Mode. FCR[5:4]: Reserved (Default 0) FCR[7:6]: Receive FIFO Trigger Select LCR Bit-2 Word Length Stop Bit Length (Bit Time) 0 5,6,7,8 1 (default) 1 5 1-1/2 1 6,7,8 2 (logic 0 = default, RX trigger level = 1) These 2 bits are used to set the trigger level for the receive FIFO. The UART will issue a receive interrupt when the number of the characters in the FIFO crosses the trigger level. Table 11 shows the complete selections. 9/4/19 Rev 4.0.2 17 ST16C554 / ST16C554D / ST68C554 Data Sheet Modem Control Register (MCR) or General Purpose Outputs Control LCR[3]: TX and RX Parity Select Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for a data integrity check. See Table 14 for parity selection summary below. ■ ■ Logic 0 = No parity. Logic 1 = A parity bit is generated during the transmission while the receiver checks for parity error of the data character received. LCR[4]: TX and RX Parity Select If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR bit-4 selects the even or odd parity format. ■ ■ ■ ■ Logic 0 = No TX break condition (default). Logic 1 = Forces the transmitter output (TX) to a “space”, logic 0, for alerting the remote receiver of a line break condition. LCR[7]: Baud Rate Divisors Enable Baud rate generator divisor (DLL / DLM) enable. ■ ■ Logic 0 = Data registers are selected (default). Logic 1 = Divisor latch registers are selected. 5.7 Modem Control Register (MCR) or General Purpose Outputs Control - Read and Write Logic 0 = ODD Parity is generated by forcing an odd number of logic 1’s in the transmitted character. The receiver must be programmed to check the same format (default). Logic 1 = EVEN Parity is generated by forcing an even number of logic 1’s in the transmitted character. The receiver must be programmed to check the same format. LCR[5]: TX and RX Parity Select If the parity bit is enabled, LCR bit-5 selects the forced parity format. The MCR register is used for controlling the serial modem interface signals or general purpose inputs and outputs. MCR[0]: DTR# Output The DTR# pin is a modem control output. If the modem interface is not used, this output may be used as a general purpose output. ■ ■ ■ ■ LCR bit-5 = logic 0, parity is not forced (default). ■ LCR bit-5 = logic 1 and LCR bit-4 = logic 1, parity bit is forced to LOW for the transmit and receive data. LCR bit-5 = logic 1 and LCR bit-4 = logic 0, parity bit is forced to HIGH for the transmit and receive data. LCR Bit-5 LCR Bit-4 LCR Bit-3 Parity Selection Logic 1 = Force DTR# output LOW. MCR[1]: RTS# Output The RTS# pin is a modem control output. If the modem interface is not used, this output may be used as a general purpose output. ■ ■ Table 14: Parity Selection Logic 0 = Force DTR# output HIGH (default). Logic 0 = Force RTS# output HIGH (default). Logic 1 = Force RTS# output LOW. X X 0 No parity 0 0 1 Odd parity MCR[2]: Reserved 0 1 1 Even parity 1 0 1 Force parity to mark, HIGH 1 1 1 Forced parity to space, LOW OP1# is not available as an output pin on the ST16C554. However, it is available for use during Internal Loopback Mode. In the Loopback Mode, this bit is used to write the state of the modem RI# interface signal. LCR[6]: Transmit Break Enable MCR[3]: INT Output Enable When enabled, the Break Control Bit causes a break condition to be transmitted (the TX output is forced to a “space’, logic 0 state). This condition remains, until disabled by setting LCR bit-6 to a logic 0. Enable or disable INT outputs to become active or in threestate. This function is associated with the INTSEL input, see below table for details. This bit is also used to control the OP2# signal during internal loopback mode. INTSEL pin must be LOW during 68 mode. 9/4/19 Rev 4.0.2 18 ST16C554 / ST16C554D / ST68C554 Data Sheet ■ ■ Line Status Register (LSR) - Read and Write Logic 0 = INT (A - D) outputs disabled (three state) in the 16 mode (default). During internal loopback mode, OP2# is HIGH. Logic 1 = INT (A - D) outputs enabled (active) in the 16 mode. During internal loopback mode, OP2# is LOW. LSR[2]: Receive Data Parity Error Tag ■ ■ Table 15: INT Output Modes INTSEL Pin MCR Bit-3 INT A - D Outputs in 16 Mode 0 0 Three-State 0 1 Active 1 X Active ■ ■ ■ ■ Logic 1 = Enable local loopback mode, see loopback section and Table 13. 5.8 Line Status Register (LSR) - Read and Write LSR[0]: Receive Data Ready Indicator Logic 0 = No break condition (default). Logic 1 = The receiver received a break signal (RX was LOW for at least a one character frame time). In the FIFO mode, only one break character is loaded into the FIFO. The break indication remains until the RX input returns to the idle condition, “mark” or HIGH. This bit is the Transmit Holding Register empty indicator. The THR bit is set to a logic 1 when the last data byte is transferred from the Transmit Holding Register to the Transmit Shift Register. The bit is reset to logic 0 concurrently with the data loading to the Transmit Holding Register by the host. In the FIFO mode, this bit is set when the transmit FIFO is empty. It is cleared when the transmit FIFO contains at least 1 byte. LSR[6]: THR and TSR Empty Flag Logic 0 = No data in receive holding register or FIFO (default). This bit is set to a logic 1 whenever the transmitter goes idle. It is set to logic 0 whenever either the THR or TSR contains a data character. In the FIFO mode, this bit is set to a logic 1 whenever the transmit FIFO and Transmit Shift Register are both empty. Logic 1 = Data has been received and can be read from the receive holding register or RX FIFO. LSR[1]: Receiver Overrun Flag ■ ■ Logic 1 = Framing error. The receive character did not have a valid stop bit(s). This error is associated with the character available for reading in RHR. LSR[5]: Transmit Holding Register Empty Flag This register is writeable, but it is not recommended. The LSR provides the status of data transfers between the UART and the host. If IER bit-2 is enabled, LSR bit-1 will generate an interrupt immediately and LSR bits 2-4 will generate an interrupt when a character with an error is in the RHR. ■ Logic 0 = No framing error (default). LSR[4]: Receive Break Tag Logic 0 = Disable loopback mode (default). MCR[7:5]: Reserved (Default 0) ■ Logic 1 = Parity error. The receive character in RHR does not have correct parity information and is suspect. This error is associated with the character available for reading in RHR. LSR[3]: Receive Data Framing Error Tag MCR[4]: Internal Loopback Enable ■ ■ Logic 0 = No parity error (default). Logic 0 = No overrun error (default). LSR[7]: Receive FIFO Data Error Flag Logic 1 = Overrun error. A data overrun error condition occurred in the Receive Shift Register. This happens when additional data arrives while the FIFO is full. In this case, the previous data in the Receive Shift Register is overwritten. Note that under this condition the data byte in the Receive Shift Register is not transferred into the FIFO, therefore the data in the FIFO is not corrupted by the error. ■ ■ 9/4/19 Rev 4.0.2 Logic 0 = No FIFO error (default). Logic 1 = A global indicator for the sum of all error bits in the RX FIFO. At least one parity error, framing error, or break indication is in the FIFO data. This bit clears when there is no more error(s) in any of the bytes in the RX FIFO. 19 ST16C554 / ST16C554D / ST68C554 Data Sheet Modem Status Register (MSR) - Read and Write 5.9 Modem Status Register (MSR) - Read and Write This register is writeable, but it is not recommended. The MSR provides the current state of the modem interface input signals. The lower four bits of this register are used to indicate the changed information. These bits are set to a logic 1 whenever a signal from the modem changes state. These bits may be used for general purpose inputs when they are not used with modem signals. MSR[0]: Delta CTS# Input Flag ■ ■ MSR[5]: DSR Input Status Logic 1 = The CTS# input has changed state since the last time it was monitored. A modem status interrupt will be generated if the MSR interrupt is enabled (IER bit-3). Normally this bit is the complement of the DSR# input. In the loopback mode, this bit is equivalent to the DTR# bit in the MCR register. The DSR# input may be used as a general purpose input when the modem interface is not used. MSR[6]: RI Input Status Logic 0 = No change on DSR# input (default). Logic 1 = The DSR# input has changed state since the last time it was monitored. A modem status interrupt will be generated if the MSR interrupt is enabled (IER bit-3). MSR[2]: Delta RI# Input Flag ■ ■ Logic 0 = No change on RI# input (default). Logic 1 = The RI# input has changed from LOW to HIGH, ending of the ringing signal. A modem status interrupt will be generated if the MSR interrupt is enabled (IER bit-3). MSR[7]: CD Input Status 5.10 Scratch Pad Register (SPR) - Read and Write Logic 0 = No change on CD# input (default). Logic 1 = Indicates that the CD# input has changed state since the last time it was monitored. A modem status interrupt will be generated if the MSR interrupt is enabled (IER bit-3). 9/4/19 Normally this bit is the complement of the RI# input. In the loopback mode, this bit is equivalent to bit-2 in the MCR register. The RI# input may be used as a general purpose input when the modem interface is not used. Normally this bit is the complement of the CD# input. In the loopback mode, this bit is equivalent to bit-3 in the MCR register. The CD# input may be used as a general purpose input when the modem interface is not used. MSR[3]: Delta CD# Input Flag ■ ■ A HIGH on the CTS# pin will stop the UART transmitter as soon as the current character has finished transmission. A LOW will resume data transmission. Normally the MSR bit4 is the compliment of the CTS# input. However in the loopback mode, this bit is equivalent to the RTS# bit in the MCR register. The CTS# input may be used as a general purpose input when the modem interface is not used. Logic 0 = No change on CTS# input (default). MSR[1]: Delta DSR# Input Flag ■ ■ MSR[4]: CTS Input Status This is a 8-bit general purpose register for the user to store temporary data. Rev 4.0.2 20 ST16C554 / ST16C554D / ST68C554 Data Sheet Baud Rate Generator Registers (DLL and DLM) - Read and Write 5.11 Baud Rate Generator Registers (DLL and DLM) - Read and Write These registers make-up the value of the baud rate divisor. The concatenation of the contents of DLM and DLL gives the 16-bit divisor value. See Programmable Baud Rate Generator on page 9. Table 16: UART Reset Conditions for Channels A - D Item Reset State Registers DLM, DLL DLM and DLL are unknown upon power up. They do not reset when the Reset Pin is asserted. RHR Bits 7 - 0 = 0xXX THR Bits 7 - 0 = 0xXX IER Bits 7 - 0 = 0x00 FCR Bits 7 - 0 = 0x00 ISR Bits 7 - 0 = 0x01 LCR Bits 7 - 0 = 0x00 MCR Bits 7 - 0 = 0x00 LSR Bits 7 - 0 = 0x60 MSR Bits 3 - 0 = Logic 0 Bits 7 - 4 = Logic levels of the inputs inverted SPR Bits 7 - 0 = 0xFF I/O Signals TX HIGH IRTX LOW RTS# HIGH DTR# HIGH RXRDY# HIGH TXRDY# LOW INT (16 Mode) LOW IRQ# (68 Mode) HIGH (INTSEL = LOW) 9/4/19 Rev 4.0.2 21 ST16C554 / ST16C554D / ST68C554 2.97V to 5.5V Quad UART with 16-Byte FIFO Data Sheet Specifications 6.0 Specifications 6.1 Absolute Maximum Ratings Table 17: Absolute Maximum Ratings Parameter Minimum Maximum Units 7.0 V VCC + 0.3V V Power supply range Voltage at any pin GND – 0.3 Operating temperature See Ordering Information. Storage temperature –65 Package Dissipation 150 °C 500 mW Table 18: Typical Package Thermal Resistance Data(1) Package ѲJA ѲJC Units LQFP64 50 11 °C/W PLCC68 46 17 °C/W 1. Margin of error: ±15% 6.2 Electrical Characteristics 6.2.1 DC Electrical Characteristics Unless otherwise noted: TA = 0°C - 70°C (–40°C to +85°C for industrial grade package), VCC = 2.97V to 5.5V . Table 19: Electrical Characteristics Limits (5.0V) Parameter VILCK Clock input low level -0.3 0.6 -0.3 0.6 V VIHCK Clock input high level 2.4 VCC 3.0 VCC V VIL Input low voltage -0.3 0.8 -0.3 0.8 V VIH Input high voltage 2.0 VCC 2.2 VCC V VOL Output low voltage 0.4 V VOH Output high voltage IIL Input low leakage current ±10 ±10 µA IIH Input high leakage current ±10 ±10 µA CIN Input pin capacitance 5 5 pF ICC Power supply current 3 6 mA 9/4/19 Conditions Limits (3.3V) Symbol Minimum Maximum Minimum IOL = 5mA IOL = 4mA 0.4 IOH = -5mA IOH = -1mA Rev 4.0.2 Maximum Units V 2.4 V 2.0 V 22 ST16C554 / ST16C554D / ST68C554 2.97V to 5.5V Quad UART with 16-Byte FIFO Data Sheet Electrical Characteristics 6.2.2 AC Electrical Characteristics TA = 0°C - 70°C (–40°C to +85°C for industrial grade package), VCC = 2.97V to 5.5V, 70pF load where applicable. Table 20: AC Electrical Characteristics Limits 3.3V ±10% Limits 5.0V ±10% Symbol Parameter CLK External clock low / high time OSC UART crystal or external clock frequency TAS Address setup time (16 Mode) 5 0 ns TAH Address hold time (16 Mode) 5 5 ns TCS Chip select width (16 Mode) 80 50 ns TRD IOR# strobe width (16 Mode) 80 50 ns TDY Read cycle delay (16 Mode) 40 30 ns TRDV Data access time (16 Mode) 40 25 ns TDD Data disable time (16 Mode) 25 15 ns TWR IOW# strobe width (16 Mode) 35 25 ns TDY Write cycle delay (16 Mode) 40 30 ns TDS Data setup time (16 Mode) 20 15 ns TDH Data hold time (16 Mode) 5 5 ns TADS Address setup (68 Mode) 10 10 ns TADH Address hold (68 Mode) 15 15 ns TRWS R/W# setup to CS# (68 Mode) 10 10 ns TRDA Data access time (68 mode) 40 25 ns TRDH Data disable time (68 mode) 25 15 ns TWDS Write data setup (68 mode) 20 15 ns TWDH Write data hold (68 Mode) 10 10 ns TRWH CS# de-asserted to R/W# de-asserted (68 Mode) 10 10 ns TCSL CS# strobe width (68 Mode) 80 50 ns TCSD CS# cycle delay (68 Mode) 40 30 ns TWDO Delay from IOW# to output 50 40 ns TMOD Delay to set interrupt from MODEM input 40 35 ns TRSI Delay to reset interrupt from IOR# 40 35 ns TSSI Delay from stop to set interrupt 1 1 Bclk TRRI Delay from IOR# to reset interrupt 45 40 ns TSI Delay from start to interrupt 45 40 ns TINT Delay from initial INT reset to transmit start 24 Bclk TWRI Delay from IOW# to reset interrupt 45 40 ns TSSR Delay from stop to set RXRDY# 1 1 Bclk TRR Delay from IOR# to reset RXRDY# 45 40 ns TWT Delay from IOW# to set TXRDY# 45 40 ns 9/4/19 Minimum Maximum Minimum 63 21 8 8 Rev 4.0.2 Maximum 24 ns 24 8 Units MHz 23 ST16C554 / ST16C554D / ST68C554 2.97V to 5.5V Quad UART with 16-Byte FIFO Data Sheet Electrical Characteristics Table 20: AC Electrical Characteristics Limits 3.3V ±10% Symbol Parameter TSRT Delay from center of start to reset TXRDY# TRST Reset pulse width 40 N Baud rate divisor 1 Bclk Baud clock Minimum Limits 5.0V ±10% Maximum Minimum Maximum 8 Units 8 Bclk 40 216-1 1 ns 216-1 - 16X of data rate Hz CLK CLK EXTERNAL CLOCK OSC Figure 14: Clock Timing IO W # IO W A c tiv e TW DO RTS# DTR# C h a n g e o f s ta te C h a n g e o f s ta te CD# CTS# DSR# C h a n g e o f s ta te C h a n g e o f s ta te TMOD T MOD IN T A c tiv e A c tiv e A c tiv e T RSI IO R # A c tiv e A c tiv e A c tiv e TMOD C h a n g e o f s ta te R I# Figure 15: Modem Input and Output Timing for Channels A - D 9/4/19 Rev 4.0.2 24 ST16C554 / ST16C554D / ST68C554 2.97V to 5.5V Quad UART with 16-Byte FIFO Data Sheet Electrical Characteristics A0-A7 Valid Address TAS TCS Valid Address TAS TAH TAH TCS CS# TDY TRD TRD IOR# TDD TRDV D0-D7 TDD TRDV Valid Data Valid Data RDTm Figure 16: 16 Mode (Intel) Data Bus Read Timing for Channels A - D A0-A7 Valid Address T AS TCS Valid Address T AS T AH T CS TAH CS# T DY TWR T WR IOW# T DS D0-D7 TDH Valid Data TDS TDH Valid Data 16Write Figure 17: 16 Mode (Intel) Data Bus Write Timing for Channels A - D 9/4/19 Rev 4.0.2 25 ST16C554 / ST16C554D / ST68C554 2.97V to 5.5V Quad UART with 16-Byte FIFO Data Sheet Electrical Characteristics A0-A7 Valid Address TADS TCSL Valid Address T ADH CS# T CSD TRWS TRWH R/W# T RDH TRDA D0-D7 Valid Data Valid Data 68Read Figure 18: 68 Mode (Motorola) Data Bus Read Timing for Channels A - D A0-A7 Valid Address TADS TCSL Valid Address TADH CS# TCSD TRWS TRWH R/W# TWDS D0-D7 T WDH Valid Data Valid Data 68Write Figure 19: 68 Mode (Motorola) Data Bus Write Timing for Channels A - D 9/4/19 Rev 4.0.2 26 ST16C554 / ST16C554D / ST68C554 2.97V to 5.5V Quad UART with 16-Byte FIFO Data Sheet Electrical Characteristics RX Start Bit Stop Bit D0:D7 INT RXRDY# D0:D7 D0:D7 TSSR T SSR T SSR 1 Byte in RHR 1 Byte in RHR 1 Byte in RHR T SSR T SSR Active Data Ready Active Data Ready TRR T SSR Active Data Ready TRR TRR IOR# (Reading data out of RHR) RXNFM Figure 20: Receive Ready and Interrupt Timing (Non-FIFO Mode) for Channels A - D TX Start Bit (Unloading) IER[1] enabled Stop Bit D0:D7 D0:D7 ISR is read D0:D7 ISR is read ISR is read INT* TWRI TWRI TWRI TSRT TSRT TSRT TXRDY# TWT TWT TWT IOW# (Loading data into THR) *INT is cleared when the ISR is read or when data is loaded into the THR. TXNonFIFO Figure 21: Transmit Ready and Interrupt Timing (Non-FIFO Mode) for Channels A - D 9/4/19 Rev 4.0.2 27 ST16C554 / ST16C554D / ST68C554 2.97V to 5.5V Quad UART with 16-Byte FIFO Data Sheet Electrical Characteristics Start Bit RX S D0:D7 S D0:D7 T D0:D7 Stop Bit S D0:D7 T S D0:D7 T S D0:D7 T S D0:D7 T RX FIFO drops below RX Trigger Level TSSI INT FIFO Empties TSSR RX FIFO fills up to RX Trigger Level or RX Data Timeout RXRDY# First Byte is Received in RX FIFO TRRI TRR IOR# (Reading data out of RX FIFO) RXINTDMA# Figure 22: Receive Ready and Interrupt Timing (FIFO Mode, DMA Disabled) for Channels A - D Start Bit RX Stop Bit S D0:D7 S D0:D7 T D0:D7 S D0:D7 T S D0:D7 T S D0:D7 T S D0:D7 T RX FIFO drops below RX Trigger Level TSSI INT RX FIFO fills up to RX Trigger Level or RX Data Timeout FIFO Empties TSSR RXRDY# TRRI TRR IOR# (Reading data out of RX FIFO) RXFIFODMA Figure 23: Receive Ready and Interrupt Timing (FIFO Mode, DMA Enabled) for Channels A - D 9/4/19 Rev 4.0.2 28 ST16C554 / ST16C554D / ST68C554 2.97V to 5.5V Quad UART with 16-Byte FIFO Data Sheet Electrical Characteristics TX FIFO Empty TX Stop Bit Start Bit S D0:D7 T (Unloading) IER[1] enabled Last Data Byte Transmitted S D0:D7 T S D0:D7 T S D0:D7 T S D0:D7 T T S D0:D7 T ISR is read ISR is read T SI INT* TX FIFO Empty T WRI Data in TX FIFO TXRDY# TWT IOW# (Loading data into FIFO) *INT is cleared when the ISR is read or when at least 1 byte is written to the TX FIFO. Figure 24: Transmit Ready and Interrupt Timing (FIFO Mode, DMA Disabled) for Channels A - D TX FIFO Empty TX Stop Bit Start Bit S D0:D7 T (Unloading) IER[1] enabled Last Data Byte Transmitted S D0:D7 T S D0:D7 T S D0:D7 T S D0:D7 T T S D0:D7 T ISR is read ISR is read T SI T SRT INT* TWRI TXRDY# At least 1 empty location in FIFO TX FIFO Full TWT IOW# (Loading data into FIFO) *INT is cleared when the ISR is read or when at least 1 byte is written to the TX FIFO. Figure 25: Transmit Ready and Interrupt Timing (FIFO Mode, DMA Enabled) for Channels A - D 9/4/19 Rev 4.0.2 29 ST16C554 / ST16C554D / ST68C554 2.97V to 5.5V Quad UART with 16-Byte FIFO Data Sheet Mechanical Dimensions 7.0 Mechanical Dimensions 7.1 LQFP64 TOP VIEW DETAIL A SIDE VIEW TERMINAL DIMENSION TYPICAL RECOMMENDED LAND PATTERN 1. Control dimensions are in Millimeters 2. Dimensions and tolerance per Jedec MS-026 Drawing No. : POD - 00000092 Revision: A Figure 26: Mechanical Dimension, LQFP64 (10 x 10 x 1.4mm Low-Profile Quad Flat Pack) 9/4/19 Rev 4.0.2 30 ST16C554 / ST16C554D / ST68C554 2.97V to 5.5V Quad UART with 16-Byte FIFO Data Sheet PLCC68 7.2 PLCC68 D 45º x H D1 A3 1 68 9 61 10 60 E3 E E1 Pin 1 I.D. Mark 44 26 27 43 TOP VIEW A1 A SIDE VIEW SEATING PLANE D3 R SIDE VIEW TERMINAL DETAILS Drawing No.: POD-000000 145 Revision: A Figure 27: Mechanical Dimensions, PLCC68 (Plastic Leaded Chip Carrier) 9/4/19 Rev 4.0.2 31 ST16C554 / ST16C554D / ST68C554 2.97V to 5.5V Quad UART with 16-Byte FIFO Data Sheet Ordering Information 8.0 Ordering Information Table 21: Ordering Information(1) Operating Temperature Range Package Packaging Method Lead-Free(2) 0°C to 70°C LQFP64 Tray Yes ST16C554DCQ64-F 0°C to 70°C LQFP64 Tray Yes ST16C554DIQ64-F –40°C to +85°C LQFP64 Tray Yes ST16C554DIQ64TR-F –40°C to +85°C LQFP64 Reel Yes ST16C554DCJ68-F 0°C to 70°C PLCC68 Tube Yes ST16C554DCJ68TR-F 0°C to 70°C PLCC68 Reel Yes ST16C554DIJ68-F –40°C to +85°C PLCC68 Tube Yes ST16C554DIJ68TR-F –40°C to +85°C PLCC68 Reel Yes –40°C to +85°C PLCC68 Tube Yes Ordering Part Number ST16C554 ST16C554CQ64-F ST16C554D ST68C554 ST68C554IJ68-F 1. Refer to www.maxlinear.com/ST16C554, www.maxlinear.com/ST16C554D, and www.maxlinear.com/ST68C554 for most up-to-date Ordering Information. 2. Visit www.maxlinear.com for additional information on Environmental Rating. 9/4/19 Rev 4.0.2 32 ST16C554 / ST16C554D / ST68C554 2.97V to 5.5V Quad UART with 16-Byte FIFO Data Sheet Disclaimer MaxLinear, Inc. 5966 La Place Court, Suite 100 Carlsbad, CA 92008 760.692.0711 p. 760.444.8598 f. www.maxlinear.com The content of this document is furnished for informational use only, is subject to change without notice, and should not be construed as a commitment by MaxLinear, Inc. MaxLinear, Inc. assumes no responsibility or liability for any errors or inaccuracies that may appear in the informational content contained in this guide. Complying with all applicable copyright laws is the responsibility of the user. Without limiting the rights under copyright, no part of this document may be reproduced into, stored in, or introduced into a retrieval system, or transmitted in any form or by any means (electronic, mechanical, photocopying, recording, or otherwise), or for any purpose, without the express written permission of MaxLinear, Inc. Maxlinear, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless MaxLinear, Inc. receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of MaxLinear, Inc. is adequately protected under the circumstances. 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