XR10910
16:1 Sensor Interface AFE
FE ATU R E S
■■ Integrated features for interfacing multiple
bridge sensors with an MCU or FPGA:
16:1 differential mux with I2C interface
Instrumentation amplifier
LDO
Offset correction DAC with I2C interface
(±560mV offset correction range - RTI)
■■ Eight selectable voltage gains from 2V/V
to 760V/V with only ±0.5% gain error
■■ 1mV maximum input offset voltage
■■ 100pA maximum input bias current
■■ 556μA maximum supply current
■■ 2.7V to 5V analog supply voltage range
■■ 1.8V to 5V digital supply voltage range
■■ -40˚C to +85˚C temperature range
■■ 6mm x 6mm QFN-40 package
General Description
The XR10910 is a unique sensor interface integrated circuit with an on-board
16:1 multiplexer, offset correction DAC, instrumentation amplifier and voltage
reference. The XR10910 is designed to integrate multiple bridge sensors
with a microcontroller (MCU) or field-programmable gate array (FPGA).
The integrated offset correction DAC provides digital calibration of the
variable and in many cases substantial offset voltage generated by the
bridge sensors. The DAC is controlled by an I2C compatible 2 wire serial
interface. The serial interface also provides the user with easy controls to the
XR10910’s many functions such as input and gain selection.
An integrated LDO provides a regulated voltage to power the input bridge
sensors and is selectable, between 3V and 2.65V, via the serial interface
for lower voltage compatibility. The LDO current can be sensed and a
proportional voltage present at the output of the IC for monitoring the LDO
current.
The XR10910 offers 8 fixed gain settings (from 2V/V to 760V/V), each with
an error of only ±0.5%, that are selectable via the I2C interface. It also offers
less than 1mV maximum input offset voltage, 100pA maximum input bias
current, and 100pA maximum input offset current.
A P P LICATION S
■■ Bridge sensor interface
■■ Pressure & temperature sensors
■■ Strain gauge amplifier
■■ Industrial process controls
■■ Weigh scales
The XR10910 is designed to operate from 2.7V to 5V supplies and is specified
over the industrial temperature range of -40°C to +85°C. It is offered in a
space saving 6mm x 6mm QFN-40 package. It consumes less than 556μA
maximum supply current and offers a sleep mode for added power savings.
Ordering Information - back page
The low power, low input bias current and integrated features make the
XR10910 well suited for both industrial and consumer applications using
bridge sensors.
Typical Application
VDD
VCC
6.8μF
6.8μF
0.1μF
0.1μF
+
+
BRDG
VCC
2.5
2
VDD
0.1μF
BRIDGE 16
1.5
LDO
1
IN16-
INA /
PGA
16:1
MUX
BRIDGE 1
10k
ADC
µC
10nF
±560mV
OFFSET TRIM
10-BIT
DAC
IN1+
IN1-
OUT
VDD
PGA
4.7k
VDD
RTI Noise (µV)
IN16+
0.5
0
-0.5
-1
4.7k
-1.5
SDA
I2C
CONTROL
-2
SCL
-2.5
0
AGND
2
4
6
8
10
Time (sec)
XR10910
DGND
Figure 1. Typical Application
Figure 2. 0.1Hz to 10Hz RTI Voltage Noise
REV 1E
1/22
XR10910
Absolute Maximum Ratings
Operating Conditions
Stresses beyond the limits listed below may cause
permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect
device reliability and lifetime.
Analog Supply Voltage Range................................... 2.7V to 5.25V
Digital Supply Voltage Range.....................................1.7V to 5.25V
Operating Temperature Range..................................-40°C to 85°C
Junction Temperature............................................................ 150°C
Storage Temperature Range....................................-65°C to 150°C
Analog Supply Voltage (VCC).......................................... 0V to 5.5V
Digital Supply Voltage (VDD)........................................... 0V to 5.5V
Digital Input/Output (VDDIO)............................................ 0V to 5.5V
VIN......................................................................................0 to VCC
Differential Input Voltage (current limit of 10mA)....................... VCC
Lead Temperature (Soldering, 10s).......................................260°C
Package thermal resistance θJA......................................... 32°C/W
NOTE:
1. JEDEC standard, multi-layer test boards, still air.
ESD Rating (HBM - Human Body Model)..................................4kV
REV 1E
2/22
XR10910
Electrical Characteristics
TA = 25°C, VCC = 3.3V, VDD = 1.8V, RL = 10kΩ to 1.5V; G = 760; unless otherwise noted.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
-1
±0.02
1
mV
DC Performance
VIO
Input offset voltage
dVIO
Input offset voltage average drift
IB
Input bias current
-100
15
100
pA
IOS
Input offset current
-100
1
100
pA
PSRR
Power supply rejection ratio
60
91
dB
Gain = 2
2.0
V/V
Gain = 20
20.0
V/V
Gain = 40
40.0
V/V
Gain
GE
Gain = 80
Input referred
3
VCC = 2.7V to 5V
μV/°C
80.0
V/V
150.0
V/V
Gain = 300
299.9
V/V
Gain = 600
599.6
V/V
Gain = 760
759.4
V/V
Gain = 150
Nominal; refer to Gain Register Table (pg. 10)
Gain error
-0.5
Gain error vs temperature
0.5
±10
ISVCC
VCC supply current
No load to output; no load to LDO
ISVCCD
Disable VCC supply current
No load to output; no load to LDO
2
%
ppm/°C
435
530
μA
48
59
μA
ISVDD
VDD supply current
No load to output; no load to LDO; I C running
22
26
μA
ISTOTAL
Total supply current
No load to output; no load to LDO
457
556
μA
ISDTOTAL
Total disable supply current
No load to output; no load to LDO; LDO DIS
45
No load to output; no load to LDO; LDO EN
70
μA
85
μA
Input Characteristics
Input impedance
CMIR
Common mode input range
CMRR
Common mode rejection ratio
Ω || pF
1013 || 11.2
0.5
0.23 to
3.06
Input referred. VCM = 0.5 to 2.0V
75
88
2.5
V
dB
Output Characteristics
VOUT
Output voltage swing
RL = 10kΩ to 1.5V
0.1
0.04 to
3.29
3.1
V
VOO
Output offset
Offset DAC 0 00 0000 0000; G = 2
1.4
1.5
1.6
V
Offset DAC range
RTI (referred to input)
Offset DAC
Offset monotonicity
±560
8
mV
10
Bits
LDO
Output voltage
Dropout voltage
1.5k load, LDO bit LOW
-6%
3
+6%
V
1.5k load, LDO bit HIGH
-6%
2.65
+6%
V
150
mV
VCC = 2.8V, LDO = 2.65V, ILOAD = 10mA
Output current
10
25
mA
Output referred, VCC = 3V to 5V, LDO = 2.65V
45
63
dB
Output referred, VCC = 3.3V to5V, LDO = 3V
45
63
dB
Output current sense transimpedance
slope
Output voltage relative to 1.5V / LDO current,
G=2
0.08
0.1
Output current sense range clip
G=2
Power supply rejection ratio
18.8
REV 1E
0.12
V/mA
mA
3/22
XR10910
Electrical Characteristics (Continued)
TA = 25°C, VCC = 3.3V, VDD = 1.8V, RL = 10kΩ to 1.5V; G = 760; unless otherwise noted.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Dynamic Performance
BW
-3dB bandwidth
SR
Slew rate
G = 760
G=2
66
kHz
1300
kHz
VOUT = 1Vpp; Gain = 2
1
V/μs
f = 10Hz
75
nV/√Hz
f = 100Hz
46
nV/√Hz
eni
Input voltage noise - RTI
f = 1kHz
35
nV/√Hz
in
Input current noise
f = 10Hz
0.6
fA/√Hz
enpp
Peak-to-peak noise
f = 0.1 to 10Hz
2
μVpp
XTALK
Crosstalk
Channel-to-channel, f = 1kHz
90
dB
TS
Set-up time, 1% settling
Analog ready after serial register finished write
3.5
μs
TWAKE
Wake up time, 1% settling
Wake from ACK of SLEEP_OUT command
9.6
μs
Digital Characteristics (CMOS)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
VIH
Logic Input HIGH
0.7 x VDD
VDD
V
VIL
Logic Input LOW
0
0.3 x VDD
V
IIH
Input Leakage HIGH
VI = VS
10
μA
IIL
Input Leakage LOW
VI = 0
CLKF
Clock Rate
-10
μA
0.4
MHz
I2C Bus Timing
TA = -40 to +85°C, VDD = 1.8 - 5V; unless otherwise noted.
Symbol
Parameter
Standard Mode
I2C-BUS
Min
Max
0
100
Fast Mode
I2C-BUS
Min
Max
0
400
Units
fSCL
Operating frequency
TBUF
Bus free time between STOP and START
4.7
1.3
μs
THD;STA
START condition hold time
4.0
0.6
μs
TSU;STA
START condition setup time
4.7
0.6
μs
THD;DAT
Data hold time
0
0
μs
TVD;ACK
Data valid acknowledge
0.6
0.6
μs
TVD;DAT
SCL LOW to data out valid
0.6
0.6
ns
TSU;DAT
Data setup time
250
150
ns
TLOW
Clock LOW period
4.7
1.3
μs
THIGH
Clock HIGH period
4.0
0.6
μs
TF
Clock/data fall time
300
300
ns
TR
Clock/data rise time
1000
300
ns
TSP
Pulse width of spikes tolerance
0.5
REV 1E
0.5
kHz
μs
4/22
XR10910
Electrical Characteristics (Continued)
Figure 3: I2C Bus Timing Diagram
REV 1E
5/22
XR10910
Register Information
Table 1. Register List
Reg No.
Name
Function
R/
W/
C
Byte of
Parameter
Parameter
Default
Code
Power-up
Condition
Remark
Hex
Dec
0x00
0
NOP
No operation
C
0
N/A
Does not execute a function. NOP
is used to test successful I2C
communication
1
SW_RESET
Software reset
C
0
N/A
Resets all registers to default values
Reset
0x01
Read ID
0x02
2
DEVICE_ID
Read Device ID
R
2
[15:0]: report “0910” in
BCD
0x03
3
VERSION_ID
Read HW & SW
version numbers
R
2
[15:12]: reserved
[11:8]: Hardware version #
[7:0]: Software version #
SLEEP_OUT
_ REG
Normal operating
mode, system
active
C
0
Instructs the XR10910 to report its
device ID “0910” in binary form
(0000 1001 0001 0000)
0x0910
N/A
Initial H/W version number is ‘0’;
Initial S/W version number is ‘01’.
Sleep in/out
0x04
0x05
4
5
SLEEP_IN_
REG
Sleep Mode
C
0
Active
Puts the XR10190 into active mode.
(wake up)
N/A
Active
Puts the analog portion of the XR10910
into sleep mode.
During sleep mode, the only I2C command
that can be received/processed is the
SLEEP_OUT command (0x04). All other
register addresses will be ignored.
N/A
Basic Config
0x06
6
Gain
Gain select
R/W
1
[2:0]: Gain select
0x00
Gain
=2
0x07
7
LDO
LDO Settings
R/W
1
[0]:LDO 3V, 2.65V
[1]:LDO disable
0x00
LDO
= 3V
0x08
8
LDO Current
Sense Select
LDO Current Sense
C
0
N/A
REV 1E
Off
Eight gain settings are selectable (from
2V/V to 760V/V), refer to the Gain Register
Table for more information.
Bit 0 controls the LDO voltage (0: 3V;
1: 2.65V).
Bit 1 (Sleep Mode only). Bit 1 controls
whether the LDO shuts down or stays on
during Sleep Mode. (0: Enable; 1: Disable).
When the XR10910 is active, the LDO is
always on.
When on, the LDO current is sensed and
a proportional voltage is present at the
output of the XR10910.
Current Sense Mode remains active until
an input select command is received by
the XR10910.
6/22
XR10910
Reg No.
Hex
Dec
Name
Function
R/
W/
C
Byte of
Parameter
Parameter
Default
Code
Power-up
Condition
Remark
Channel Switch (Input Mux Select)
0x10 16
Select_
Input_1
Select Channel 1
C
0
Select +IN1, -IN1; Channel 1
0x11 17
Select_
Input_2
Select Channel 2
C
0
Select +IN2, -IN2; Channel 2
0x12 18
Select_
Input_3
Select Channel 3
C
0
Select +IN3, -IN3; Channel 3
0x13 19
Select_
Input_4
Select Channel 4
C
0
Select +IN4, -IN4; Channel 4
0x14 20
Select_
Input_5
Select Channel 5
C
0
Select +IN5, -IN5; Channel 5
0x15 21
Select_
Input_6
Select Channel 6
C
0
Select +IN6, -IN6; Channel 6
0x16 22
Select_
Input_7
Select Channel 7
C
0
Select +IN7, -IN7; Channel 7
0x17 23
Select_
Input_8
Select Channel 8
C
0
0x18 24
Select_
Input_9
Select Channel 9
C
0
0x19 25
Select_
Input_10
Select Channel 10
C
0
Select +IN10, -IN10; Channel 10
0x1A 26
Select_
Input_11
Select Channel 11
C
0
Select +IN11, -IN11; Channel 11
0x1B 27
Select_
Input_12
Select Channel 12
C
0
Select +IN12, -IN12; Channel 12
0x1C 28
Select_
Input_13
Select Channel 13
C
0
Select +IN13, -IN13; Channel 13
0x1D 29
Select_
Input_14
Select Channel 14
C
0
Select +IN14, -IN14; Channel 14
0x1E 30
Select_
Input_15
Select Channel 15
C
0
Select +IN15, -IN15; Channel 15
0x1F 31
Select_
Input_16
Select Channel 16
C
0
Select +IN16, -IN16; Channel 16
N/A
REV 1E
Channel
1 is
selected
Select +IN8, -IN8; Channel 8
Select +IN9, -IN9; Channel 9
7/22
XR10910
Reg No.
Hex
Dec
Name
Function
R/
W/
C
Byte of
Parameter
Parameter
Default
Code
Power-up
Condition
Remark
Offset DAC Config
0x20 32
DAC1
Configures DAC
offset applied to
Channel 1
R/W
2
0x21 33
DAC2
Configures DAC
offset applied to
Channel 2
R/W
2
0x22 34
DAC3
Configures DAC
offset applied to
Channel 3
R/W
2
0x23 35
DAC4
Configures DAC
offset applied to
Channel 4
R/W
2
0x24 36
DAC5
Configures DAC
offset applied to
Channel 5
R/W
2
0x25 37
DAC6
Configures DAC
offset applied to
Channel 6
R/W
2
0x26 38
DAC7
Configures DAC
offset applied to
Channel 7
R/W
2
0x27 39
DAC8
Configures DAC
offset applied to
Channel 8
R/W
2
R/W
2
[10]: DAC Sign
[9:0]: DAC Range
0x28 40
DAC9
Configures DAC
offset applied to
Channel 9
0x29 41
DAC10
Configures DAC
offset applied to
Channel 10
R/W
2
0x2A 42
DAC11
Configures DAC
offset applied to
Channel 11
R/W
2
0x2B 43
DAC12
Configures DAC
offset applied to
Channel 12
R/W
2
0x2C 44
DAC13
Configures DAC
offset applied to
Channel 13
R/W
2
0x2D 45
DAC14
Configures DAC
offset applied to
Channel 14
R/W
2
0x2E 46
DAC15
Configures DAC
offset applied to
Channel 15
R/W
2
0x2F 47
DAC16
Configures DAC
offset applied to
Channel 16
R/W
2
0x00
0mV
offset
Bit 10 controls the sign of the DAC offset
voltage. Bits 9 thru 0 control the value of
the DAC offset voltage.
[10]: DAC Sign 0 = positive; 1 = negative
NOTE:
Register Numbers not listed above have no function.
REV 1E
8/22
XR10910
Table 2. DAC Registers
Hex
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Offset % of FS Input
Voltage RTI
0x3FF
0
1
1
1
1
1
1
1
1
1
1
50
+560mV
0x000
0
0
0
0
0
0
0
0
0
0
0
0
0
0x7FF
1
1
1
1
1
1
1
1
1
1
1
-50
-560mV
0x400
1
0
0
0
0
0
0
0
0
0
0
0
0
DAC
Sign
10-bit DAC Range
Table 3: Gain Registers
Hex
D2
D1
D0
Gain
0x00
0
0
0
2
0x01
0
0
1
20
0x02
0
1
0
40
0x03
0
1
1
80
0x04
1
0
0
150
0x05
1
0
1
300
0x06
1
1
0
600
0x07
1
1
1
760
REV 1E
9/22
XR10910
VDD
SDA
SCL
DGND
VCC
OUT
AGND
BRDG
IN16-
IN16+
40
39
38
37
36
35
34
33
32
31
Pin Configuration
IN1+
1
30
IN15-
IN1-
2
29
IN15+
IN2+
3
28
IN14-
IN2-
4
27
IN14+
IN3+
5
26
IN13-
IN3-
6
25
IN13+
IN4+
7
24
IN12-
IN4-
8
23
IN12+
IN5+
9
22
IN11-
IN5-
10
21
IN11+
19
20
IN10-
16
IN8-
IN10+
15
IN8+
18
14
IN7-
IN9-
13
IN7+
17
12
IN6-
IN9+
11
QFN-40
IN6+
NOTE:
XR10910
MaxLinear recommends grounding the exposed pad.
Pin Functions
Pin No.
Pin Name
Description
Pin No.
Pin Name
Description
1
IN1+
Positive Input 1
21
IN11+
Positive Input 11
2
IN1-
Negative Input 1
22
IN11-
Negative Input 11
3
IN2+
Positive Input 2
23
IN12+
Positive Input 12
4
IN2-
Negative Input 2
24
IN12-
Negative Input 12
5
IN3+
Positive Input 3
25
IN13+
Positive Input 13
6
IN3-
Negative Input 3
26
IN13-
Negative Input 13
7
IN4+
Positive Input 4
27
IN14+
Positive Input 14
8
IN4-
Negative Input 4
28
IN14-
Negative Input 14
9
IN5+
Positive Input 5
29
IN15+
Positive Input 15
10
IN5-
Negative Input 5
30
IN15-
Negative Input 15
11
IN6+
Positive Input 6
31
IN16+
Positive Input 16
12
IN6-
Negative Input 6
32
IN16-
Negative Input 16
13
IN7+
Positive Input 7
33
BRDG
BRDG Power Connection ( LDO output )
14
IN7-
Negative Input 7
34
AGND
Analog Ground
15
IN8+
Positive Input 8
35
OUT
Output
16
IN8-
Negative Input 8
36
VCC
Analog Supply
17
IN9+
Positive Input 9
37
DGND
Digital Ground
18
IN9-
Negative Input 9
38
SCL
Serial Clock Input
19
IN10+
Positive Input 10
39
SDA
Serial Data Input/Output
20
IN10-
Negative Input 10
40
VDD
Digital Supply
REV 1E
10/22
XR10910
Typical Performance Characteristics
TA = 25°C, VCC = 3.3V, VDD = 1.8V, RL = 10kΩ to 1.5V; G = 760; unless otherwise noted.
2
G = 2, Vout = 0.5Vpp
2.5
Output Voltage (V)
1.75
Output Voltage (V)
G = 2, Vout = 2.5Vpp
3
1.5
2
1.5
1
1.25
0.5
0
1
0
5
10
15
20
25
30
35
0
40
5
10
15
20
25
30
35
40
Time (µs)
Time (µs)
Figure 4. Small Signal Pulse Response at G = 2
Figure 5. Large Signal Pulse Response at G = 2
2
G = 300, Vout = 0.5Vpp
2.5
Output Voltage (V)
1.75
Output Voltage (V)
G = 300, Vout = 2.5Vpp
3
1.5
2
1.5
1
1.25
0.5
0
1
0
20
40
60
80
0
100
20
40
60
Figure 6. Small Signal Pulse Response at G = 300
100
Figure 7. Large Signal Pulse Response at G = 300
3
3
G=2
G = 300
0
0
-3
Normalized Gain (dB)
Normalized Gain (dB)
80
Time (µs)
Time (µs)
VOUT = 0.5Vpp
VOUT = 1Vpp
-6
VOUT = 2.5Vpp
-9
-3
VOUT = 0.5Vpp
VOUT = 1Vpp
-6
VOUT = 2.5Vpp
-9
-12
0.1
1
10
100
1000
-12
10000
0.1
Frequency (kHz)
1
10
100
1000
10000
Frequency (kHz)
Figure 8. Frequency Response at G = 2
Figure 9. Frequency Response at G = 300
REV 1E
11/22
XR10910
Typical Performance Characteristics
TA = 25°C, VCC = 3.3V, VDD = 1.8V, RL = 10kΩ to 1.5V; G = 760; unless otherwise noted.
3.5
4
G=2
3.5
Current Sense Mode Active
VCC = 5V
3
VLDO (V)
Output Voltage (V)
3
2.5
2
2.5
2
VCC = 3.3V
1.5
1
0.5
1.5
0
0
5
10
15
20
25
0
10
20
ILDO (mA)
Figure 10. LDO Current vs. Output Voltage
40
50
Figure 11. LDO Output Current
5
1.55
G=2
1.53
4
G=2
1.51
Output Voltage (V)
Output Voltage (V)
30
ILDO (mA)
3
2
1
1.49
G = 300
1.47
1.45
1.43
G = 760
1.41
1.39
0
1.37
1.35
0.25
-1
-10
-5
0
5
10
0.75
Figure 12. Output Offset Voltage vs. Output Current
1.75
2.25
2.75
Figure 13. Output Offset vs. Input Common Mode Voltage
100
2.5
90
G = 760
2
80
1.5
70
1
RTI Noise (µV)
Input Voltage Noise (nV/√Hz)
1.25
Input Common Mode Voltage (V)
Output Current (mA)
60
50
40
0.5
0
-0.5
30
-1
20
-1.5
10
-2
0
0.01
0.1
1
10
100
-2.5
1000
0
Frequency (KHz)
2
4
6
8
10
Time (sec)
Figure 14. Input Voltage Noise vs. Frequency
Figure 15. 0.1Hz to 10Hz RTI Voltage Noise
REV 1E
12/22
XR10910
Typical Performance Characteristics
TA = 25°C, VCC = 3.3V, VDD = 1.8V, RL = 10kΩ to 1.5V; G = 760; unless otherwise noted.
2.5
4
G=2
Stop Time = 1% Settling
3.5
2
Output Voltage (V)
Output Voltage (V)
3
1.5
DUT OUTPUT
1
SDA
0.5
2
DUT OUTPUT
1.5
1
0
Stop Time = 1% Settling
SDA
2.5
Start Time = 50% Acknowledge
0.5
Start Time = 50% Acknowledge
-0.5
0
0
5
10
15
20
0
5
10
Time (µs)
Figure 16. Sleep to Wake Time (DUT Output)
3.5
3.5
3
2.5
SDA
Output Voltage (V)
Output Voltage (V)
3
2.5
2
LDO Output
1
LDO OUTPUT
Stop Time = 1% Settling
2
1.5
1
SDA
0.5
Stop Time = 1% Settling
0.5
20
Figure 17. Set-up Time - from G = 2 to G = 300
(DUT Output)
4
1.5
15
Time (µs)
0
0
Start Time = 50% Acknowledge
Start Time = 50% Acknowledge
-0.5
-0.5
0
50
100
150
200
250
0
Time (µs)
10
20
30
40
50
Time (µs)
Figure 18. LDO Enable to Disable Time
Figure 19. LDO Disable to Enable Time
REV 1E
13/22
XR10910
Functional Block Diagram
VCC
LDO Output
1.5V
Reference
LDO Enable
LDO Select ( 3V, 2.65V )
AGnd
Input 1 +/Input 2 +/Input 3 +/2:1 Differential Mux
Output
SDA
SCL
Power Down Analog
Gain Select
DAC [0:9], Sign
Current Sense Mode
Input [0:15]
VDD
10 bit Offset DAC
LDO Select
Offset +
Input 15 +/Input 16 +/-
Offset -
Input 14 +/-
LDO Enable
16:1 Differential Mux
Input 4 +/-
PGA
I2C Serial Digital Interface
DGnd
Figure 20: Functional Block Diagram
Application Information
The XR10910 sensor interface includes a 16:1 differential
multiplexor (mux), a programmable gain instrumentation
amplifier, a 10-bit offset correction DAC and an LDO. An
I2C interface controls the many functions and features of the
XR10910. The XR10910 is designed to integrate multiple
bridge sensors with an ADC/MCU or FPGA.
The XR10910 also provides the ability to monitor the LDO
current. When the XR10910 is in Current Sense Mode, an
internal 2:1 mux allows a voltage proportional to the LDO
current to be present at the output. Once all channels have
been calibrated, the LDO current can be used to indirectly
monitor any voltage or resistive changes seen by the inputs.
Each bridge sensor connected to the XR10910 has its
own inherent offset that if not calibrated out can decrease
sensitivity and overall performance of the sensor system. The
on-board DAC introduces an offset into the instrumentation
amplifier to calibrate the offset voltage generated by the
sensors. An independent offset can be set for each of the
16 channels. Only the offset voltage of the active channel is
applied to the PGA.
The XR10910 also includes an internal 1.5V reference that
is used by the internal LDO circuitry and used to set the
reference voltage for the programmable gain instrumentation
amplifier.
The programmable gain instrumentation amplifier offers 8
selectable gains from 2V/V to 760V/V to amplify the signal
such that it falls within the input range of the ADC.
During sleep mode, the analog components of the XR10910
are powered down for added power savings.
The XR10910 offers many functions, each controlled by the
I2C compatible serial interface:
An integrated LDO provides a regulated voltage to power
the input bridge sensors and is selectable, between 3V and
2.65V. The LDO can be set to turn off when the XR10910 is
in Sleep Mode to save power.
REV 1E
■■
Input Selection
■■
Gain Selection
■■
Offset Correction
■■
LDO Enable / Select
■■
Current Sense Mode
■■
Sleep Mode (Analog Power Down)
14/22
XR10910
Application Information (Continued)
Power Up
After initial system power up, the I2C master must provide
one SCL clock pulse prior to the first I2C access (first start
condition). The first access to the XR10910 must be a
RESET command.
SDA
SCL
Data Cycle
After the master detects this acknowledge, the next byte
transmitted by the master is the sub-address. This 8-bit
sub-address contains the address of the register to access.
The XR10910 Register List is shown in Table 1. Depending
on the register accessed, there will be up to two additional
data bytes transmitted by the master. Refer to the “Byte of
Parameter” column in the Register Table. The XR10910 will
respond to each write with an acknowledge.
Stop Condition
Figure 21: I2C Power Up
To signal the end of the data transfer, the master generates
a stop condition by pulling the SDA line from low to high
while the SCL line is high, as shown in Figure 22.
The I2C-bus interface consists of two lines: serial data (SDA)
and serial clock (SCL). The XR10910 works as a slave and
supports both standard mode transfer rates (100 kbps) and
fast mode transfer rates (400 kbps) as defined in the I2CBus specification. The I2C-bus interface follows all standard
I2C protocols. Some information is provided below, for
additional information, refer to the I2C-bus specifications.
Figures 23 and 24 illustrate a write and a read cycle. For
complete details, see the I2C-bus specifications.
I2C Bus Interface
SLAVE
ADDRESS
S
W
A
REGISTER
ADDRESS
A
nDATA
A
P
NOTES:
White Block = host to XR10910, Red Block = XR10910 to host
Figure 23: Master Writes to Slave (XR10910)
SLAVE
REGISTER
SLAVE
LAST
S ADDRESS W A ADDRESS A S ADDRESS R A nDATA A DATA NA P
NOTES:
White Block = host to XR10910, Red Block = XR10910 to host
Figure 22: I2C Start and Stop Conditions
Figure 24: Master Reads from Slave (XR10910)
2
I C Bus Addressing
2
The basic I C access cycle for the XR10910 consists of:
■■
A start condition
■■
A slave address cycle
■■
■■
The XR10910 uses a 7-bit address space. For the standard
XR10910, the default address is 0x67 (110 0111).
Zero, one, or two data cycles - depending on the XR10910
register accessed
Table 4: XR10910 I2C Address Map
A stop condition
Start Condition
The master initiates data transfer by generating a start
condition. The start condition is when a high-to-low transition
occurs on the SDA line while SCL is high, as shown in
Figure 22.
Slave Address Cycle
After the start condition, the first byte sent by the master
is the 7-bit address and the read/write direction bit R/W
on the SDA line. If the address matches the XR10910’s
internal fixed address, the XR10910 will respond with an
acknowledge by pulling the SDA line low for one clock cycle
while SCL is high.
I2C Address
Orderable Part Number
0x67
XR10910IL40TR-F
A read or write transaction is determined by bit-0 of the
slave address, (shown as an “x” in Table 4 above). If bit-0 is
’0’, then it is a write transaction. If bit-0 is ’1’, then it is a read
transaction.
An I2C sub-address is sent by the I2C master following
the slave address. The sub-address contains the XR10910
register address being accessed. Table 1 illustrates the
available XR10910 register addresses.
After the last read or write transaction, the I2C-bus master
will set the SCL signal back to its idle state (HIGH).
REV 1E
15/22
XR10910
Application Information (Continued)
Inputs and Input Selection
Gain Selection
The XR10910 includes 16 differential inputs and a 16:1
differential mux that is controlled by an I2C compatible 2
wire serial interface. The XR10910 is designed to accept 16
differential inputs.
The XR10910 offers 8 selectable fixed gains ranging from
2V/V to 760V/V. When the XR10910 is powered-up, the
default gain is 2V/V.
■■
■■
If fewer than 16 differential inputs are required, tie the unused
inputs to GND.
If single ended inputs are required, tie the unused inputs to
1.5V.
The input common mode range of the XR10910 is typically
0.6V to 2.4V when running from a 3.3V supply. The XR10910
offers a very wide gain range. In most cases, the output
voltage swing will be the limiting factor.
When the XR10910 is powered-up, the default input selected
is Channel 1.
The gain is selected via I2C using the register address 0x06
followed by another byte of data to select the gain. Refer
to the Register List in Table 1 and the Gain Register list in
Table 3.
Example: The example below illustrates how to select a
gain of 150V/V.
To start communication with the XR10910, repeat steps 1-3
as shown in the Inputs and Input Selection section on page
16.
Step 4
Master sends address of register to
access
Inputs are selected via I2C using one of 16 register addresses
0x10 thru 0x1F. Refer to the Register List in Table 1.
7
6
5
4
3
2
1
0
0
0
0
0
0
1
1
0
Gain Select
register address = 0x06
Example: The example below illustrates how to select
Channel 5.
Step 1
0
Step 5
9
Master sends start condition
S
XR10910 sends acknowledge
A
Step 2
7
6
5
4
3
2
1
0
Master sends XR10910 address with
write bit
1
1
0
0
1
1
1
0
7-bit XR10910
Address = 0x67
Step 3
9
XR10910 sends acknowledge
A
Step 4
Master sends address of register to
access
W
7
6
5
4
3
2
1
0
0
0
0
1
0
1
0
0
Since the Gain Select register was accessed, the XR10910
is expecting another byte of data from the master to complete
the command. Refer to the “Byte of Parameter” column in
the Register List (Table 1). D0 thru D2 are used to select
the gain. Refer to the Gain Register list in Table 3, 150V/V is
D2 = 1, D1 = 0, and D0 = 0. This translates to a hex code of
0x04, since a full byte of data (8-bits) will be sent.
9
XR10910 sends acknowledge
A
Step 6
0
Master sends stop condition
P
7
6
5
4
3
2
1
0
Master sends gain register data to select
G=150
0
0
0
0
0
1
0
0
Gain of 150V/V = 0x04
Select_Input 5
register address = 0x14
Step 5
Step 6
Step 7
9
XR10910 sends acknowledge
A
Step 8
0
Master sends stop condition
P
White Block = host to XR10910, Red Block = XR10910 to host
Grey Block = Notes
White Block = host to XR10910, Red Block = XR10910 to host
Grey Block = Notes
REV 1E
16/22
XR10910
Application Information (Continued)
Offset Correction
The XR10910 has a 10-bit offset correction DAC that can be
used to provide digital calibration on each of the 16 inputs.
Only the offset voltage of the active channel is applied to
the PGA.
The DAC offset of each channel is controlled by the I2C
compatible interface. At any time, the master can read or
write to any of the DAC offset registers. The DAC offset for
each channel is set via I2C using the register addresses
0x20 thru 0x2F followed by another two bytes of data to
set the polarity and value of the offset voltage. Refer to the
Register List in Table 1.
A ±560mV offset correction range is available. The full
range of the DAC offset is only available at a gain of 2. At
higher gains, the output voltage range of the XR10910 will
be exceeded if the full range of the DAC offset is used. The
internal 10-bit DAC allows 1,024 different offset voltage
settings between 0mV and 560mV. The polarity of the
offset correction is set with an additional bit. The unit offset
is determined by the following:
■■
A
To determine what DAC output level corresponds to 75mV,
use the following equation:
Desired Offse t
DAC Output Level =
Unit Offset
= 75mV = 137
547 nV
A decimal value of 137 corresponds to 75mV. Therefore:
■■
■■
From Table 3:
■■
9
XR10910 sends acknowledge
Since a DAC Offset register was accessed, the XR10910
is expecting another two bytes of data from the master to
complete the command. Refer to the “Byte of Parameter”
column in the Register List (Table 1). D0 thru D9 are used
to set the offset voltage and D10 is used to set the sign of
the offset voltage, 0 = positive and 1 = negative. Refer to the
DAC Offset register list in Table 2.
Total Offset
560mV
Unit offset = DAC output levels = 1024 = 547nV
■■
Step 5
0x00 (hex) or 0 00 0000 0000 (binary) applies a 0mV offset
0x89 (hex) or 0 00 1000 1001 (binary) applies a +75mV
offset
0x489 (hex) or 1 00 1000 1001 (binary) applies a -75mV
offset
Step 6
15 14 13 12 11
10
9
8
Master sends 1st byte
of DAC offset register
data to select an offset
of +75mV
0
0
0
0
0
0
0
0
2 MSBs of 10-bit DAC
0x3FF (hex) or 0 11 1111 1111 (binary) applies a +560mV
offset
Sign output level that corresponds to 137 (0x89)
0x7FF (hex) or 1 11 1111 1111 (binary) applies a -560mV
offset
Each DAC output level provides an additional 547µV of
offset. To determine what DAC output level corresponds to
a specific desired offset, use the following equation:
See example below for additional information.
Step 7
9
XR10910 sends acknowledge
A
Step 8
7
6
5
4
3
2
1
0
Master sends 2nd byte of DAC offset
register data to select an offset of +75mV
1
0
0
0
1
0
0
1
8 LSBs of 10-bit DAC output
level that corresponds to 137
(0x89)
Example: The example below illustrates how to set the DAC
offset for channel 4 to a value of 75mV.
To start communication with the XR10910, repeat steps 1-3
as shown in the Inputs and Input Selection section on page
16.
Step 4
Master sends address of register to
access
7
6
5
4
3
2
1
0
0
0
1
0
0
1
1
0
DAC4 register address
= 0x25
Step 9
9
XR10910 sends acknowledge
A
Step 10
0
Master sends stop condition
P
White Block = host to XR10910, Red Block = XR10910 to host
Grey Block = Notes
REV 1E
17/22
XR10910
Application Information (Continued)
LDO Enable / Select (Power to External Bridge Sensors)
Step 6
7
6
5
4
3
2
1
0
The XR10910 includes an on-board LDO that provides a
regulated voltage that can be used to power external input
bridge sensors. Two voltage options are available, 3V and
2.65V. The LDO voltage is selected via the I2C compatible
two-wire serial interface.
Master sends code to select LDO
voltage of 2.65V and Enable LDO
during Sleep Mode
0
0
0
0
0
0
0
0
0=
Enable
1=
2.65V
When the XR10910 is powered-up, the default LDO voltage
is 3V.
When the XR10910 is active (not in sleep mode), the LDO
is always on. If the LDO voltage is not used, the LDO output
can be left floating. The LDO can either stay on or shut down
while the XR10910 is in Sleep Mode.
■■
■■
Set LDO to shut down while XR10910 is in Sleep Mode to
save power
Step 7
9
XR10910 sends acknowledge
A
Step 8
0
Master sends stop condition
P
White Block = host to XR10910, Red Block = XR10910 to host
Grey Block = Notes
Set LDO to stay on while XR10910 is in Sleep Mode to
improve wake-up time
The LDO voltage and disable setting are selected via I2C
using the register address 0x07 followed by another byte
of data to select the voltage and disable setting. Refer to
the Register List in Table 1 and the example below for more
information.
Example: The example below illustrates how to select an
LDO voltage of 2.65V and keep the LDO enabled during
Sleep Mode.
To start communication with the XR10910, repeat steps 1-3
as shown in the Inputs and Input Selection section on page
11.
Current Sense Mode (Monitoring the LDO Current)
Current Sense Mode is activated via I2C using the register
address 0x08. When activated, the LDO current is sensed
and a proportional voltage is present at the output of the
XR10910 (ILDO = VOUT/RL). Current Sense Mode stays
active until the XR10910 receives any input select command
(0x10 thru 0x1F).
Current sense mode can be used to monitor the change
over time of the bridge impedance.
Sleep Mode (Analog Power Down)
Step 4
7
6
5
4
3
2
1
0
Master sends address of register to
access
0
0
0
0
0
1
1
1
Sleep Mode is activated via I2C using the register address
0x05. When activated, the XR10910 will enter Sleep Mode.
During Sleep Mode, the analog portion of the XR10910
is disabled. All register settings are retained during Sleep
Mode.
LDO Settings
register address = 0x07
Step 5
9
XR10910 sends acknowledge
A
During Sleep Mode, the nominal supply current will drop
below 70µA (with LDO on) and below 45µA (with LDO off).
Since the LDO Settings register was accessed, the
XR10910 is expecting another byte of data from the master
to complete the command. Refer to the “Byte of Parameter”
column in the Register List (Table 1). D0 and D1 are used to
select the LDO voltage and enable/disable the LDO during
Sleep Mode. Bit 0 (D0) controls the LDO voltage (0: 3V;
1: 2.65V). Bit 1 (D1) is only applicable in Sleep Mode. Bit
1 controls whether the LDO shuts down or stays on during
sleep mode (0: Enable; 1: Disable). When the XR0910 is
active, the LDO is always on.
During Sleep Mode, the master can read the value in any
register that saves a value during sleep mode. The only
I2C commands that can be received or processed is the
SLEEP_OUT (wake up) command (0x04) or the LDO on/off
and voltage command (0x07). All other register addresses
will be ignored.
Register address 0x04 is used to return to normal operation
(exit Sleep Mode).
By default, the XR10910 is active.
REV 1E
18/22
XR10910
Application Information (Continued)
Typical Application – 16:1 Bridge Sensor Interface
The XR10910 was designed to interface multiple bridge sensors with a microcontroller or FPGA as illustrated in Figure 25.
The bridge output signal is differential (Vo+ and Vo-). Ideally, the unloaded bridge output is zero (Vo+ and Vo- are identical).
However, in-exact resistive values result in a difference between Vo+ and Vo-. This bridge offset voltage can be substantial
and vary between sensors. The XR10910 provides the ability to calibrate the bridge offset on each of the 16 bridge sensors
using the on-board DAC.
VDD
VCC
6.8μF
6.8μF
0.1μF
0.1μF
+
+
BRDG
VCC
VDD
0.1μF
BRIDGE 16
LDO
IN16+
IN16-
INA /
PGA
10k
ADC
µC
10nF
16:1
MUX
BRIDGE 1
OUT
±560mV
OFFSET TRIM
10-BIT
DAC
IN1+
VDD
PGA
4.7k
VDD
4.7k
SDA
I2C
CONTROL
IN1-
SCL
XR10910
AGND
DGND
Figure 25: 16:1 Bridge Sensor Interface
Layout Considerations
General layout and supply bypassing play major roles in high frequency performance. Follow the steps below as a basis for
high frequency layout:
■■
Include 6.8µF and 0.1µF ceramic capacitors for power supply decoupling
■■
Place the 6.8µF capacitor within 0.75 inches of the power pin
■■
Place the 0.1µF capacitor within 0.1 inches of the power pin
■■
Connection to the exposed pad is not required. Exposed pad can be connected to ground (GND).
■■
Minimize all trace lengths to reduce series inductances
REV 1E
19/22
XR10910
Mechanical Dimensions
QFN-40 Package
TOP VIEW
BOTTOM VIEW
SIDE VIEW
TERMINAL DETAILS
Drawing No.: POD-00000041
Revision: B.3
REV 1E
20/22
XR10910
Recommended Land Pattern and Stencil
QFN-40 Package
TYPICAL RECOMMENDED LAND PATTERN
TYPICAL RECOMMENDED STENCIL
Drawing No.: POD-00000041
Revision: B.3
REV 1E
21/22
XR10910
Ordering Information(1)
Part Number
Operating Temperature Range
Lead-Free
Package
-40°C to +85°C
Yes(2)
QFN-40
XR10910IL40-F
XR10910IL40TR-F
XR10910IL40EVB
Packaging Method
Tray
Tape & Reel
Evaluation Board
NOTES:
1. Refer to www.exar.com/XR10910 for most up-to-date Ordering Information.
2. Visit www.exar.com for additional information on Environmental Rating.
Revision History
Part
Part
Part
1A
May 2015
Initial Release
1B
July 2015
Added Typical Performance Characteristics section.
1C
May 2016
Updated to latest format and added figure numbers. Updated Figures 1 and 25. Added
Figure 2. Updated page number reference in Gain section of Electrical Characteristics table.
Updated Figure 24. Added clarity to I2C Bus Addressing section. Updated Table 4. Updated
Step 2 in Inputs and Input Selection section.
1D
March 2018
1E
January 2019
Updated to MaxLinear logo. Updated format and Ordering information table. Added I2C
Power Up section.
Correct typo in Recommended Stencil.
Corporate Headquarters:
5966 La Place Court
Suite 100
Carlsbad, CA 92008
Tel.:+1 (760) 692-0711
Fax: +1 (760) 444-8598
www.maxlinear.com
The content of this document is furnished for informational use only, is subject to change without notice, and should not be construed as a commitment by MaxLinear, Inc.. MaxLinear, Inc. assumes
no responsibility or liability for any errors or inaccuracies that may appear in the informational content contained in this guide. Complying with all applicable copyright laws is the responsibility of the
user. Without limiting the rights under copyright, no part of this document may be reproduced into, stored in, or introduced into a retrieval system, or transmitted in any form or by any means (electronic,
mechanical, photocopying, recording, or otherwise), or for any purpose, without the express written permission of MaxLinear, Inc.
Maxlinear, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support
system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless MaxLinear, Inc. receives, in writing, assurances to its satisfaction that: (a) the
risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of MaxLinear, Inc. is adequately protected under the circumstances.
MaxLinear, Inc. may have patents, patent applications, trademarks, copyrights, or other intellectual property rights covering subject matter in this document. Except as expressly provided in any written
license agreement from MaxLinear, Inc., the furnishing of this document does not give you any license to these patents, trademarks, copyrights, or other intellectual property.
Company and product names may be registered trademarks or trademarks of the respective owners with which they are associated.
© 2016 - 2019 MaxLinear, Inc. All rights reserved
XR10910_DS_011519
REV 1E
22/22
工商网监
湘ICP备2023018690号
