XR17C154_05

xr AUGUST 2005 XR17C154 5V PCI BUS QUAD UART REV. 1.3.2 GENERAL DESCRIPTION The XR17C1541 (154) is a quad PCI Bus Universal Asynchronous Receiver and Transmitter (UART) with same package and pin-out as the Exar XR17x158 octal UARTs. The device is designed to meet today’s 32-bit PCI Bus and high bandwidth requirements in communication systems. The global interrupt source register provides a complete interrupt status indication for all 4 channels to speed up interrupt parsing. Each UART is independently controlled and has its own 16C550 compatible 5G register set, transmit and receive FIFOs of 64 bytes, fully programmable transmit and receive FIFO trigger levels, transmit and receive FIFO level counters, automatic hardware flow control with programmable hysteresis, automatic software (Xon/Xoff) flow control, IrDA (Infrared Data Association) encoder/decoder, 8 multi-purpose definable inputs/outputs, and a 16-bit general purpose timer/counter. NOTE: 1 Covered by U.S. Patents #5,649,122, #5,949,787 FEATURES • High Performance Quad UART • PCI Bus 2.2 Target Interface Compliance • 5V PCI Bus Compliant up to 33MHz Clock • 32-bit PCI Bus Interface with EEPROM Interface • A Global Interrupt Source Register for all 4 UARTs • Data Transfer in Byte, Word and Double-word • Data Read/Write Burst Operation • Each UART is independently Controlled with: • 16C550 Compatible 5G (Fifth Gen Register Set • 64-byte Transmit and Receive FIFOs • Transmit and Receive FIFO Level Counters • Automatic RTS/CTS or DTR/DSR Flow Control • Automatic Xon/Xoff Software Flow Control • Automatic RS485 Half-duplex Control Output with 16 Selectable Turn-around Delay • Infrared (IrDA 1.0) Data Encoder/Decoder • Programmable Data Rate with Prescaler • Up to 6.25 Mbps Serial Data Rate at 8X and 5V • Eight Multi-Purpose Inputs/outputs • A General Purpose 16-bit Timer/Counter • Sleep Mode with Automatic Wake-up Indicator • Same Package and Pin-out as the XR17C158, XR17D154 and XR17D158 UART • 20x20x1.4mm 144-LQFP package APPLICATIONS • Remote Access Servers • Ethernet Network to Serial Ports • Network Management • Factory Automation and Process Control • Point-of-Sale Systems • Multi-port RS-232/RS-422/RS-485 Cards FIGURE 1. BLOCK DIAGRAM 5V VCC CLK (33MHz) RST# AD[31:0] C/BE[3:0]# FRAME# IRDY# TRDY# DEVSEL# STOP# INTA# IDSEL PERR# SERR# PAR UART Channel 0 UART Regs 64 Byte TX FIFO TX & RX IR ENDEC GND PCI Local Bus Interface TX0, RX0, DTR0#, DSR0#, RTS0#, CTS0#, CD0#, RI0# Device Configuration Registers BRG 64 Byte RX FIFO UART Channel 1 UART Channel 2 Configuration Space Registers TX3, RX3, DTR3#, DSR3#, RTS3#, CTS3#, CD3#, RI3# MPIO0- MPIO7 XTAL1 XTAL2 TMRCK UART Channel 3 EECK EEDI EEDO EECS ENIR EEPROM Interface 16-bit Timer/Counter Multi-purpose . Inputs/Outputs Crystal Osc/Buffer Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com XR17C154 5V PCI BUS QUAD UART FIGURE 2. PIN OUT OF THE DEVICE DTR1# DSR1# RTS1# CTS1# MPIO0 107 MPIO1 DTR2# RTS2# DSR2# CD1# CD2# CTS2# RI1# TX1 RI2# RX1 TX2 xr REV. 1.3.2 104 103 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 108 106 105 102 79 78 77 76 75 74 MPIO2 GND VCC XTAL2 XTAL1 TEST# VCC EEDO EEDI EECS EECK NC NC NC NC NC NC NC NC TX0 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 MPIO3 RX2 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC ENIR TMRCK MPIO4 MPIO5 MPIO6 MPIO7 VCC GND TX3 DTR3# RTS3# RI3# CD3# DSR3# CTS3# RX3 NC NC NC NC NC NC NC NC GND VCC AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 DTR0# 126 RTS0# 127 RI0# CD0# 128 129 XR17C154 144-LQFP 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 DSR0# 130 CTS0# RX0 INTA# RST# CLK GND VCC AD31 AD30 AD29 AD28 AD27 AD26 AD25 131 132 133 134 135 136 137 138 139 140 141 142 143 144 21 PERR# 22 DEVSEL# 18 SERR# 23 11 12 16 17 31 35 GND FRAME# 15 CBE0 36 32 33 AD8 19 24 CBE1 25 27 AD19 10 AD16 13 CBE2 14 30 20 26 28 29 34 VCC 2 4 1 5 3 6 7 8 9 CBE3 IDSEL TRDY# STOP# AD24 AD23 AD20 AD17 AD22 AD21 AD18 AD15 AD14 AD13 AD12 IRDY# AD11 GND AD10 GND VCC VCC PAR ORDERING INFORMATION PART NUMBER XR17C154CV XR17C154IV PACKAGE 144-Lead LQFP 144-Lead LQFP OPERATING TEMPERATURE RANGE 0°C to +70°C -40°C to +85°C DEVICE STATUS Active Active 2 AD9 xr REV. 1.3.2 XR17C154 5V PCI BUS QUAD UART PIN DESCRIPTIONS Pin Description NAME RST# PIN # 134 TYPE I DESCRIPTION Bus reset input (active low). It resets the PCI local bus configuration space registers, device configuration registers and UART channel registers to the default condition, see Table 19. Bus clock input of up to 33.34MHz at 5V. Address data lines [31:0] (bidirectional). PCI LOCAL BUS INTERFACE CLK AD31-AD25, AD24, AD23-AD16, AD15-AD8, AD7-AD0 FRAME# C/BE3#-C/BE0# IRDY# 135 138-144, 1, 6-13, 26-33, 37-44 15 2, 14, 25, 36 16 I IO I I I Bus transaction cycle frame (active low). It indicates the beginning and duration of an access. Bus Command/Byte Enable [3:0] (active low). This line is multiplexed for bus Command during the address phase and Byte Enables during the data phase. Initiator Ready (active low). During a write, it indicates that valid data is present on data bus. During a read, it indicates the master is ready to accept data. Target Ready (active low). Target request to stop current transaction (active low). 5 Initialization device select (active high). Device select to the XR17C154 (active low). Device interrupt from XR17C154 (open drain, active low). Parity is even across AD[31:0] and C/BE[3:0]# (bidirectional, active high). Parity error indicator to host (active low). Optional in bus target application. System error indicator to host (open drain, active low). Optional in bus target application. UART channel 0 Transmit Data or infrared transmit data. Normal TXD output idles HIGH while infrared TXD output idles LOW. UART channel 0 Receive Data or infrared receive data. Normal RXD input idles HIGH. The infrared pulses typically idle LOW but can be inverted internally prior the decoder by FCTR[4]. UART channel 0 Request to Send or general purpose output (active low). UART channel 0 Clear to Send or general purpose input (active low). UART channel 0 Data Terminal Ready or general purpose output (active low). UART channel 0 Data Set Ready or general purpose input (active low). UART channel 0 Carrier Detect or general purpose input (active low). UART channel 0 Ring Indicator or general purpose input (active low). UART channel 1 Transmit Data or infrared transmit data. Normal TXD output idles HIGH while infrared TXD output idles LOW. UART channel 1 Receive Data or infrared receive data. Normal RXD input idles HIGH. The infrared pulses typically idle LOW but can be inverted internally prior the decoder by FCTR[4]. UART channel 1 Request to Send or general purpose output (active low). TRDY# STOP# IDSEL DEVSEL# INTA# PAR PERR# SERR# 17 21 3 18 133 24 22 23 O O I O OD IO O OD MODEM OR SERIAL I/O INTERFACE TX0 RX0 125 132 O I RTS0# CTS0# DTR0# DSR0# CD0# RI0# TX1 RX1 127 131 126 130 129 128 106 99 O I O I I I O I RTS1# 104 O 3 XR17C154 5V PCI BUS QUAD UART Pin Description NAME CTS1# DTR1# DSR1# CD1# RI1# TX2 RX2 PIN # 100 105 101 102 103 88 81 TYPE I O I I I O I DESCRIPTION xr REV. 1.3.2 UART channel 1 Clear to Send or general purpose input (active low). UART channel 1 Data Terminal Ready or general purpose output (active low). UART channel 1 Data Set Ready or general purpose input (active low). UART channel 1 Carrier Detect or general purpose input (active low). UART channel 1 Ring Indicator or general purpose input (active low). UART channel 2 Transmit Data or infrared transmit data. Normal TXD output idles HIGH while infrared TXD output idles LOW. UART channel 2 Receive Data or infrared receive data. Normal RXD input idles HIGH. The infrared pulses typically idle LOW but can be inverted internally prior the decoder by FCTR[4]. UART channel 2 Request to Send or general purpose output (active low). UART channel 2 Clear to Send or general purpose input (active low). UART channel 2 Data Terminal Ready or general purpose output (active low). UART channel 2 Data Set Ready or general purpose input (active low). UART channel 2 Carrier Detect or general purpose input (active low). UART channel 2 Ring Indicator or general purpose input (active low). UART channel 3 Transmit Data or infrared transmit data. Normal TXD output idles HIGH while infrared TXD output idles LOW. UART channel 3 Receive Data or infrared receive data. Normal RXD input idles HIGH. The infrared pulses typically idle LOW but can be inverted internally prior the decoder by FCTR[4]. UART channel 3 Request to Send or general purpose output (active low). UART channel 3 Clear to Send or general purpose input (active low). UART channel 3 Data Terminal Ready or general purpose output (active low). UART channel 3 Data Set Ready or general purpose input (active low). UART channel 3 Carrier Detect or general purpose input (active low). UART channel 3 Ring Indicator or general purpose input (active low). Multi-purpose input/output 0. The function of this pin is defined thru the Configuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT Multi-purpose input/output 1. The function of this pin is defined thru the Configuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT. Multi-purpose input/output 2. The function of this pin is defined thru the Configuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT. Multi-purpose input/output 3. The function of this pin is defined thru the Configuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT. Multi-purpose input/output 4. The function of this pin is defined thru the Configuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT. Multi-purpose input/output 5. The function of this pin is defined thru the Configuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT. Multi-purpose input/output 6. The function of this pin is defined thru the Configuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT. Multi-purpose input/output 7. The function of this pin is defined thru the Configuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT. RTS2# CTS2# DTR2# DSR2# CD2# RI2# TX3 RX3 86 82 87 83 84 85 62 55 O I O I I I O I RTS3# CTS3# DTR3# DSR3# CD3# RI3# ANCILLARY SIGNALS MPIO0 MPIO1 MPIO2 MPIO3 MPIO4 MPIO5 MPIO6 MPIO7 60 56 61 57 58 59 108 107 74 73 68 67 66 65 O I O I I I I/O I/O I/O I/O I/O I/O I/O I/O 4 xr REV. 1.3.2 XR17C154 5V PCI BUS QUAD UART Pin Description NAME EECK PIN # 116 TYPE O DESCRIPTION Serial clock to EEPROM. An internal clock of CLK divide by 256 is used for reading the vendor and sub-vendor ID during power up or reset. However, it can be manually clocked thru the Configuration Register REGB. Chip select to a EEPROM device like 93C46. It is manually selectable thru the Configuration Register REGB. Requires a pull-up 4.7K ohm resister for external sensing of EEPROM during power up. See DAN112 for further details. Write data to EEPROM device. It is manually accessible thru the Configuration Register REGB. The 154 auto-configuration register interface logic uses the 16-bit format. Read data from EEPROM device. It is manually accessible thru the Configuration Register REGB. Crystal or external clock input of up to 50MHz for data rate of 3.125Mbps at 5V. Crystal or buffered clock output. 16-bit timer/counter external clock input. Infrared mode enable (active high). This pin is sampled during power up, following a hardware reset (RST#) or soft-reset (register RESET). It can be used to start up all 4 UARTs in the infrared mode. The sampled logic state is transferred to MCR bit-6 in the UART. Software can override this pin thereafter and enable or disable it. Factory Test. Connect to VCC for normal operation. +5V (PCI Compliance). For 3.3V operation, see the XR17D154. Power supply common, ground. No Connection. These pins are reserved and used by the octal PCI UART XR17C158. EECS 115 O EEDI 114 O EEDO XTAL1 XTAL2 TMRCK ENIR 113 110 109 69 70 I I O I I TEST# VCC GND NC 111 4,19,34,45,64, 90,112,137 5,20,35,46,63, 89,136 47-54, 71,72,75-80, 91-98, 117-124 I PWR PWR NOTE: Pin type: I=Input, O=Output, IO= Input/output, OD=Output Open Drain. 5 XR17C154 5V PCI BUS QUAD UART xr REV. 1.3.2 FUNCTIONAL DESCRIPTION The XR17C154 (154) integrates the functions of 4 enhanced 16550 UARTs with the PCI Local Bus interface and a non-volatile memory interface for PCI bus’s plug-and-play auto-configuration, a 16-bit timer/counter, 8 multi-purpose inputs/outputs, and an on-chip oscillator. The PCI local bus is a synchronous timing bus where all bus transactions are associated to the bus clock of up to 33.34MHz. The 154 supports 32-bit wide read and write data transfer operations including data burst mode through the PCI Local Bus interface. Read and write data operations may be in byte, word or double-word (DWORD) format. A single 32-bit interrupt status register provides interrupts status for all 4 UARTs, timer/counter, multipurpose inputs/outputs, and a special sleep wake up indicator. There are three sets of register in the device. First, the PCI local bus configuration registers for PCI auto configuration. A set of device configuration registers for overall control, 32-bit wide transmit and receive data transfer, and monitoring of the 4 UART channels. Lastly, each UART channel has its own 16550 UART compatible configuration register set for individual channel control, status, and byte wide data transfer. Each UART has 64-byte FIFOs, automatic RTS/CTS or DTR/DSR hardware flow control with hysteresis control, automatic Xon/Xoff and special character software flow control, programmable transmit and receive FIFO trigger level, FIFO level counters, infrared encoder and decoder (IrDA ver. 1.0), programmable baud rate generator with a prescaler of 1X or 4X, and data rate up to 6.25 Mbps at 8X sampling clock. The XR17C154 bus timing and drive capability meets the PCI local bus specification revision 2.2 for 5 volt operation over the temperature range. For a pin-to-pin compatible part that can operate at 3.3V, see the XR17D154. The XR17C154 is available in a thin 144-pin LQFP (20x20x1.4mm) package in commercial and industrial temperature ranges. PCI LOCAL BUS INTERFACE This is the host interface and it meets the PCI Local Bus Specification revision 2.2. The PCI local bus operations are synchronous meaning each transaction is associated to the bus clock. The XR17C154 can operate with the bus clock of up to a 33.34MHz. Data transfers operation can be formatted in 8-bit, 16-bit, 24-bit or 32bit wide. With 32-bit data operations, it pushes the data transfer rate on the bus up to 132 MByte/sec. This increases the overall system’s communication performance up to 16 times better than the 8-bit ISA bus. See PCI local bus specification revision 2.2 for bus operation details. PCI Local Bus Configuration Space Registers A set of PCI local bus configuration space register is provided. These registers provide the PCI local bus operating system with the card’s vendor ID, device ID, sub-vendor ID, product model number, and resources and capabilities. The PCI local bus operating system collects this data from all the cards on the bus during the auto configuration phase that follows immediately after a power up or system reset/reboot. After it has sorted out all devices on the bus, it defines and download the operating conditions to the cards. One of the definitions is the base address loaded into the Base Address Register (BAR) where the card will be operating in the PCI local bus memory space. EEPROM Interface An external 93C46 EEPROM is only used to store the vendor’s ID and model number, and the sub-vendor’s ID and product model number. This information is only used with the plug-and-play auto configuration of the PCI local bus. These data provide automatic hardware installation onto the PCI bus. The EEPROM interface consists of 4 signals, EEDI, EEDO, EECS, and EECK. The EEPROM is not needed when auto configuration is not required in the application. However, If your design requires non-volatile memory for other purpose. It is possible to store and retrieve data on the EEPROM through a special PCI device configuration register. See application note DAN112 for its programming details. 6 xr REV. 1.3.2 XR17C154 5V PCI BUS QUAD UART 1.0 XR17C154 REGISTERS The XR17C154 UART has three different sets of registers as shown in Figure 3. The PCI local bus configuration space registers are for plug-and-play auto-configuration when connecting the device to the PCI bus. This auto-configuration feature makes installation very easy into a PCI system and it is part of the PCI local bus specification. The second register set is the device configuration registers that are accessible directly from the PCI bus for programming general operating conditions of the device and monitoring the status of various functions. These registers are mapped into 2K of the PCI bus memory address space. These functions include all 4 channel UART’s interrupt control and status, 16-bit general purpose timer control and status, multipurpose inputs/outputs control and status, sleep mode, soft-reset, and device identification and revision. And lastly, each UART channel has its own set of 5G internal UART configuration registers for its own operation control and status reporting. All 4 sets of channel registers are embedded inside the device configuration registers space, which provides faster access. The following paragraphs describe all 3 sets of registers in detail. FIGURE 3. THE XR17C154 REGISTER SETS PCI Local Bus Configuration Space Registers for Plugand-Play Auto Configuration 0x0000 0x0080 0x0100 0x0200 0x0400 0x0600 0x07FF Device Configuration Registers 4 channel Interrupts, Multipurpose I/Os, 16-bit Timer/Counter, Sleep, Reset, DVID, DREV Device Configuration and UART[3:0] Configuration Registers are mapped on to the Base Address Register (BAR) in a 2Kbyte of memory address space Vendor and Sub-vendor ID and Product Model Number in External EEPROM Channel 0 INT, MPIO, TIMER, REG Channel 0 Channel 1 Channel 2 Channel 3 PCI Local Bus Target Interface UART[3:0] Configuration Registers 16550 Compatible and EXAR Enhanced Registers PCIREGS-1 1.1 PCI LOCAL BUS CONFIGURATION SPACE REGISTERS The PCI local bus configuration space registers are responsible for setting up the device’s operating environment in the PCI local bus. The pre-defined operating parameters of the device are read by the PCI bus plugand-play auto-configuration manager in the operating system. After the PCI bus has collected all data from every device/card on the bus, it defines and downloads the memory mapping information to each device/card about their individual operation memory address location and conditions. The operating memory mapped address location is downloaded into the Base Address Register (BAR) register, 0x10. The plug-and-play auto configuration feature is only available when an external 93C46 EEPROM is used. The EEPROM contains the device vendor and sub-vendor data required by the auto-configuration setup. 7 XR17C154 5V PCI BUS QUAD UART SPACE, xr REV. 1.3.2 TABLE 1: PCI LOCAL BUS CONFIGURATION SPACE REGISTERS ADDRESS 0x00 BITS 31:16 15:0 0x04 31:28 27 26:25 24 23 22:16 TYPE RWR1 RWR1 RO R-Reset RO RO RO RO DESCRIPTION Device ID (Exar device ID number or from EEPROM) Vendor ID (Exar ID or from EEPROM) specified by PCISIG Status bits (error reporting bits) Target Abort. Set whenever 154 terminates with a target abort. DEVSEL# timing. Unimplemented bus master error reporting bit Fast back to back transactions are supported Reserved Status bits Command bits (reserved) SERR# driver enable. Logic 1=enable driver and 0=disable driver Parity error enable. Logic 1=respond to parity error and 0=ignore Command controls a device’s response to mem space accesses: 0=disable mem space accesses, 1=enable mem space accesses Command controls a device’s response to I/O space accesses: 0 = disable I/O space accesses 1 = enable I/O space accesses Class Code (Simple 550 Communication Controller). Revision ID (Exar device revision number) BIST (Built-in Self Test) Header Type (a single function device with one BAR) Unimplemented Latency Timer (needed only for bus master) Unimplemented Cache Line Size Memory Base Address Register (BAR) Claims a 2K address space for the memory mapped UARTs Unimplemented Base Address Register (returns zeros) Unimplemented Base Address Register (returns zeros) Unimplemented Base Address Register (returns zeros) Unimplemented Base Address Register (returns zeros) Unimplemented Base Address Register (returns zeros) Reserved RESET VALUE (HEX) 0x0154 0x13A8 0000 0 00 0 1 000 0000 0x0000 0 0 0 0 0x070002 Current Rev. value 0x00 0x00 0x00 0x00 0x00 0xX000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 15:9,7, RO 5,4,3,2 8 6 1 0 0x08 31:8 7:0 0x0C 31:24 23:16 15:8 7:0 0x10 31:11 10:0 0x14 0x18h 0x1C 0x20 0x24 0x28 31:0 31:0 31:0 31:0 31:0 31:0 WO WO RWR RO RO RO RO RO RO RO RW RO RO RO RO RO RO RO 8 xr REV. 1.3.2 XR17C154 5V PCI BUS QUAD UART TABLE 1: PCI LOCAL BUS CONFIGURATION SPACE REGISTERS ADDRESS 0x2C BITS 31:16 15:0 TYPE RWR1 RWR1 RO RO RO RO RO RO RWR DESCRIPTION Subsystem ID (write from external EEPROM by customer) Subsystem Vendor ID (write from external EEPROM by customer) Expansion ROM Base Address (Unimplemented) Reserved (returns zeros) Reserved (returns zeros) Unimplemented MAXLAT Unimplemented MINGNT Interrupt Pin, use INTA#. Interrupt Line. RESET VALUE (HEX) 0x0000 0x0000 0x00000000 0x00000000 0x00000000 0x00 0x00 0x01 0xXX 0x30 0x34 0x38 0x3C 31:0 31:0 31:0 31:24 23:16 15:8 7:0 RWR1=Read/Write from external EEPROM. RWR=Read/Write from AD[31:0]. RO= Read Only. WO=Write Only. 1.2 DEVICE CONFIGURATION REGISTER SET The device configuration registers and a special way to access each of the UART’s transmit and receive data FIFOs are accessible directly from the PCI data bus. This provides easy programming of general operating parameters to the 154 UART and for monitoring the status of various functions. The registers occupy 2K of PCI bus memory address space. These addresses are offset onto the basic memory address, a value loaded into the Memory Base Address Register (BAR) in the PCI local bus configuration register set. These registers control or report on all 4 channel UARTs functions that include interrupt control and status, 16-bit general purpose timer control and status, multipurpose inputs/outputs control and status, sleep mode control, soft-reset control, and device identification and revision, and others. The registers set is mapped into 4 address blocks where each UART channel occupies 512 bytes memory space for its own 16550 compatible configuration registers. The device configuration and control registers are embedded inside the UART channel zero’s address space between 0x0080 to 0x0093. All these registers can be accessed in 8, 16, 24 or 32 bit width depending on the starting address given by the host at beginning of the bus cycle. Transmit and receive data may be loaded or unloaded in 8, 16, 24 or 32 bit format to the register’s address. Every time a read or write operation is made to the transmit or receive register, its FIFO data pointer is automatically bumped to the next sequential data location either in byte, word or dword. One special case applies to the receive data unloading when reading the receive data together with its LSR register content. The host must read them in 16 or 32 bits format in order to maintain integrity of the data byte with its associated error flags. 9 XR17C154 5V PCI BUS QUAD UART TABLE 2: XR17C154 DEVICE CONFIGURATION REGISTERS OFFSET ADDRESS 0x000 - 0x00F 0x010 - 0x07F 0x080 - 0x093 0x094 - 0x0FF 0x100 - 0x13F 0x100 - 0x13F 0x140 - 0x17F 0x180 - 0x1FF MEMORY SPACE UART channel 0 Regs Reserved DEVICE CONFIG. REGISTERS Reserved UART 0 – Read FIFO UART 0 – Write FIFO Reserved UART 0 – Read FIFO with errors Read-Only 16/32 Read-Only Write-Only 8/16/24/32 8/16/24/32 (Table 3) 8/16/24/32 READ/WRITE (Table 11 & Table 12) DATA WIDTH 8/16/24/32 xr REV. 1.3.2 COMMENT First 8 regs are 16550 compatible 64 bytes of RX FIFO data 64 bytes of TX FIFO data 64 bytes of RX FIFO data + LSR 0x200 - 0x20F 0x210 - 0x2FF 0x300 - 0x33F 0x300 - 0x33F 0x340 - 0x37F 0x380 - 0x3FF UART channel 1 Regs Reserved UART 1 – Read FIFO UART 1 – Write FIFO Reserved UART 1 – Read FIFO with errors (Table 11 & Table 12) 8/16//24/32 First 8 regs are 16550 compatible Read-Only Write-Only 8/16/24/32 8/16/24/32 64 bytes of RX FIFO data 64 bytes of TX FIFO data Read-Only 16/32 64 bytes of RX FIFO data + LSR 0x400 - 0x40F 0x410 - 0x4FF 0x500 - 0x53F 0x500 - 0x53F 0x540 - 0x57F 0x580 - 0x5FF UART channel 2 Regs Reserved UART 2 – Read FIFO UART 2 – Write FIFO Reserved UART 2 – Read FIFO with errors (Table 11 & Table 12) 8/16/24/32 First 8 regs are 16550 compatible Read-Only Write-Only 8/16/24/32 8/16/24/32 64 bytes of RX FIFO data 64 bytes of TX FIFO data Read-Only 16/32 64 bytes of RX FIFO data + LSR 0x600 - 0x60F 0x610 - 0x6FF 0x700 - 0x73F 0x700 - 0x73F UART channel 3 Regs Reserved UART 3 – Read FIFO UART 3 – Write FIFO (Table 11 & Table 12) 8/16/24/32 First 8 regs are 16550 compatible Read-Only Write-Only 8/16/24/32 8/16/24/32 64 bytes of RX FIFO data 64 bytes of TX FIFO data 10 xr REV. 1.3.2 XR17C154 5V PCI BUS QUAD UART TABLE 2: XR17C154 DEVICE CONFIGURATION REGISTERS OFFSET ADDRESS 0x740 - 0x77F 0x780 - 0x7FF MEMORY SPACE Reserved UART 3 – Read FIFO with errors READ/WRITE DATA WIDTH COMMENT Read-Only 16/32 64 bytes of RX FIFO data + LSR 11 XR17C154 5V PCI BUS QUAD UART TABLE 3: DEVICE CONFIGURATION REGISTERS SHOWN IN BYTE ALIGNMENT ADDRESS [A7:A0] Ox080 Ox081 Ox082 Ox083 REGISTER INT0 [7:0] INT1 [15:8] INT2 [23:16] INT3 [31:24] READ/WRITE COMMENT Read-only Interrupt [3:0], Reserved [7:4] Read-only Read-only [3:0], Reserved [7:4] Reserved xr REV. 1.3.2 RESET STATE Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Ox084 Ox085 Ox086 Ox087 TIMERCNTL TIMER TIMERLSB TIMERMSB Read/Write Timer Control Reserved Read/Write Timer LSB Read/Write Timer MSB Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Ox088 Ox089 Ox08A Ox08B 8XMODE REGA RESET SLEEP Read/Write Reserved Write-only Self clear bits after executing Reset [3:0] Read/Write Sleep mode [3:0] Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Ox08C Ox08D Ox08E Ox08F DREV DVID REGB MPIOINT Read-only Device revision Read-only Device identification Write-only Read/Write MPIO interrupt mask Bits 7-0 = 0x04 Bits 7-0 = 0x24 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Ox090 Ox091 Ox092 Ox093 MPIOLVL MPIO3T MPIOINV MPIOSEL Read/Write MPIO level control Read/Write MPIO output control Read/Write MPIO input polarity select Read/Write MPIO select Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0xFF TABLE 4: DEVICE CONFIGURATION REGISTERS SHOWN IN DWORD ALIGNMENT ADDRESS 0x080-083 0x084-087 0x088-08B 0x08C-08F 0x090-093 REGISTER INTERRUPT (read-only) TIMER (read/write) ANCILLARY1 (read/write) ANCILLARY2 (read-only) MPIO (read/write) BYTE 3 [31:24] INT3 TIMERMSB SLEEP MPIOINT MPIOSEL BYTE 2 [23:16] INT2 TIMERLSB RESET REGB MPIOINV BYTE 1 [15:8] INT1 TIMER (reserved) REGA (reserved) DVID MPIO3T BYTE 0 [7:0] INT0 TIMERCNTL 8XMODE DREV MPIOLVL 12 xr REV. 1.3.2 XR17C154 5V PCI BUS QUAD UART 1.2.1 The Interrupt Status Register The XR17C154 has a 32-bit wide register [INT0, INT1, INT2 and INT3] to provide interrupt information and supports two interrupt schemes. The first scheme uses bits 0 to 3 of an 8-bit indicator (INT0) representing channels 0 to 3 of the XR17C154, respectively. This permits the interrupt routine to quickly vector and serve that UART channel and determine the source(s) in each individual routines. INT0 bit-0 represents the interrupt status for UART channel 0 when its transmitter, receiver, line status, or modem port status requires service. Other bits in the INT0 register provide indication for the other channels with bit-3 representing UART channel 3 respectively. Bits 4 through 7 are reserved and remain at a logic 0. The second scheme provides detail about the source of the interrupts for each UART channel. All the interrupts are encoded into a 3-bit code. This 3-bit code represents 7 interrupts corresponding to individual UART’s transmitter, receiver, line status, modem port status. INT1 and INT2 registers provide the 12-bit interrupt status for all 4 channels. Bits 8, 9 and 10 representing channel 0 and bits 17, 18 and 19 representing channel 3 respectively. Bits 20 to 31 are reserved and remain at a logic 0. All 4 channel interrupts status are available with a single DWORD read operation. This feature allows the host quickly vectors and serves the interrupts, reducing service interval, hence, reduce host bandwidth requirement. Figure 4 shows the 4-byte interrupt register and its make up. GLOBAL INTERRUPT REGISTER (DWORD) INT3 [31:24] INT2 [23:16] [default 0x00-00-00-00] INT0 [7:0] INT1 [15:8] A special interrupt condition is generated by the 154 when it wakes up from sleep mode. This special interrupt is cleared by reading the INT0 register. If there are not any other interrupts pending, the value read from INT0 would be 0x00. INT0 [7:0] Channel Interrupt Indicator Each bit gives an indication of the channel that has requested for service. Bit-0 represents channel 0 and bit-3 indicates channel 3. Logic 1 indicates that a channel has called for service. Bits 4 to 7 are reserved and remain at a logic 0. The interrupt bit clears after reading the appropriate register of the interrupting channel register, see Interrupt Clearing section. The INT0 register provides individual status for each channel INT0 Register Individual UART Channel Interrupt Status Rsvd Rsvd Rsvd Rsvd Ch-3 Ch-2 Ch-1 Ch-0 Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 INT3, INT2 and INT1 [32:8] Twenty four bit encoded interrupt indicator. Each channel’s interrupt is encoded into 3 bits for receive, transmit, and status. Bit [10:8] represent channel 0 and go up to channel 3 with bits [19:17]. The 3 bit encoding and their priority order are shown below in Table 5. The Timer and MPIO interrupts are for the device and therefore they exist within channel 0 space (bits [10:8]) and not in other channel. 13 XR17C154 5V PCI BUS QUAD UART . xr REV. 1.3.2 FIGURE 4. THE GLOBAL INTERRUPT REGISTER, INT0, INT1, INT2 AND INT3 Interrupt Registers, INT0, INT1, INT2 and INT3 INT3 Register Rsvd Bit N+2 Bit N+1 Bit N Bit N+2 Rsvd Bit N+1 Bit N Bit N+2 Rsvd Bit N+1 Bit N Bit N+2 Rsvd Bit N+1 Bit N INT2 Register Channel-3 Bit N+2 Bit N+1 Bit N Channel-2 Bit N+2 Bit N+1 Bit N INT1 Register Channel-1 Bit N+2 Bit N+1 Bit N Channel-0 Bit N+2 Bit N+1 Bit N INT0 Register Rsvd Rsvd Rsvd Rsvd Ch-3 Ch-2 Ch-1 Ch-0 Bit-3 Bit-2 Bit-1 Bit-0 Bit-7 Bit-6 Bit-5 Bit-4 TABLE 5: UART CHANNEL [3:0] INTERRUPT SOURCE ENCODING PRIORITY x 1 2 3 4 5 6 7 BIT[N+2] 0 0 0 0 1 1 1 1 BIT[N+1] 0 0 1 1 0 0 1 1 BIT[N] 0 1 0 1 0 1 0 1 None RXRDY and RX Line Status (logic OR of LSR[4:1]) RXRDY Time-out TXRDY, THR or TSR (auto RS485 mode) empty MSR, RTS/CTS or DTR/DSR delta or Xoff/Xon det. or special char. detected Reserved. MPIO pin(s). Available only within channel 0, reserved in other channels. TIMER Time-out. Available only within channel 0, reserved in other channels. INTERRUPT SOURCE(S) TABLE 6: UART CHANNEL [3:0] INTERRUPT CLEARING RXRDY is cleared by reading data in the RX FIFO until it falls below the trigger level. RXRDY Time-out is cleared by reading data until the RX FIFO is empty. RX Line Status interrupt clears after reading the LSR register. TXRDY interrupt clears after reading ISR register that is in the UART channel register set. Modem Status Register interrupt clears after reading MSR register that is in the UART channel register set. RTS/CTS or DTR/DSR delta interrupt clears after reading MSR register that is in the UART channel register set. Xoff/Xon interrupt clears after reading the ISR register that is in the UART channel register set. Special character detect interrupt is cleared by a read to ISR or after the next character is received. TIMER Time-out interrupt clears after reading the TIMERCNTL register that is in the Device Configuration register set. MPIO interrupt clears after reading the MPIOLVL register that is in the Device Configuration register set. 14 xr REV. 1.3.2 XR17C154 5V PCI BUS QUAD UART 1.2.2 General Purpose 16-bit Timer/Counter [TIMERMSB, TIMELSB, TIMER, TIMECNTL] (DEFAULT 0XXX-XX-00-00) A 16-bit down-count timer for general purpose timer or counter. Its clock source may be selected from internal crystal oscillator or externally on pin TMRCK. The timer can be set to be a single-shot for a one-time event or re-triggerable for continue interval. An interrupt may be generated in the INT Register when the timer times out. It is controlled through 4 configuration registers [TIMERCNTL, TIMER, TIMELSB, TIMERMSB]. These registers provide start/stop and re-triggerable or one-shot operation. The time-out output of the Timer can be set to generate an interrupt for system or event alarm. FIGURE 5. TIMER/COUNTER CIRCUIT. TIMERMSB and TIMERLSB (16-bit Value) TMRCK OSC. CLOCK TIMERCNTL [3] TIMERCNTL [1] TIMERCNTL [2] TIMERCNTL [0] TIMERCNTL [4] 1 0 Clock Select Start/Stop Single/Re-triggerable Timer Interrupt Enable 16-Bit Timer/Counter Time-out 1 0 Timer Interrupt, Ch-0 INT=7 No Interrupt Re-trigger 0 1 1 0 MPIO[0] MPIOLVL[0] Single-shot TABLE 7: TIMER CONTROL REGISTERS TIMERCNTL [0] TIMERCNLT [1] TIMERCNTL [2] TIMERCNTL [3] TIMERCNTL [4] TIMERCNTL [7:5] Logic 0 (default) disables Timer-Counter interrupt and logic one enables the interrupt, reading the TIMERCNTL clears the interrupt. Logic 0 (default) stops/pauses the timer and logic one starts/re-starts the timer/counter. Logic 0 (default) selects re-trigger timer function and logic one selects one-shot (timer function. Logic 0 (default) selects internal and logic one selects external clock to the timer/counter. Routes the Timer-Counter interrupt to MPIO[0] if MPIOSEL[0]=0 for external event control. Reserved (defaults to zero) TIMERCNTL Register Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Rsvd Rsvd Rsvd MPIO[0] Clock Single/ Control Select Re-trigger Bit-1 Bit-0 Start/ Stop INT Enable TIMER [15:8] Reserved 15 XR17C154 5V PCI BUS QUAD UART TIMERMSB [31:24] and TIMERLSB [23:16] xr REV. 1.3.2 TIMERMSB and TIMERLSB form a 16-bit value. The least-significant bit of the timer is being bit [0] of the TIMERLSB with most-significant-bit being bit [7] in TIMERMSB. Notice that these registers do not hold the current counter value when read. Reading the TIMERCNTL register will clear its interrupt. Default value is zero (timer disabled) upon powerup and reset. 16-Bit Timer/Counter Programmable Registers TIMERMSB Register Bit-15 Bit-14 Bit-13 Bit-12 Bit-11 Bit-10 Bit-9 Bit-8 Bit-7 Bit-6 TIMERLSB Register Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 1.2.3 8XMODE [7:0] (default 0x00) Each bit selects 8X or 16X sampling rate for that UART channel, bit-0 is channel 0. Logic 0 (default) selects normal 16X sampling with logic one selects 8X sampling rate. Transmit and receive data rates will double by selecting 8X. 8XMODE Register Individual UART Channel 8X Clock Mode Enable Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 Rsvd Rsvd Rsvd Rsvd Ch-3 Ch-2 Ch-1 Ch-0 1.2.4 1.2.5 REGA [15:8] Reserved RESET [23:16] (default 0x00) Bits 0 to 3 of the Reset register [RESET] provides the software with the ability to reset the UART(s) when there is a need. Each bit is self-resetting after it is written a logic 1 to perform a reset to that channel. All registers in that channel will be reset to the default condition, see Table 19 for details. Bit-0 =1 resets UART channel 0 with bit-3=1 resets channel 3 RESET Register Individual UART Channel Reset Enable Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 Rsvd Rsvd Rsvd Rsvd Ch-3 Ch-2 Ch-1 Ch-0 16 xr REV. 1.3.2 XR17C154 5V PCI BUS QUAD UART 1.2.6 SLEEP [31:24](default 0x00) Each UART can be separately enabled to enter Sleep mode through the Sleep register. Sleep mode reduces power consumption when the system needs to put the UART(s) to idle. All of these conditions must be satisfied for the 154 to enter sleep mode: • no interrupts pending (INT0 = 0x00) • divisor is a non-zero value for all channels (ie. DLL = 0x1) • sleep mode is enabled (SLEEP = 0x0F) • modem inputs for all channels are not toggling (MSR bits 0-3 = 0) • RX input pins for all channels are idling HIGH The 154 stops its crystal oscillator to conserve power in the sleep mode. User can check the XTAL2 pin for no clock output as an indication that the device has entered the sleep mode. The 154 resumes normal operation by any of the following: • a receive data start bit transition (HIGH to LOW) • a data byte is loaded to the transmitter, THR or FIFO • a change of logic state on any of the modem or general purpose serial inputs: CTS#, DSR#, CD#, RI# If the 154 is awakened by any one of the above conditions, it will return to the sleep mode automatically after all interrupting conditions have been serviced and cleared. If the 154 is awakened by the modem inputs, a read to the MSR is required to reset the modem inputs. In any case, the sleep mode will not be entered while an interrupt is pending from any channel. The 154 will stay in the sleep mode of operation until it is disabled by setting Sleep = 0x00. In this case, the quad UART is awaken by any of the UART channel from a receive data byte or a change on the serial port. The UART is ready after 32 crystal clocks to ensure full functionality. Also, a special interrupt is generated with an indication of no pending interrupt. Reading INT0 will clear this special interrupt. Logic 0 (default) is disable and logic 1 is enable to sleep mode. SLEEP Register Individual UART Channel Sleep Enable Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 Rsvd Rsvd Rsvd Rsvd Ch-3 Ch-2 Ch-1 Ch-0 1.2.7 Device Identification and Revision There are two internal registers that provide device identification and revision, DVID and DREV registers. The 8-bit content in the DVID register provides device identification. A return value of 0x24 from this register indicates the device is a XR17C154. The DREV register returns an 8-bit value of 0x01 for revision A with 0x02 equals to revision B and so forth. This information is very useful to the software driver for identifying which device it is communicating with and to keep up with revision changes. DVID [15:8] Device identification for the type of UART. The upper nibble indicates it is a XR17Cxxx series with lower nibble indicating the number of channels. Examples: XR17C158 or XR17D158 = 0x28 XR17C154 or XR17D154 = 0x24 XR17C152 or XR17D152 = 0x22 DREV [7:0] Revision number of the XR17C154. A 0x01 represents "revision-A" with 0x02 for rev-B and so forth. 17 XR17C154 5V PCI BUS QUAD UART REGB [23:16] (default 0x00) xr REV. 1.3.2 REGB register provides a control for simultaneous write to all 8 UARTs configuration register or individually. This is very useful for device initialization in the power up and reset routines. Also, the register provides a facility to interface to the non-volatile memory device such as a 93C46 EEPROM. In embedded applications, the user can use this facility to store proprietary data. 1.2.8 REGB Register Logic 0 (default) write to each UART configuration registers individually. Logic 1 enables simultaneous write to all 8 UARTs configuration register. REGB[19:17] REGB[20] (Write-Only) REGB[21] (Write-Only) REGB[22] (Write-Only) REGB[23] (Read-Only) Reserved Control the EECK, clock, output (pin 116) on the EEPROM interface. Control the EECS, chips select, output (pin 115) to the EEPROM device. EEDI (pin 114) data input. Write data to the EEPROM device. EEDO (pin 113) data output. Read data from the EEPROM device. REGB[16](Read/Write) 1.2.9 Multi-Purpose Inputs and Outputs The 154 provides 8 multi-purpose inputs/outputs [MPIO7:0] for general use. Each pin can be programmed to be an input or output function. The input logic state can be set for normal or inverted level, and optionally set to generate an interrupt. The outputs can be set to be normal HIGH or LOW state, or 3-state. Their functions and definitions are programmed through 5 registers: MPIOINT, MPIOLVL, MPIO3T, MPIOINV and MPIOSEL. If all 8 pins are set for inputs, all 8 interrupts would be OR’ed together. The Or’ed interrupt is reported in the channel 0 UART interrupt status (3-bit interrupt encoding, bits [10:8], in the global interrupt status register. The pins may also be programmed to be outputs and to the 3-state condition for signal sharing. 1.2.10 MPIO REGISTER Bit 7 represents MPIO7 pin and bit 0 represents MPIO0 pin. There are 5 registers that select, control and monitor the 8 multipurpose inputs and outputs. Figure 6 shows the internal circuitry. 18 xr REV. 1.3.2 XR17C154 5V PCI BUS QUAD UART FIGURE 6. MULTIPURPOSE INPUT/OUTPUT INTERNAL CIRCUIT MPIOINT [7:0] INT AND Rising Edge Detection AND 1 MPIOLVL [7:0] Read Input Level MPIO Pin [7:0] 0 MPIOINV [7:0] (Input Inversion Enable =1) MPIOLVL [7:0] (Output Level) MPIO3T [7:0] (3-state Enable =1) OR MPIOSEL [7:0] (Select Input=1, Output=0 ) MPIOCKT MPIOINT [7:0] (default 0x00) Enable multipurpose input pin interrupt. If the MPIO pin is selected by MPIOSEL as input then bit-0 enables input pin 0 for interrupt, and bit-7 enables input pin 7. No interrupt is enable if the pin is selected to be an output. The interrupt is edge sensing and determined by MPIOINV and MPIOLVL registers. The MPIO interrupt clears after a read to register MPIOLVL. The combination of MPIOLVL and MPIOINV determines the interrupt being active low or active high, it’s level trigger. Logic 0 (default) disables the pin’s interrupt and logic 1 enables it. MPIOINT Register Multipurpose Input/Output Interrupt Enable Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 MPIO7 MPIO6 MPIO5 MPIO4 MPIO3 MPIO2 MPIO1 MPIO0 19 XR17C154 5V PCI BUS QUAD UART MPIOLVL [7:0] (default 0x00) xr REV. 1.3.2 Output pin level control and input level status. The status of the input pin(s) is read on this register and output pins are controlled on this register. A logic 0 (default) sets the output to low and a logic 1 sets the output pin to high. The MPIO interrupt will clear upon reading this register. MPIOLVL Register Multipurpose Output Level Control Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 MPIO7 MPIO6 MPIO5 MPIO4 MPIO3 MPIO2 MPIO1 MPIO0 MPIO3T [7:0] (default 0x00) Output pin tri-state control. A logic 0 (default) sets the output to active level per register MPIO3T settling, a logic 1 sets the output pin to tri-state. MPIO3T Register Multipurpose Output 3-state Enable Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 MPIO7 MPIO6 MPIO5 MPIO4 MPIO3 MPIO2 MPIO1 MPIO0 MPIOINV [7:0] (default 0x00) Input inversion control. A logic 0 (default) does not invert the input pin logic. A logic 1 inverts the input logic level. MPIOINV Register Multipurpose Input Signal Inversion Enable Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 MPIO7 MPIO6 MPIO5 MPIO4 MPIO3 MPIO2 MPIO1 MPIO0 MPIOSEL [7:0] (default 0xFF) Multipurpose input/output pin select. This register defines the functions of the pins. A logic 1 (default) defines the pin for input and a logic 0 for output. MPIOSEL Register Multipurpose Input/Output Selection Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 MPIO7 MPIO6 MPIO5 MPIO4 MPIO3 MPIO2 MPIO1 MPIO0 20 xr REV. 1.3.2 XR17C154 5V PCI BUS QUAD UART 2.0 CRYSTAL OSCILLATOR / BUFFER The 154 includes an on-chip oscillator (XTAL1 and XTAL2). The crystal oscillator provides the system clock to the Baud Rate Generators (BRG) in each of the 4 UARTs, the 16-bit general purpose timer/counter and internal logics. XTAL1 is the input to the oscillator or external clock buffer input with XTAL2 pin being the output. See Programmable Baud Rate Generator in the UART section for programming details. The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant with 10-22 pF capacitance load, 100ppm) connected externally between the XTAL1 and XTAL2 pins (see Figure 7). Alternatively, an external clock can be connected to the XTAL1 pin to clock the internal 4 baud rate generators for standard or custom rates. However, for external clock frequencies greater than 24MHz, a 2K pull-up may be necessary on the XTAL2 output (see Figure 8). Typical oscillator connections are shown in Figure 7. For further reading on oscillator circuit please see application note DAN108 on EXAR’s web site. FIGURE 7. TYPICAL OSCILLATOR CONNECTIONS R=300K to 400K XTAL1 14.7456 MHz XTAL2 C1 22-47pF C2 22-47pF FIGURE 8. EXTERNAL CLOCK CONNECTION FOR EXTENDED DATA RATE vcc gnd External Clock XTAL1 VCC R1 2K XTAL2 21 XR17C154 5V PCI BUS QUAD UART 3.0 TRANSMIT AND RECEIVE DATA xr REV. 1.3.2 There are two methods to load transmit data and unload receive data from each UART channel. First, there is a transmit data register and receive data register for each UART channel in the device configuration register set to ease programming. These registers support 8, 16, 24 and 32 bits wide format. In the 32-bit format, it increases the data transfer rate on the PCI bus. Additionally, a special register location provides receive data byte with its associated error flags. This is a 16-bit or 32-bit read operation where the Line Status Register (LSR) content in the UART channel register is paired along with the data byte. This operation further facilitates data unloading with the error flags without having to read the LSR register separately. Furthermore, the XR17C154 supports PCI burst mode for read/write operation of up to 64 bytes of data. The second method is through each UART channel’s transmit holding register (THR) and receive holding register (RHR). The THR and RHR registers are 16550 compatible so their access is limited to 8-bit format. The software driver must separately read the LSR content for the associated error flags before reading the data byte. 3.1 DATA LOADING AND UNLOADING VIA 32-BIT PCI BURST TRANSFERS The XR17C154 supports PCI Burst Read and PCI Burst Write transactions anywhere in the mapped memory region (except reserved areas). In addition, to utilize this feature fully, the device provides a separate memory location (apart from the 16550 register set) where the RX and the TX FIFO can be read from/written to, as shown in Table 2. The following is an extract from the table showing the burstable memory locations: Channel 0: RX FIFO TX FIFO RX FIFO + status Channel 1: RX FIFO TX FIFO RX FIFO + status Channel 2: RX FIFO TX FIFO RX FIFO + status Channel 3: RX FIFO TX FIFO RX FIFO + status 3.1.1 : : : 0x700 - 0x73F (64 bytes) 0x700 - 0x73F (64 bytes) 0x780 - 0x7FF (64 bytes data + 64 bytes status) : : : 0x500 - 0x53F (64 bytes) 0x500 - 0x53F (64 bytes) 0x580 - 0x5FF (64 bytes data + 64 bytes status) : : : 0x300 - 0x33F (64 bytes) 0x300 - 0x33F (64 bytes) 0x380 - 0x3FF (64 bytes data + 64 bytes status) : : : 0x100 - 0x13F (64 bytes) 0x100 - 0x13F (64 bytes) 0x180 - 0x1FF (64 bytes data + 64 bytes status) Normal Rx FIFO Data Unloading at locations 0x100, 0x300, 0x500, 0x700 The RX FIFO data (up to the maximum 64 bytes) can be read out in a single burst 32-bit read operation (maximum 16 DWORD reads) at memory locations 0x100 (channel 0), 0x300 (channel 1), 0x500 (channel 2), and 0x700 (channel 3). This operation is at least 16 times faster than reading the data in 64 separate 8-bit memory reads of RHR register (0x000 for channel 0, 0x200 for channel 1, 0x400 for channel 2, and 0x600 for channel 3). 22 xr REV. 1.3.2 XR17C154 5V PCI BUS QUAD UART READ RX FIFO, WITH NO ERRORS Read n+0 to n+3 Read n+4 to n+7 Etc. BYTE 3 FIFO Data n+3 FIFO Data n+7 BYTE 2 FIFO Data n+2 FIFO Data n+6 BYTE 1 FIFO Data n+1 FIFO Data n+5 BYTE 0 FIFO Data n+0 FIFO Data n+4 Channel 0 to 3 ReceiveData in 32-bit alignment through the Configuration Register Address 0x0100, 0x0300, 0x0500 and 0x0700 Receive Data Byte n+3 B7 B6 B5 B4 B3 B2 B1 B0 Receive Data Byte n+2 B7 B6 B5 B4 B3 B2 B1 B0 Receive Data Byte n+1 B7 B6 B5 B4 B3 B2 B1 B0 B7 Receive Data Byte n+0 B6 B5 B4 B3 B2 B1 B0 PCI Bus Data Bit-31 PCI Bus Data Bit-0 3.1.2 Special Rx FIFO Data Unloading at locations 0x180, 0x380, 0x580, and 0x780 The XR17C154 also provides the same RX FIFO data along with the LSR status information of each byte sideby-side, at locations 0x180 (channel 0), 0x380 (channel 1), 0x580 (channel 2), and 0x780 (channel 3). The entire RX data along with the status can be downloaded in a single PCI Burst Read operation of 32 DWORD reads. The Status and Data bytes must be read in 16 or 32 bits format to maintain data integrity. The following tables show this clearly. READ RX FIFO, ERRORS BYTE 3 FIFO Data n+1 FIFO Data n+3 BYTE 2 LSR n+1 LSR n+3 BYTE 1 FIFO Data n+0 FIFO Data n+2 BYTE 0 LSR n+0 LSR n+2 WITH LSR Read n+0 to n+1 Read n+2 to n+3 Etc Channel 0 to 1 Receive Data with Line Status Register in a 32-bit alignment through the Configuration Register Address 0x0180 and 0x0380 Receive Data Byte n+1 B7 B6 B5 B4 B3 B2 B1 B0 Line Status Register n+1 B7 B6 B5 B4 B3 B2 B1 B0 Receive Data Byte n+0 B7 B6 B5 B4 B3 B2 B1 B0 B7 Line Status Register n+0 B6 B5 B4 B3 B2 B1 B0 PCI Bus Data Bit-31 PCI Bus Data Bit-0 3.1.3 Tx FIFO Data Loading at locations 0x100, 0x300, 0x500, 0x700 The TX FIFO data (up to the maximum 64 bytes) can be loaded in a single burst 32-bit write operation (maximum 16 DWORD writes) at memory locations 0x100 (channel 0), 0x300 (channel 1), 0x500 (channel 2), and 0x700 (channel 3). 23 XR17C154 5V PCI BUS QUAD UART WRITE TX FIFO Write n+0 to n+3 Write n+4 to n+7 Etc. BYTE 3 FIFO Data n+3 FIFO Data n+7 BYTE 2 FIFO Data n+2 FIFO Data n+6 BYTE 1 FIFO Data n+1 FIFO Data n+5 xr REV. 1.3.2 BYTE 0 FIFO Data n+0 FIFO Data n+4 Channel 0 to 3 Transmit Data in 32-bit alignment through the Configuration Register Address 0x0100, 0x0300, 0x0500 and 0x0700 Transmit Data Byte n+3 B7 B6 B5 B4 B3 B2 B1 B0 Transmit Data Byte n+2 B7 B6 B5 B4 B3 B2 B1 B0 Transmit Data Byte n+1 B7 B6 B5 B4 B3 B2 B1 B0 Transmit Data Byte n+0 B7 B6 B5 B4 B3 B2 B1 B0 PCI Bus Data Bit-31 PCI Bus Data Bit-0 3.2 FIFO DATA LOADING AND UNLOADING THROUGH THE UART CHANNEL REGISTERS, THR AND RHR IN 8-BIT FORMAT The THR and RHR register address for channel 0 to channel 3 is shown in Table 8 below. The THR and RHR for each channel 0 to 3 are located sequentially at address 0x0000, 0x0200, 0x0400 and 0x0600. Transmit data byte is loaded to the THR when writing to that address and receive data is unloaded from the RHR register when reading that address. Both THR and RHR registers are 16C550 compatible in 8-bit format, so each bus operation can only write or read in bytes. TABLE 8: TRANSMIT AND RECEIVE DATA REGISTER IN BYTE FORMAT, 16C550 COMPATIBLE THR and RHR Address Locations For CH0 to CH3 (16C550 Compatible) CH0 0x000 Write THR CH0 0x000 Read RHR CH1 0x200 Write THR CH1 0x200 Read RHR CH2 0x400 Write THR CH2 0x400 Read RHR CH3 0x600 Write THR CH3 0x600 Read RHR Bit-7 Bit-7 Bit-7 Bit-7 Bit-7 Bit-7 Bit-7 Bit-7 Bit-6 Bit-6 Bit-6 Bit-6 Bit-6 Bit-6 Bit-6 Bit-6 Bit-5 Bit-5 Bit-5 Bit-5 Bit-5 Bit-5 Bit-5 Bit-5 Bit-4 Bit-4 Bit-4 Bit-4 Bit-4 Bit-4 Bit-4 Bit-4 Bit-3 Bit-3 Bit-3 Bit-3 Bit-3 Bit-3 Bit-3 Bit-3 Bit-2 Bit-2 Bit-2 Bit-2 Bit-2 Bit-2 Bit-2 Bit-2 Bit-1 Bit-1 Bit-1 Bit-1 Bit-1 Bit-1 Bit-1 Bit-1 Bit-0 Bit-0 Bit-0 Bit-0 Bit-0 Bit-0 Bit-0 Bit-0 784THRRHR1 24 xr REV. 1.3.2 XR17C154 5V PCI BUS QUAD UART 4.0 UART There are 4 UARTs [channel 3:0] in the 154. Each has its own 64-byte of transmit and receive FIFO, a set of 16550 compatible control and status registers, and a baud rate generator for individual channel data rate setting. Eight additional registers per UART were added for the EXAR enhanced features. 4.1 Programmable Baud Rate Generator Each UART has its own Baud Rate Generator (BRG) with a prescaler for the transmitter and receiver. The prescaler is controlled by a software bit in the MCR register. The MCR register bit-7 sets the prescaler to divide the input crystal or external clock by 1 or 4. The output of the prescaler clocks to the BRG. The BRG further divides this clock by a programmable divisor between 1 and (216 -1) to obtain a 16X or 8X sampling clock of the serial data rate. The sampling clock is used by the transmitter for data bit shifting and receiver for data sampling. The BRG divisor (DLL and DLM registers) defaults to a random value upon power up. Therefore, the BRG must be programmed during initialization to the operating data rate. FIGURE 9. BAUD RATE GENERATOR To Other Channels DLL and DLM Registers Prescaler Divide by 1 XTAL1 XTAL2 Crystal Osc/ Buffer Prescaler Divide by 4 MCR Bit-7=0 (default) Baud Rate Generator Logic MCR Bit-7=1 16X or 8X Sampling Rate Clock to Transmitter and Receiver Programming the Baud Rate Generator Registers DLM and DLL provides the capability for selecting the operating data rate. Table 9 shows the standard data rates available with a 14.7456 MHz crystal or external clock at 16X clock rate. At 8X sampling rate, these data rates would double. When using a non-standard data rate crystal or external clock, the divisor value can be calculated with the following equation(s). divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 16), WITH 8XMODE [7:0] IS 0 divisor (decimal) = (XTAL1 clock frequency / prescaler / (serial data rate x 8), WITH 8XMODE [7:0] IS 1 25 XR17C154 5V PCI BUS QUAD UART xr REV. 1.3.2 TABLE 9: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK AT 16X SAMPLING OUTPUT Data Rate OUTPUT Data Rate DIVISOR FOR 16x DIVISOR FOR 16x MCR Bit-7=1 MCR Bit-7=0 Clock (Decimal) Clock (HEX) 100 600 1200 2400 4800 9600 19.2k 38.4k 57.6k 115.2k 230.4k 400 2400 4800 9600 19.2k 38.4k 76.8k 153.6k 230.4k 460.8k 921.6k 2304 384 192 96 48 24 12 6 4 2 1 900 180 C0 60 30 18 0C 06 04 02 01 DLM PROGRAM VALUE (HEX) 09 01 00 00 00 00 00 00 00 00 00 DLL PROGRAM VALUE (HEX) 00 80 C0 60 30 18 0C 06 04 02 01 DATA RATE ERROR (%) 0 0 0 0 0 0 0 0 0 0 0 4.2 Transmitter The transmitter section comprises of a 64 bytes of FIFO, a byte-wide Transmit Holding Register (THR) and an 8-bit Transmit Shift Register (TSR). THR receives a data byte from the host (non-FIFO mode) or a data byte from the FIFO when the FIFO is enabled by FCR bit-0. TSR shifts out every data bit with the 16X or 8X internal clock. A bit time is 16 or 8 clock periods. The transmitter sends the start bit followed by the number of data bits, inserts the proper parity bit if enable, and adds the stop bit(s). The status of the THR and TSR are reported in the Line Status Register (LSR bit-5 and bit-6). 4.2.1 Transmit Holding Register (THR) - Write-Only The transmit holding register is an 8-bit register providing a data interface to the host processor. The host writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits, parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is also the input register to the transmit FIFO of 64 bytes when FIFO operation is enabled by FCR bit-0. A THR empty interrupt can be generated when it is enabled in IER bit-1. 4.2.2 Transmitter Operation in non-FIFO mode The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty. 26 xr REV. 1.3.2 XR17C154 5V PCI BUS QUAD UART FIGURE 10. TRANSMITTER OPERATION IN NON-FIFO MODE Data Byte Transmit Holding Register (THR) THR Interrupt (ISR bit-1) Enabled by IER bit-1 16X or 8X Clock (8XMODE Register) Transmit Shift Register (TSR) M S B L S B TXNOFIFO1 4.2.3 Transmitter Operation in FIFO mode The host may fill the transmit FIFO with up to 64 bytes of transmit data. The THR empty flag (LSR bit-5) is set whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the amount of data in the FIFO falls below its programmed trigger level (see TXTRG register). The transmit empty interrupt is enabled by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty. Furthermore, with the RS485 half-duplex direction control enabled (FCTR bit-5=1) the source of the transmit empty interrupt changes to TSR empty instead of THR empty. This is to ensure the RTS# output is not changed until the last stop bit of the last character is shifted out. 4.2.4 Auto RS485 Operation The auto RS485 half-duplex direction control changes the behavior of the transmitter when enabled by FCTR bit-5. While transmitting, the RTS# or DTR# signal is HIGH. The RTS# or DTR# signal changes from HIGH to LOW after a specified delay indicated in MSR[7:4] following the last stop bit of the last character that has been transmitted. This helps in turning around the transceiver to receive the remote station’s response. The delay optimizes the time needed for the last transmission to reach the farthest station on a long cable network before switching off the line driver. This delay prevents undesirable line signal disturbance that causes signal degradation. It also changes the transmitter empty interrupt to TSR empty instead of THR empty. FIGURE 11. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE Transmit Data Byte Transmit FIFO (64-Byte) Flow Control Characters (Xoff1/2 and Xon1/2 Reg. Auto Software Flow Control THR Interrupt (ISR bit-1) falls below Programmed Trigger Level (TXTRG) and then when becomes empty. FIFO is Enabled by FCR bit-0=1 16X or 8X Clock (8XMODE Register) Auto CTS Flow Control (CTS# pin) Transmit Data Shift Register (TSR) TXFIFO1 27 XR17C154 5V PCI BUS QUAD UART 4.3 Receiver xr REV. 1.3.2 The receiver section contains an 8-bit Receive Shift Register (RSR) and Receive Holding Register (RHR). The RSR uses the 16X or 8X clock for timing. It verifies and validates every bit on the incoming character in the middle of each data bit. On the falling edge of a start or false start bit, an internal receiver counter starts counting at the 16X or 8X clock rate. After 8 or 4 clocks the start bit period should be at the center of the start bit. At this time the start bit is sampled and if it is still a logic 0 it is validated. Evaluating the start bit in this manner prevents the receiver from assembling a false character. The rest of the data bits and stop bits are sampled and validated in this same manner to prevent false framing. If there were any error(s), they are reported in the LSR register bits 1-4. Upon unloading the receive data byte from RHR, the receive FIFO pointer is bumped and the error flags are immediately updated to reflect the status of the data byte in RHR register. RHR can generate a receive data ready interrupt upon receiving a character or delay until it reaches the FIFO trigger level. Furthermore, data delivery to the host is guaranteed by a receive data ready time-out function when receive data does not reach the receive FIFO trigger level. This time-out delay is 4 word lengths as defined by LCR[1:0] plus 12 bits time. The RHR interrupt is enabled by IER bit-0. 4.3.1 Receive Holding Register (RHR) - Read-Only The receive holding register is an 8-bit register that holds a receive data byte from the receive shift register (RSR). It provides the receive data interface to the host processor. The host reads the receive data byte on this register whenever a data byte is transferred from the RSR. RHR also part of the receive FIFO of 64 bytes by 11-bit wide, 3 extra bits are for the error flags to be in LSR register. When the FIFO is enabled by FCR bit-0, it acts as the first-out register of the FIFO as new data are put over the first-in register. The receive FIFO pointer is bumped after the RHR register is read. Also, the error flags associated with the data byte are immediately updated onto the line status register (LSR) bits 1-4. 4.3.2 Receiver Operation in non-FIFO Mode FIGURE 12. RECEIVER OPERATION IN NON-FIFO MODE 16X or 8X Clock (8XMODE Register) Receive Data Shift Register (RSR) Data Bit Validation Receive Data Characters Receive Data Byte and Errors Error Flags in LSR bits 4:2 Receive Data Holding Register (RHR) RHR Interrupt (ISR bit-2) RXFIFO1 28 xr REV. 1.3.2 XR17C154 5V PCI BUS QUAD UART 4.3.3 Receiver Operation with FIFO FIGURE 13. RECEIVER OPERATION IN FIFO AND FLOW CONTROL MODE 16X or 8X Sampling Clock (8XMODE Reg.) Receive Data Shift Register (RSR) Data Bit Validation Receive Data Characters 64 bytes by 11bit wide FIFO Example: - FIFO trigger level set at 48 bytes - RTS/DTR hyasteresis set at +/-8 chars. Data falls to 40 RTS#/DTR# re-asserts when data falls below Error Flags (64-sets) the trigger level to restart remote transmitter. Enable by EFR bit-6=1, MCR bit-2. RHR Interrupt (ISR bit-2) is programmed at FIFO trigger level (RXTRG). FIFO is Enable by FCR bit-0=1 Receive Data FIFO (64-byte) FIFO Trigger=48 Data fills to 56 Error Flags in LSR bits 4:2 RTS#/DTR# de-asserts when data fills above the trigger level to suspend remote transmitter. Enable by EFR bit-6=1, MCR bit-2. Receive Data Byte and Errors Receive Data RXFIFO1 4.4 Automatic Hardware (RTS/CTS or DTR/DSR) Flow Control Operation Automatic hardware RTS/CTS or DTR/DSR flow control is used to prevent data overrun to the local receiver FIFO and remote receiver FIFO. The RTS#/DTR# output pin is used to request the remote unit to suspend/ restart data transmission while the CTS#/DSR# input pin is monitored to suspend/restart the local transmitter. The auto RTS/CTS or DTR/DSR flow control features are individually selected to fit specific application requirement and enabled through EFR bit-6 and 7 and MCR bit-2 for either RTS/CTS or DTR/DSR control signals. TABLE 10: AUTO RTS/CTS OR DTR/DSR FLOW CONTROL SELECTION MCR BIT-2 0 0 1 1 X EFR BIT-7 1 X 1 X 0 EFR BIT-6 X 1 X 1 0 HARDWARE FLOW CONTROL SELECTION Auto CTS Flow Control Enabled Auto RTS Flow Control Enabled Auto DSR Flow Control Enabled Auto DTR Flow Control Enabled No Hardware Flow Control Auto RTS flow control must be started by asserting the RTS# output pin LOW (MCR bit-1 = 1). Similarly, Auto DTR flow control must be started by asserting the DTR# output pin LOW (MCR bit-0 = 1). Figure 14 shows in detail how automatic hardware flow control works. 29 XR17C154 5V PCI BUS QUAD UART xr REV. 1.3.2 Two interrupts associated with auto RTS/CTS and DTR/DSR flow control have been added to give indication when RTS#/DTR# pin or CTS#/DSR# pin are de-asserted during operation. These interrupts are enabled by: • Setting EFR bit-4 =1 to enable the shaded register bits • Setting IER bit-7 will enable the CTS#/DSR# interrupt when these pins are de-asserted. The selection of CTS# or DSR# is selected via MCR bit-2. See Table 10 above for complete details. • Setting IER bit-6 will enable the RTS#/DTR# interrupt when these pins are de-asserted. The selection of RTS# or DTR# is selected via MCR bit-2. See Table 10 above for complete details. Automatic hardware flow control is selected by setting bits 6 (RTS) and 7 (CTS) of the EFR register to logic 1. If CTS# pin transitions from LOW to HIGH indicating a flow control request, ISR bit-5 will be set to logic 1, (if enabled via IER bit 6-7), and the UART will suspend TX transmissions as soon as the stop bit of the character in process is shifted out. Transmission is resumed after the CTS# input returns LOW, indicating more data may be sent. FIGURE 14. AUTO RTS/DTR AND CTS/DSR FLOW CONTROL OPERATION Local UART UARTA Receiver FIFO Trigger Reached Auto RTS Trigger Level Transmitter Auto CTS Monitor RXA TXB Remote UART UARTB Transmitter Auto CTS Monitor Receiver FIFO Trigger Reached Auto RTS Trigger Level RTSA# TXA CTSB# RXB CTSA# Assert RTS# to Begin Transmission 1 ON 2 7 ON 3 8 OFF RTSB# RTSA# CTSB# TXB OFF 10 11 ON ON Data Starts 4 RXA FIFO INTA (RXA FIFO Interrupt) Receive RX FIFO Data Trigger Level 5 6 Suspend Restart 9 RTS High Threshold RTS Low Threshold 12 RX FIFO Trigger Level RTSCTS1 The local UART (UARTA) starts data transfer by asserting -RTSA# (1). RTSA# is normally connected to CTSB# (2) of remote UART (UARTB). CTSB# allows its transmitter to send data (3). TXB data arrives and fills UARTA receive FIFO (4). When RXA data fills up to its receive FIFO trigger level, UARTA activates its RXA data ready interrupt (5) and continues to receive and put data into its FIFO. If interrupt service latency is long and data is not being unloaded, UARTA monitors its receive data fill level to match the upper threshold of RTS delay and de-assert RTSA# (6). CTSB# follows (7) and request UARTB transmitter to suspend data transfer. UARTB stops or finishes sending the data bits in its transmit shift register (8). When receive FIFO data in UARTA is unloaded to match the lower threshold of RTS delay (9), UARTA re-asserts RTSA# (10), CTSB# recognizes the change (11) and restarts its transmitter and data flow again until next receive FIFO trigger (12). This same event applies to the reverse direction when UARTA sends data to UARTB with RTSB# and CTSA# controlling the data flow. 30 xr REV. 1.3.2 XR17C154 5V PCI BUS QUAD UART 4.5 Infrared Mode Each UART in the 154 includes the infrared encoder and decoder compatible to the IrDA (Infrared Data Association) version 1.0. The input pin ENIR conveniently activates all 8 UART channels to start up in the infrared mode. The ENIR pin is sampled when the RST# input is de-asserted. This global control pin enables the MCR bit-6 function in every UART channel register. After power up or a reset, the software can overwrite MCR bit-6 if so desired. ENIR and MCR bit-6 also disable its receiver while the transmitter is sending data. This prevents the echoed data from going to the receiver. The global activation ENIR pin prevents the infrared emitter from turning on and drawing large amount of current while the system is starting up. When the infrared feature is enabled, the transmit data outputs, TX[3:0], would idle LOW. Likewise, the RX [3:0] inputs assume an idling condition when it is LOW. The infrared encoder sends out a 3/16 of a bit wide pulse for each “0” bit in the transmit data stream. This signal encoding reduces the on-time of the infrared LED, hence reduces the power consumption. See Figure 15 below. The infrared decoder receives the input pulse from the infrared sensing diode on RX pin. Each time the decoder senses a light pulse, it returns a logic zero to the data bit stream. The RX input signal may be inverted prior delivered to the input of the decoder via internal register setting. This option supports active low instead of normal active high pulse from some infrared modules on the market. FIGURE 15. INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING Character Start Stop 1 1 0 1 1/2 Bit Time 3/16 Bit Time IrEncoder-1 Data Bits 1 0 1 0 0 TX Data 0 Transmit IR Pulse (TX Pin) Bit Time Receive IR Pulse (RX pin) Bit Time 1/16 Clock Delay RX Data 0 Start 1 0 1 0 0 11 0 1 Stop IRdecoder- Data Bits Character 31 XR17C154 5V PCI BUS QUAD UART 4.6 Internal Loopback xr REV. 1.3.2 Each UART channel provides an internal loopback capability for system diagnostic. The internal loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally. Figure 16 shows how the modem port signals are re-configured. Transmit data from the transmit shift register output is internally routed to the receive shift register input allowing the system to receive the same data that it was sending. The TX, RTS# and DTR# pins are held HIGH (idle or de-asserted state), and the CTS#, DSR# CD# and RI# inputs are ignored. FIGURE 16. INTERNAL LOOP BACK VCC Transmit Shift Register MCR bit-4=1 TX [3:0] Internal Bus Lines and Control Signals Receive Shift Register VCC RX [3:0] RTS# [3:0] Modem / General Purpose Control Logic RTS# CTS# VCC DTR# CTS# [3:0] DTR# [3:0] DSR# OP1# RI# OP2# CD# DSR# [3:0] RI# [3:0] CD# [3:0] 4.7 UART CHANNEL CONFIGURATION REGISTERS AND ADDRESS DECODING The 4 sets of UART configuration registers are decoded using address lines A8 to A11 as show below. Address lines A0 to A3 select the 16 registers in each channel. The first 8 registers are 16550 compatible with EXAR enhanced feature registers located on the upper 8 addresses. A11 0 0 0 0 A10 0 0 1 1 A9 0 1 0 1 A8 0 0 0 0 UART CHANNEL SELECTION 0 1 2 3 32 xr REV. 1.3.2 XR17C154 5V PCI BUS QUAD UART TABLE 11: UART CHANNEL CONFIGURATION REGISTERS . ADDRESS A3 A2 A1 A0 REGISTER READ/WRITE COMMENTS 16550 COMPATIBLE REGISTERS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 1 0 0 1 1 1 0 0 0 1 1 0 0 1 0 1 0 0 1 RHR - Receive Holding Register THR - Transmit Holding Register DLL - Div Latch Low DLM - Div Latch High IER - Interrupt Enable Register ISR - Interrupt Status Register FCR - FIFO Control Register LCR - Line Control Register MCR - Modem Control Register LSR - Line Status Register MSR - Modem Status Register RS485 Turn-Around Delay Register SPR - Scratch Pad Register ENHANCED REGISTERS 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 0 0 1 1 1 1 0 0 0 1 1 0 1 0 0 1 1 0 0 1 0 1 FCTR - Feature Control Register EFR - Enhanced Function Register TXCNT - Transmit FIFO Level Counter TXTRG - Transmit FIFO Trigger Level RXCNT - Receive FIFO Level Counter RXTRG - Receive FIFO Trigger Level Xoff-1 - Xoff Character 1 Xchar Xoff-2 - Xoff Character 2 Xon-1 - Xon Character 1 Xon-2 - Xon Character 2 Read/Write Read/Write Read-only Write-only Read-only Write-only Write-only Read-only Write-only Write-only Write-only Xon,Xoff Rcvd. Flags Read-only Write-only Read/Write Read/Write Read/Write Read-only Write-only Read/Write Read/Write Read-only Read-only Write-only Read/Write LCR[7] = 0 LCR[7] = 0 LCR[7] = 1 LCR[7] = 1 LCR[7] = 0 33 XR17C154 5V PCI BUS QUAD UART xr REV. 1.3.2 TABLE 12: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED BY EFR BIT-4. ADDRESS A3-A0 0000 0000 0000 0001 0001 REG NAME RHR THR DLL DLM IER READ/ WRITE R W R/W R/W R/W BIT-7 Bit-7 Bit-7 Bit-7 Bit-7 0/ BIT-6 Bit-6 Bit-6 Bit-6 Bit-6 0/ BIT-5 Bit-5 Bit-5 Bit-5 Bit-5 0/ BIT-4 Bit-4 Bit-4 Bit-4 Bit-4 0 BIT-3 Bit-3 Bit-3 Bit-3 Bit-3 BIT-2 Bit-2 Bit-2 Bit-2 Bit-2 BIT-1 Bit-1 Bit-1 Bit-1 Bit-1 BIT-0 Bit-0 Bit-0 Bit-0 Bit-0 RX Data Int. Enable COMMENT LCR[7]=0 LCR[7]=0 LCR[7]=1 LCR[7]=1 CTS/ RTS/ Xon/Xoff/ DSR# Int. DTR# Int. Sp. Char. Enable Enable Int. Enable 0010 ISR R FIFOs Enable FIFOs Enable 0/ 0/ Modem RX Line TX Empty Status Int. Status Int. Int. Enable Enable Enable DeltaXoff/special char Flow Cntl 0/ TX FIFO Trigger 0/ TX FIFO Trigger INT Source Bit-3 DMA Mode INT Source Bit-2 TX FIFO Reset INT Source Bit-1 RX FIFO Reset INT Source Bit-0 FIFOs Enable 0010 FCR W RX FIFO Trigger RX FIFO Trigger 0011 LCR R/W Divisor Enable Set TX Break Set Parity Even Parity Parity Enable Stop Bits Word Length Bit-1 Word Length Bit-0 0100 MCR R/W 0/ BRG Prescaler 0/ IR Enable TSR Empty RI 0/ XonAny Internal Lopback Enable (OP2)1 (OP1)1 RTS/DTR Flow Sel RTS# Pin DTR# Pin Control Control 0101 0110 LSR MSR R/W R RX FIFO ERROR CD THR Empty DSR RX Break CTS RX Fram- RX Parity RX OverError ing Error run Delta CD# Delta RI# Delta DSR# RX Data Ready Delta CTS# MSR 0111 1000 SPR FCTR W R/W R/W RS485 DLY-3 Bit-7 TRG Table Bit-1 RS485 DLY-2 Bit-6 TRG Table Bit-0 RS485 DLY-1 Bit-5 Auto RS485 Enable Special Char Select RS485 DLY-0 Bit-4 Invert IR RX Input Reserved Reserved Reserved Reserved Bit-3 Bit-2 Bit-1 Bit-0 User Data RTS/DTR RTS/DTR RTS/DTR RTS/DTR Hyst Bit-3 Hyst Bit-2 Hyst Bit-1 Hyst Bit-0 1001 EFR R/W Auto Auto CTS/DSR RTS/DTR Enable Enable Enable IER [7:5], ISR [5:4], FCR[5:4], MCR[7:5,2] MSR[7:4] Software Software Software Software Flow Cntl Flow Cntl Flow Cntl Flow Cntl Bit-3 Bit-2 Bit-1 Bit-0 1010 1010 1011 1011 TXCNT TXTRG RXCNT RXTRG R W R W Bit-7 Bit-7 Bit-7 Bit-7 Bit-6 Bit-6 Bit-6 Bit-6 Bit-5 Bit-5 Bit-5 Bit-5 Bit-4 Bit-4 Bit-4 Bit-4 Bit-3 Bit-3 Bit-3 Bit-3 Bit-2 Bit-2 Bit-2 Bit-2 Bit-1 Bit-1 Bit-1 Bit-1 Bit-0 Bit-0 Bit-0 Bit-0 34 xr REV. 1.3.2 ADDRESS A3-A0 1100 1100 1101 1110 1111 REG NAME XCHAR XOFF1 XOFF2 XON1 XON2 READ/ WRITE R W W W W XR17C154 5V PCI BUS QUAD UART TABLE 12: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED BY EFR BIT-4. BIT-7 0 Bit-7 Bit-7 Bit-7 Bit-7 BIT-6 0 Bit-6 Bit-6 Bit-6 Bit-6 BIT-5 0 Bit-5 Bit-5 Bit-5 Bit-5 BIT-4 0 Bit-4 Bit-4 Bit-4 Bit-4 BIT-3 0 Bit-3 Bit-3 Bit-3 Bit-3 BIT-2 0 Bit-2 Bit-2 Bit-2 Bit-2 BIT-1 Xon Det. Indicator Bit-1 Bit-1 Bit-1 Bit-1 BIT-0 Xoff Det. Indicator Bit-0 Bit-0 Bit-0 Bit-0 COMMENT Self-clear after read NOTE: MCR bits 2 and 3 (OP1 and OP2 outputs) are not available in the XR17C154. They are present for 16C550 compatibility during Internal loopback, see Figure 16. 4.8 4.8.1 4.8.2 4.8.3 Registers Receive Holding Register (RHR) - Read-Only Transmit Holding Register (THR) - Write-Only Baud Rate Generator Divisors (DLL and DLM) - Read/Write See “Section 4.3, Receiver” on page 28 for complete details. See “Section 4.2, Transmitter” on page 26 for complete details. The Baud Rate Generator (BRG) is a 16-bit counter that generates the data rate for the transmitter and receiver. The baud rate is programmed through registers DLL and DLM which are only accessible when LCR bit-7 is set to logic 1. See “Section 4.1, Programmable Baud Rate Generator” on page 25 for more detail. 4.8.4 Interrupt Enable Register (IER) - Read/Write The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR) register and also encoded in INT (INT0-INT3) register in the Device Configuration Registers. IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION When the receive FIFO (FCR bit-0 = a logic 1) and receive interrupts (IER BIT-0 = logic 1) are enabled, the RHR interrupts (see ISR bits 3 and 4) status will reflect the following: A. The receive data available interrupts are issued to the host when the FIFO has reached the programmed trigger level. It will be cleared when the FIFO drops below the programmed trigger level. B. FIFO level will be reflected in the ISR register when the FIFO trigger level is reached. Both the ISR register status bit and the interrupt will be cleared when the FIFO drops below the trigger level. C. The receive data ready bit (LSR BIT-0) is set as soon as a character is transferred from the shift register to the receive FIFO. It is reset when the FIFO is empty. IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION When FCR BIT-0 equals a logic 1 for FIFO enable, resetting IER bits 0-3 enables the 158 in the FIFO polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). A. LSR BIT-0 indicates there is data in RHR or RX FIFO. B. LSR BIT-1 indicates an overrun error has occurred and that data in the FIFO may not be valid. C. LSR BITS 2-4 provides the type of receive data errors encountered for the data byte in RHR, if any. D. LSR BIT-5 indicates THR is empty. E. LSR BIT-6 indicates when both the transmit FIFO and TSR are empty. F. LSR BIT-7 indicates a data error in at least one character in the RX FIFO. 35 XR17C154 5V PCI BUS QUAD UART IER[0]: RHR Interrupt Enable xr REV. 1.3.2 The receive data ready interrupt will be issued when RHR has a data character in the non-FIFO mode or when the receive FIFO has reached the programmed trigger level in the FIFO mode. A receive data timeout interrupt will be issued in the FIFO mode when the receive FIFO has not reached the programmed trigger level and the RX input has been idle for 4 character + 12 bit times. • Logic 0 = Disable the receive data ready interrupt (default). • Logic 1 = Enable the receiver data ready interrupt. IER[1]: THR Interrupt Enable When Auto RS485 mode operation is disabled (FCTR bit-5 = 0), this interrupt is associated with bit-5 in the LSR register. An interrupt is issued whenever the THR becomes empty or when data in the FIFO falls below the programmed trigger level. When Auto RS485 mode operation is enabled (FCTR bit-5 = 1), this interrupt is associated with bit-6 in the LSR register. An interrupt is issued whenever the TX FIFO and the TSR becomes empty. • Logic 0 = Disable Transmit Holding Register empty interrupt (default). • Logic 1 = Enable Transmit Holding Register empty interrupt. IER[2]: Receive Line Status Interrupt Enable Any of LSR register bits 1, 2, 3 or 4 will generate an LSR interrupt immediately when a character received by the RX FIFO has an error. • Logic 0 = Disable the receiver line status interrupt (default). • Logic 1 = Enable the receiver line status interrupt. IER[3]: Modem Status Interrupt Enable • Logic 0 = Disable the modem status register interrupt (default). • Logic 1 = Enable the modem status register interrupt. IER[4]: Reserved IER[5]: Xoff Interrupt Enable (requires EFR bit-4=1) • Logic 0 = Disable the software flow control, receive Xoff interrupt (default). • Logic 1 = Enable the software flow control, receive Xoff interrupt. See Software Flow Control section for details. IER[6]: RTS#/DTR# Output Interrupt Enable (requires EFR bit-4=1) The RTS# or DTR# output is selected via MCR bit-2. See Table 10 or MCR[2] for complete details. • Logic 0 = Disable the RTS#/DTR# interrupt (default). • Logic 1 = Enable the RTS#/DTR# interrupt. The UART issues an interrupt when the RTS#/DTR# pin makes a transition. IER[7]: CTS# Input Interrupt Enable (requires EFR bit-4=1) The CTS# or DSR# input is selected via MCR bit-2. See Table 10 or MCR[2] for complete details. • Logic 0 = Disable the CTS#/DSR# interrupt (default). • Logic 1 = Enable the CTS#/DSR# interrupt. The UART issues an interrupt when CTS# pin makes a transition. 4.8.5 Interrupt Status Register (ISR) - Read-Only The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the ISR will give the user the current highest pending interrupt level to be serviced with others queued up for next service. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt Source Table, Table 13, shows the data values (bit 0-5) for the six prioritized interrupt levels and the interrupt sources associated with each of these interrupt levels. 36 xr REV. 1.3.2 XR17C154 5V PCI BUS QUAD UART Interrupt Generation: • LSR is by any of the LSR bits 1, 2, 3 and 4. • RXRDY is by RX trigger level. • RXRDY Time-out is by the a 4-char plus 12 bits delay timer if the RX FIFO level is less than the RX trigger level. • TXRDY is by LSR bit-5 (or bit-6 in auto RS485 control). • MSR is by any of the MSR bits, 0, 1, 2 and 3. • Receive Xon/Xoff/Special character is by detection of a Xon, Xoff or Special character. • CTS#/DSR# is by a change of state on the input pin (from LOW to HIGH) with auto flow control enabled, EFR bit-7, and depending on selection of MCR bit-2. • RTS#/DTR# is when its receiver changes the state of the output pin (from LOW to HIGH) during auto RTS/ DTR flow control enabled by EFR bit-6 and selection of MCR bit-2. • Wake-up Indicator: when the UART comes out of sleep mode. Interrupt Clearing: • LSR interrupt is cleared by a read to the LSR register. • RXRDY is cleared by reading data until FIFO falls below the trigger level. • RXRDY Time-out is cleared by reading data until the RX FIFO is empty. • TXRDY interrupt is cleared by a read to the ISR register. • MSR interrupt is cleared by a read to the MSR register. • Xon or Xoff character interrupt is cleared by a read to ISR register. • Special character interrupt is cleared by a read to ISR register or after the next character is received. • RTS#/DTR# and CTS#/DSR# status change interrupts are cleared by a read to the MSR register. • Wake-up Indicator is cleared by a read to the INT0 register. ] TABLE 13: INTERRUPT SOURCE AND PRIORITY LEVEL PRIORITY LEVEL 1 2 3 4 5 6 7 X BIT-5 0 0 0 0 0 0 1 0 ISR REGISTER STATUS BITS BIT-4 0 0 0 0 0 1 0 0 BIT-3 0 0 1 0 0 0 0 0 BIT-2 1 1 1 0 0 0 0 0 BIT-1 1 0 0 1 0 0 0 0 BIT-0 0 0 0 0 0 0 0 1 LSR (Receiver Line Status Register) RXRDY (Received Data Ready) RXRDY (Receive Data Time-out) TXRDY (Transmitter Holding Register Empty) MSR (Modem Status Register) RXRDY (Received Xon/Xoff or Special character) CTS#/DSR#, RTS#/DTR# change of state None (default) SOURCE OF THE INTERRUPT ISR[0]: Interrupt Status • Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt service routine. • Logic 1 = No interrupt pending (default condition). ISR[3:1]: Interrupt Status These bits indicate the source for a pending interrupt at interrupt priority levels 1, 2, 3 and 4 (See Interrupt Source Table 13). 37 XR17C154 5V PCI BUS QUAD UART ISR[4]: Xoff/Xon or Special Character Interrupt Status xr REV. 1.3.2 This bit is enabled when EFR bit-4 is set to a logic 1. ISR bit-4 indicates that the receiver detected a data match of the Xoff character(s). If this is an Xoff/Xon interrupt, it can be cleared by a read to the ISR. Reading the XCHAR register will indicate which character (Xoff or Xon) was received last. If it is a special character interrupt, it can be cleared by reading ISR or it will automatically clear after the next character is received. ISR[5]: RTS#/CTS# Interrupt Status This bit is enabled when EFR bit-4 is set to a logic 1. ISR bit-5 indicates that the CTS# or RTS# has changed state from LOW to HIGH. ISR[7:6]: FIFO Enable Status These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are enabled. 4.8.6 FIFO Control Register (FCR) - Write-Only This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and select the DMA mode (legacy term that refers to "block transfer mode"). The DMA and FIFO modes are defined as follows: FCR[0]: TX and RX FIFO Enable • Logic 0 = Disable the transmit and receive FIFO (default). • Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are written or they will not be programmed. FCR[1]: RX FIFO Reset This bit is only active when FCR bit-0 is active. • Logic 0 = No receive FIFO reset (default). • Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not cleared or altered). This bit will return to a logic 0 after resetting the FIFO. FCR[2]: TX FIFO Reset This bit is only active when FCR bit-0 is active. • Logic 0 = No transmit FIFO reset (default). • Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not cleared or altered). This bit will return to a logic 0 after resetting the FIFO. FCR[3]: DMA Mode Select This bit has no effect since TXRDY and RXRDY pins are not available in this device. It is provided for legacy software. DMA is a legacy term used for block transfer mode. DMA does not stand for "Direct Memory Access." • Logic 0 = Set DMA to mode 0 (default). • Logic 1 = Set DMA to mode 1. FCR[5:4]: Transmit FIFO Trigger Select (logic 0 = default, TX trigger level = 1) The FCTR bits 6-7 are associated with these 2 bits by selecting one of the four tables. The 4 user selectable trigger levels in 4 tables are supported for compatibility reasons. These 2 bits set the trigger level for the transmit FIFO interrupt. The UART will issue a transmit interrupt when the number of characters in the FIFO falls below the selected trigger level, or when it gets empty in case that the FIFO did not get filled over the trigger level on last re-load. Table 14 below shows the selections. EFR bit-4 must be set to ‘1’ before these bits can be accessed. Note that the receiver and the transmitter cannot use different trigger tables. Whichever selection is made last applies to both the RX and TX side. 38 xr REV. 1.3.2 XR17C154 5V PCI BUS QUAD UART FCR[7:6]: Receive FIFO Trigger Select (logic 0 = default, RX trigger level =1) The FCTR Bits 6-7 are associated with these 2 bits. These 2 bits are used to set the trigger level for the receiver FIFO interrupt. Table 14 shows the complete selections. Note that the receiver and the transmitter cannot use different trigger tables. Whichever selection is made last applies to both the RX and TX side. TABLE 14: TRANSMIT AND RECEIVE FIFO TRIGGER LEVEL SELECTION TRIGGER TABLE Table A FCTR BIT-7 0 FCTR BIT-6 0 0 0 1 1 Table B 0 1 0 1 0 1 0 0 1 1 0 0 1 1 Table C 1 0 0 1 0 1 0 0 1 1 0 0 1 1 Table D 1 1 X 0 1 0 1 X X X 0 1 0 1 8 16 56 60 Programmable Programmable 16C850, 16C2850, 16C2852, 16C854, 16C864, 16L2750, 16L2751, 16L2752 compatible. 0 1 0 1 8 16 24 28 8 16 32 56 16C654 compatible. FCR BIT-7 FCR BIT-6 FCR BIT-5 0 FCR BIT-4 0 1 (default) 4 8 14 16 8 24 30 RECEIVE TRIGGER LEVEL TRANSMIT TRIGGER LEVEL 1 (default) COMPATIBILITY 16C550, 16C2550, 16C2552, 16C554, 16C580 compatible. 16C650A compatible. 39 XR17C154 5V PCI BUS QUAD UART 4.8.7 Line Control Register (LCR) - Read/Write xr REV. 1.3.2 The Line Control Register is used to specify the asynchronous data communication format. The word or character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. LCR[1:0]: TX and RX Word Length Select These two bits specify the word length to be transmitted or received. BIT-1 0 0 1 1 BIT-0 0 1 0 1 WORD LENGTH 5 (default) 6 7 8 LCR[2]: TX and RX Stop-bit Length Select The length of stop bit is specified by this bit in conjunction with the programmed word length. BIT-2 0 1 1 WORD LENGTH STOP BIT LENGTH (BIT TIME(S)) 1 (default) 1-1/2 2 5,6,7,8 5 6,7,8 LCR[3]: TX and RX Parity Select Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data integrity check. See Table 15 for parity selection summary below. • Logic 0 = No parity. • Logic 1 = A parity bit is generated during the transmission while the receiver checks for parity error of the data character received. LCR[4]: TX and RX Parity Select If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR BIT-4 selects the even or odd parity format. • Logic 0 = ODD Parity is generated by forcing an odd number of logic 1’s in the transmitted character. The receiver must be programmed to check the same format (default). • Logic 1 = EVEN Parity is generated by forcing an even the number of logic 1’s in the transmitted character. The receiver must be programmed to check the same format. LCR[5]: TX and RX Parity Select If the parity bit is enabled, LCR BIT-5 selects the forced parity format. • LCR BIT-5 = logic 0, parity is not forced (default). • LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit is forced to a logical 1 for the transmit and receive data. • LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit is forced to a logical 0 for the transmit and receive data. 40 xr REV. 1.3.2 XR17C154 5V PCI BUS QUAD UART TABLE 15: PARITY SELECTION LCR BIT-5 LCR BIT-4 LCR BIT-3 X 0 0 1 1 X 0 1 0 1 0 1 1 1 1 PARITY SELECTION No parity Odd parity Even parity Force parity to mark, “1” Forced parity to space, “0” LCR[6]: Transmit Break Enable When enabled the Break control bit causes a break condition to be transmitted (the TX output is forced to a “space", LOW state). This condition remains until disabled by setting LCR bit-6 to a logic 0. • Logic 0 = No TX break condition (default). • Logic 1 = Forces the transmitter output (TX) to a “space”, LOW, for alerting the remote receiver of a line break condition. LCR[7]: Baud Rate Divisors Enable Baud rate generator divisor (DLL/DLM) enable. • Logic 0 = Data registers are selected (default). • Logic 1 = Divisor latch registers are selected. 4.8.8 Modem Control Register (MCR) - Read/Write The MCR register is used for controlling the modem interface signals or general purpose inputs/outputs. MCR[0]: DTR# Pins The DTR# pin may be used for automatic hardware flow control enabled by EFR bit-6 and MCR bit-2=1. If the modem interface is not used, this output may be used for general purpose. • Logic 0 = Force DTR# output HIGH (default). • Logic 1 = Force DTR# output LOW. MCR[1]: RTS# Pins The RTS# pin may be used for automatic hardware flow control by enabled by EFR bit-6 and MCR bit-2=0. If the modem interface is not used, this output may be used for general purpose. • Logic 0 = Force RTS# output HIGH (default). • Logic 1 = Force RTS# output LOW. MCR[2]: DTR# or RTS# for Auto Flow Control DTR# or RTS# auto hardware flow control select. This bit is in effect only when auto RTS/DTR is enabled by EFR bit-6. DTR# selection is associated with DSR# and RTS# is with CTS#. • Logic 0 = Uses RTS# and CTS# pins for auto hardware flow control. • Logic 1 = Uses DTR# and DSR# pins for auto hardware flow control. MCR[3]: (OP2) The OP2 output is not available in the XR17C154. It is present for 16C550 compatibility during internal loopback. See Figure 16. Logic 0 is default. MCR[4]: Internal Loopback Enable • Logic 0 = Disable internal loopback mode (default). • Logic 1 = Enable internal loopback mode, see loopback section and Figure 16. 41 XR17C154 5V PCI BUS QUAD UART MCR[5]: Xon-Any Enable xr REV. 1.3.2 • Logic 0 = Disable Xon-Any function (for 16C550 compatibility) (default). • Logic 1 = Enable Xon-Any function. In this mode any RX character received will enable Xon, resume data transmission. MCR[6]: Infrared Encoder/Decoder Enable The state of this bit depends on the sampled logic level of pin ENIR during power up, following a hardware reset or a soft-reset. Afterward user can override this bit for desired operation. • Logic 0 = Disable the infrared mode, operates in the normal serial character mode. • Logic 1 = Enable infrared IrDA receive and transmit inputs/outputs. While in this mode, the TX/RX output/ input are routed to the infrared encoder/decoder. The data input and output levels will conform to the IrDA infrared interface requirement. As such, while in this mode the infrared TX output will be a logic 0 during idle data conditions. FCTR bit-4 may be selected to invert the RX input signal level going to the decoder for infrared modules that provide rather an inverted output. MCR[7]: Clock Prescaler Select • Logic 0 = Divide by one. The input clock from the crystal or external clock is fed directly to the Programmable Baud Rate Generator without further modification, i.e., divide by one (default). • Logic 1 = Divide by four. The prescaler divides the input clock from the crystal or external clock by four and feeds it to the Programmable Baud Rate Generator, hence, data rates become one-fourth. 4.8.9 Line Status Register (LSR) - Read/Only This register provides the status of data transfers between the UART and the host. If IER bit-2 is set to a logic 1, an LSR interrupt will be generated immediately when any character in the RX FIFO has an error (parity, framing, overrun, break). Reading LSR will clear LSR bits 4-1. LSR[0]: Receive Data Ready Indicator • Logic 0 = No data in receive holding register or FIFO (default). • Logic 1 = Data has been received and is saved in the receive holding register or FIFO. LSR[1]: Receiver Overrun Flag • Logic 0 = No overrun error (default). • Logic 1 = Overrun error. A data overrun error condition occurred in the receive shift register. This happens when additional data arrives while the FIFO is full. In this case the previous data in the receive shift register is overwritten. Note that under this condition the data byte in the receive shift register is not transferred into the FIFO, therefore the data in the FIFO is not corrupted by the error. This bit is cleared after LSR is read. LSR[2]: Receive Data Parity Error Tag • Logic 0 = No parity error (default). • Logic 1 = Parity error. The receive character in RHR does not have correct parity information and is suspect. This error is associated with the character available for reading in RHR. This bit is cleared after LSR is read. LSR[3]: Receive Data Framing Error Tag • Logic 0 = No framing error (default). • Logic 1 = Framing error. The receive character did not have a valid stop bit(s). This error is associated with the character available for reading in RHR. This bit is cleared after LSR is read. LSR[4]: Receive Break Tag • Logic 0 = No break condition (default). • Logic 1 = The receiver received a break signal (RX was a logic 0 for one character frame time). In the FIFO mode, only one break character is loaded into the FIFO. This bit is cleared after LSR is read. 42 xr REV. 1.3.2 XR17C154 5V PCI BUS QUAD UART LSR[5]: Transmit Holding Register Empty Flag This bit is the Transmit Holding Register Empty indicator. This bit indicates that the transmitter is ready to accept a new character for transmission. In addition, this bit causes the UART to issue an interrupt to the host when the THR interrupt enable is set. The THR bit is set to a logic 1 when the last data byte is transferred from the transmit holding register to the transmit shift register. The bit is reset to logic 0 concurrently with the data loading to the transmit holding register by the host. In the FIFO mode this bit is set when the transmit FIFO is empty; it is cleared when at least 1 byte is written to the transmit FIFO. LSR[6]: Transmit Shift Register Empty Flag This bit is the Transmit Shift Register Empty indicator. This bit is set to a logic 1 whenever the transmitter goes idle. It is set to logic 0 whenever either the THR or TSR contains a data character. In the FIFO mode this bit is set to one whenever the transmit FIFO and transmit shift register are both empty. LSR[7]: Receive FIFO Data Error Flag • Logic 0 = No FIFO error (default). • Logic 1 = An indicator for the sum of all error bits in the RX FIFO. At least one parity error, framing error or break indication is in the FIFO data. This bit clears when there is no more error(s) in the FIFO. 4.8.10 Modem Status Register (MSR) - Read-Only This register provides the current state of the modem interface signals, or other peripheral device that the UART is connected. Lower four bits of this register are used to indicate the changed information. These bits are set to a logic 1 whenever a signal from the modem changes state. These bits may be used as general purpose inputs/outputs when they are not used with modem signals. MSR[0]: Delta CTS# Input Flag • Logic 0 = No change on CTS# input (default). • Logic 1 = The CTS# input has changed state since the last time it was monitored. A modem status interrupt will be generated if MSR interrupt is enabled (IER bit-3. MSR[1]: Delta DSR# Input Flag • Logic 0 = No change on DSR# input (default). • Logic 1 = The DSR# input has changed state since the last time it was monitored. A modem status interrupt will be generated if MSR interrupt is enabled (IER bit-3). MSR[2]: Delta RI# Input Flag • Logic 0 = No change on RI# input (default). • Logic 1 = The RI# input has changed from a logic 0 to a logic 1, ending of the ringing signal. A modem status interrupt will be generated if MSR interrupt is enabled (IER bit-3). MSR[3]: Delta CD# Input Flag • Logic 0 = No change on CD# input (default). • Logic 1 = Indicates that the CD# input has changed state since the last time it was monitored. A modem status interrupt will be generated if MSR interrupt is enabled (IER bit-3). MSR[4]: CTS Input Status CTS# pin may function as automatic hardware flow control signal input if it is enabled and selected by Auto CTS (EFR bit-7) and RTS/CTS flow control select (MCR bit-2). Auto CTS flow control allows starting and stopping of local data transmissions based on the modem CTS# signal. A logic 1 on the CTS# pin will stop UART transmitter as soon as the current character has finished transmission, and a logic 0 will resume data transmission. If automatic hardware flow control is not used, MSR bit-4 bit is the compliment of the CTS# input. However in the loopback mode, this bit is equivalent to the RTS# bit in the MCR register. The CTS# input may be used as a general purpose input when the modem interface is not used. 43 XR17C154 5V PCI BUS QUAD UART MSR[5]: DSR Input Status xr REV. 1.3.2 This input may be used for auto DTR/DSR flow control function, see “Section 4.4, Automatic Hardware (RTS/CTS or DTR/DSR) Flow Control Operation” on page 29 for complete details. If automatic hardware flow control is not used, this bit is the compliment of the DSR# input. In the loopback mode, this bit is equivalent to the DTR# bit in the MCR register. The DSR# input may be used as a general purpose input when the modem interface is not used. MSR[6]: RI Input Status This bit is the compliment of the RI# input. In the loopback mode this bit is equivalent to bit-2 in the MCR register. The RI# input may be used as a general purpose input when the modem interface is not used. MSR[7]: CD Input Status This bit is the compliment of the CD# input. In the loopback mode this bit is equivalent to bit-3 in the MCR register. The CD# input may be used as a general purpose input 4.8.11 Modem Status Register (MSR) - Write-Only The upper four bits 4-7 of this register sets the delay in number of bits time for the auto RS485 turn around from transmit to receive. MSR [7:4] When Auto RS485 feature is enabled (FCTR bit-5=1) and RTS# output is connected to the enable input of a RS-485 transceiver. These 4 bits select from 0 to 15 bit-time delay after the end of the last stop-bit of the last transmitted character. This delay controls when to change the state of RTS# output. This delay is very useful in long-cable networks. Table 16 shows the selection. The bits are enabled by EFR bit-4. TABLE 16: AUTO RS485 HALF-DUPLEX DIRECTION CONTROL DELAY FROM TRANSMIT-TO-RECEIVE MSR[7] 0 0 0 0 0 9 0 0 1 1 1 1 1 1 1 1 MSR[6] 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 MSR[5] 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 MSR[4] 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 DELAY IN DATA BIT(S) TIME 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 44 xr REV. 1.3.2 XR17C154 5V PCI BUS QUAD UART 4.8.12 SCRATCH PAD REGISTER (SPR) - Read/Write This is an 8-bit general purpose register for the user to store temporary data. The content of this register is preserved during sleep mode but becomes 0xFF (default) after a reset or a power off-on cycle. 4.8.13 FEATURE CONTROL REGISTER (FCTR) - Read/Write FCTR [3:0] - Auto RTS/DTR Flow Control Hysteresis Select These bits select the auto RTS/DTR flow control hysteresis and only valid when TX and RX Trigger Table-D is selected (FCTR bit-6 and 7 are set to logic 1). The RTS/DTR hysteresis is referenced to the RX FIFO trigger level. After reset, these bits are set to logic 0 selecting the next FIFO trigger level for hardware flow control. Table 17 shows the 16 selectable hysteresis levels. FCTR[4]: Infrared RX Input Logic Select • Logic 0 = Select RX input as active high encoded IrDA data, normal, (default). • Logic 1 = Select RX input as active low encoded IrDA data, inverted. FCTR[5]: Auto RS485 Enable Auto RS485 half duplex control enable/disable. • Logic 0 = Standard ST16C550 mode. Transmitter generates an interrupt when transmit holding register (THR) becomes empty. Transmit Shift Register (TSR) may still be shifting data bit out. • Logic 1 = Enable Auto RS485 half duplex direction control. RTS# output changes its logic level from HIGH to LOW when finished sending the last stop bit of the last character out of the TSR register. It changes back to HIGH from LOW when a data byte is loaded into the THR or transmit FIFO. The change to HIGH occurs prior sending the start-bit. It also changes the transmitter interrupt from transmit holding to transmit shift register (TSR) empty. FCTR[7:6]: TX and RX FIFO Trigger Table Select These 2 bits select the transmit and receive FIFO trigger level table A, B, C or D. When table A, B, or C is selected the auto RTS flow control trigger level is set to "next FIFO trigger level" for compatibility to ST16C550 and ST16C650 series. RTS#/DTR# triggers on the next level of the RX FIFO trigger level, in another word, one FIFO level above and one FIFO level below. See Table 14 for complete selection with FCR bit 4-5 and FCTR bit 6-7, i.e. if Table C is used on the receiver with RX FIFO trigger level set to 56 bytes, RTS/DTR# output will de-assert at 60 and re-assert at 16. 45 XR17C154 5V PCI BUS QUAD UART xr REV. 1.3.2 TABLE 17: 16 SELECTABLE HYSTERESIS LEVELS WHEN TRIGGER TABLE-D IS SELECTED FCTR BIT-3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FCTR BIT-2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 FCTR BIT-1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FCTR BIT-0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 RTS/DTR HYSTERESIS (CHARACTERS) 0 ±4 ±6 ±8 ±8 ± 16 ± 24 ± 32 ± 12 ± 20 ± 28 ± 36 ± 40 ± 44 ± 48 ± 52 4.8.14 Enhanced Feature Register (EFR) - Read/Write Enhanced features are enabled or disabled using this register. Bits 0-3 provide single or dual consecutive character software flow control selection (see Table 18). When the Xon1 and Xon2 and Xoff1 and Xoff2 modes are selected, the double 8-bit words are concatenated into two sequential characters. Caution: note that whenever changing the TX or RX flow control bits, always reset all bits back to logic 0 (disable) before programming a new setting. EFR[3:0]: Software Flow Control Select Combinations of software flow control can be selected by programming these bits. See Table 18 for complete selections. The XOFF1/XOFF2 characters are transmitted approximately 2 character times after the RX FIFO level has reached the RX trigger level, irrespective of which trigger table is used (Trigger Tables A-D). The XON1/XON2 characters are transmitted when the RX FIFO level falls below the next lower trigger level for Trigger Tables A-C and they are transmitted when the RX FIFO level falls below the (RX trigger level hysteresis level) for Trigger Table D. For example, if Trigger Table D is used with an RX trigger level of 56 and a hysteresis level of 16, the XON1/XON2 characters are sent when the RX FIFO level count falls below 40. 46 xr REV. 1.3.2 XR17C154 5V PCI BUS QUAD UART EFR[4]: Enhanced Function Bits Enable Enhanced function control bit. This bit enables the functions in IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR bits 5-7 to be modified. After modifying any enhanced bits, EFR bit-4 can be set to a logic 0 to latch the new values. This feature prevents legacy software from altering or overwriting the enhanced functions once set. Normally, it is recommended to leave it enabled, logic 1. • Logic 0 = modification disable/latch enhanced features. IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR bits 5-7 are saved to retain the user settings. After a reset, the IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR bits 5-7 are set to a logic 0 to be compatible with the industry standard 16550 (default). • Logic 1 = Enables the enhanced functions. When this bit is set to a logic 1 all enhanced features are enabled. EFR[5]: Special Character Detect Enable • Logic 0 = Special Character Detect Disabled (default). • Logic 1 = Special Character Detect Enabled. The UART compares each incoming receive character with data in Xoff-2 register. If a match exists, the received data will be transferred to FIFO and ISR bit-4 will be set to indicate detection of the special character. Bit-0 corresponds with the LSB bit for the receive character. If flow control is set for comparing Xon1, Xoff1 (EFR [1:0]=’10’) then flow control and special character work normally. However, if flow control is set for comparing Xon2, Xoff2 (EFR[1:0]=’01’) then flow control works normally, but Xoff2 will not go to the FIFO, and will generate an Xoff interrupt and a special character interrupt. TABLE 18: SOFTWARE FLOW CONTROL FUNCTIONS TX S/W FLOW CONTROL EFR BIT-3 CONT-3 0 0 1 1 X X X 0 1 0 1 EFR BIT-2 CONT-2 0 1 0 1 X X X 1 0 0 1 RX S/W FLOW CONTROL EFR BIT-1 CONT-1 X X X X 0 0 1 1 1 1 1 EFR BIT-0 CONT-0 X X X X 0 1 0 1 1 1 1 SOFTWARE FLOW CONTROL FUNCTIONS No transmit flow control Transmit Xon2, Xoff2 Transmit Xon1, Xoff1 Transmit Xon1 and Xon2, Xoff1 and Xoff2 No receive flow control Receiver compares Xon2, Xoff2 Receiver compares Xon1, Xoff1 Transmit Xon2, Xoff2 Receiver compares Xon1 or Xon2, Xoff1 or Xoff2 Transmit Xon1, Xoff1 Receiver compares Xon1 or Xon2, Xoff1 or Xoff2 No transmit flow control Receiver compares Xon1 and Xon2, Xoff1 and Xoff2 Transmit Xon1 and Xon2, Xoff1 and Xoff2 Receiver compares Xon1 and Xon2, Xoff1 and Xoff2 47 XR17C154 5V PCI BUS QUAD UART EFR[6]: Auto RTS or DTR Flow Control Enable xr REV. 1.3.2 RTS#/DTR# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS/ DTR is selected, an interrupt will be generated when the receive FIFO is filled to the programmed trigger level and RTS#/DTR# will de-assert HIGH at the next upper trigger or selected hysteresis level. RTS#/DTR# will return LOW when FIFO data falls below the next lower trigger or selected hysteresis level (see FCTR bits 4-7). The RTS# or DTR# output must be asserted (LOW) before the auto RTS/DTR can take effect. The selection for RTS# or DTR# is through MCR bit-2. RTS/DTR# pin will function as a general purpose output when hardware flow control is disabled. • Logic 0 = Automatic RTS/DTR flow control is disabled (default). • Logic 1 = Enable Automatic RTS/DTR flow control. EFR[7]: Auto CTS Flow Control Enable Automatic CTS or DSR Flow Control. • Logic 0 = Automatic CTS/DSR flow control is disabled (default). • Logic 1 = Enable Automatic CTS/DSR flow control. Transmission stops when CTS#/DSR# pin de-asserts HIGH. Transmission resumes when CTS/DSR# pin returns LOW. The selection for CTS# or DSR# is through MCR bit-2. 4.8.15 TXCNT[7:0]: Transmit FIFO Level Counter - Read-Only Transmit FIFO level byte count from 0x00 (zero) to 0x40 (64). This 8-bit register gives an indication of the number of characters in the transmit FIFO. The FIFO level Byte count register is read only. The user can take advantage of the FIFO level byte counter for faster data loading to the transmit FIFO, which reduces CPU bandwidth requirements. Please see the Application Note DAN119 on Exar’s website for a detailed discussion of FIFO level counters. Due to the dynamic nature of the FIFO counters, this register should be read until the same value is returned twice. 4.8.16 TXTRG [7:0]: Transmit FIFO Trigger Level - Write-Only An 8-bit value written to this register sets the TX FIFO trigger level from 0x00 (zero) to 0x40 (64). The TX FIFO trigger level generates an interrupt whenever the data level in the transmit FIFO falls below this preset trigger level. 4.8.17 RXCNT[7:0]: Receive FIFO Level Counter - Read-Only Receive FIFO level byte count from 0x00 (zero) to 0x40 (64). It gives an indication of the number of characters in the receive FIFO. The FIFO level byte count register is read only. The user can take advantage of the FIFO level byte counter for faster data unloading from the receiver FIFO, which reduces CPU bandwidth requirements. Please see the Application Note DAN119 on Exar’s website for a detailed discussion of FIFO level counters. Due to the dynamic nature of the FIFO counters, this register should be read until the same value is returned twice. 4.8.18 RXTRG[7:0]: Receive FIFO Trigger Level - Write-Only An 8-bit value written to this register, sets the RX FIFO trigger level from 0x00 (zero) to 0x40 (64). The RX FIFO trigger level generates an interrupt whenever the receive FIFO level rises to this preset trigger level. 48 xr REV. 1.3.2 XR17C154 5V PCI BUS QUAD UART TABLE 19: UART RESET CONDITIONS REGISTERS DLL DLM RHR THR IER FCR ISR LCR MCR LSR MSR SPR FCTR EFR TXCNT TXTRG RXCNT RXTRG XCHAR XON1 XON2 XOFF1 XOFF2 I/O SIGNALS TX[ch-3:0] RTS#[ch-3:0] DTR#[ch-3:0] EECK EECS EEDI Bits 7-0 = 0xXX Bits 7-0 = 0xXX Bits 7-0 = 0xXX Bits 7-0 = 0xXX Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x01 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x60 Bits 3-0 = logic 0 Bits 7-4 = logic levels of the inputs Bits 7-0 = 0xFF Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x00 RESET STATE HIGH (if ENIR pin = LOW) LOW (if ENIR pin = HIGH) HIGH HIGH LOW LOW LOW RESET STATE 49 XR17C154 5V PCI BUS QUAD UART 5.0 PROGRAMMING EXAMPLES 5.1 UNLOADING RECEIVE DATA USING THE SPECIAL RECEIVE FIFO DATA WITH STATUS xr REV. 1.3.2 It is suggested that before starting to read the Special Receive FIFO Data with Status to unload data from any UART channel (address 0x180 for channel 0), do a dummy read to the Device ID (DVID) register in the Configuration Register of the device. The Special Receive FIFO Data with Status register can then be read multiple times subsequently without any byte-swapping problem as long as no other register (except the Device ID register) is accessed in between data unload. If you must read or write to another register, make that dummy read to the DVID register again and continue with data unloading. A step by step procedure describing the sequence for a target channel is shown below. From the receive data service routine: • Do a dummy read to Device ID (DVID) register. Address 0x8D in BYTE alignment or address 0x8C in DWORD alignment. • Read the data byte and its associated error status from ‘Special Receive FIFO Data with Status’ register of the target channel until done or empty when one of the LSR status byte bit-0=0. NOTE: If you must do other Read/Write operations to other register(s) during data unloading, repeat steps 1 & 2 to continue unloading data plus status from the ‘Special Receive FIFO Data with Status’ register of the target channel. Some Examples of using the Special Receive FIFO Data with Status: EXAMPLE I: POLLING ..................... Read LSR Read DVID Read Special Receive FIFO Data with Status (address 0x180 for channel 0, etc) Read Special Receive FIFO Data with Status (address 0x180 for channel 0, etc)* Read Special Receive FIFO Data with Status (address 0x180 for channel 0, etc) .................... EXAMPLE 2: INTERRUPT SERVICE USING INTERRUPT INFORMATION IN DEVICE CONFIGURATION REGISTER SET ..................... Read Global Interrupt Register INT0 (address 0x080) Read INT1 through INT3 registers to identify interrupting channel (address 0x081 through 0x083) Read DVID Read Special Receive FIFO Data with Status (address 0x180 for channel 0, etc) Read Special Receive FIFO Data with Status (address 0x180 for channel 0, etc)* Read Special Receive FIFO Data with Status (address 0x180 for channel 0, etc) ................ EXAMPLE 3: INTERRUPT SERVICE USING INTERRUPT INFORMATION IN INDIVIDUAL CHANNEL’S REGISTERS ................ Read Global Interrupt Register INT0 (address 0x080) Read ISR register of interrupting channel Read DVID Read Special Receive FIFO Data with Status (address 0x180 for channel 0, etc) Read Special Receive FIFO Data with Status (address 0x180 for channel 0, etc)* Read Special Receive FIFO Data with Status (address 0x180 for channel 0, etc) ................ * In case some other registers need to be accessed in between ‘Special Receive FIFO Data with Status’ reads, a ‘Read DVID’ instruction has to be inserted before resuming ‘Special Receive FIFO Data with Status’ read operation. 50 xr REV. 1.3.2 XR17C154 5V PCI BUS QUAD UART ABSOLUTE MAXIMUM RATINGS Power Supply Range Voltage at Any Pin Operating Temperature Storage Temperature Package Dissipation Thermal Resistance (20x20x1.4mm 144-LQFP) 7 Volts -0.5 to 7V -40o to +85o C -65o to +150o C 500 mW theta-ja = 42, theta-jc = 8 ELECTRICAL CHARACTERISTICS DC ELECTRICAL CHARACTERISTICS FOR 5V SIGNALING TA=0o to 70oC (-40o to +85oC for industrial grade package). VCC = 4.5 - 5.5V. SYMBOL VIL VIH VOL VOH IIL IIH ICL CIN CCLK CIDSEL ICC PARAMETER Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input Low Leakage Current Input High Leakage Current Input Clock Leakage Input Pin Capacitance CLK Pin Capacitance IDSEL Pin Capacitance Power Supply Current 5 2.4 -10 10 ±10 10 12 8 3 MIN -0.5 2.0 MAX 0.8 6.0 0.55 UNITS V V V V uA uA uA pF pF pF mA PCI Bus CLK and Ext. Clock = 2MHz, all inputs at VCC or GND and all outputs are unloaded. All four UARTs asleep. AD[31:0] at GND, all inputs at VCC or GND. Iout=6 mA Iout=-2 mA CONDITION NOTES ISLEEP Sleep Current 20 uA 51 XR17C154 5V PCI BUS QUAD UART AC ELECTRICAL CHARACTERISTICS FOR 5V SIGNALING TA=0o to 70oC (-40o to +85oC for industrial grade package). VCC = 4.5 - 5.5V. SYMBOL XTAL1 ECLK IOH(AC) IOL(AC) SlewR SlewF TCYC THI TLO PARAMETER UART Crystal Oscillator External Clock Switching Current High Switching Current Low Output Rise Slew Rate Output Fall Slew Rate CLK Cycle Time CLK High Time CLK Low Time CLK Slew Rate TVAL TON TOFF TSETUP THOLD CLK to Signal Valid Delay Float to Active Delay Active to Float Delay Input Setup Time to CLK bused signals Input Hold Time from CLK 7 0 -44 95 1 1 30 11 11 1 2 2 28 4 11 4 4 MIN MAX 24 50 UNITS MHz MHz mA mA V/ns V/ns ns ns ns V/ns ns ns ns ns ns xr REV. 1.3.2 NOTES 0