XR18910
8:1 Sensor Interface Analog Front End
Description
FEATURES
■■ Integrated features for interfacing multiple
bridge sensors with an MCU or FPGA
8:1 differential MUX with I2C interface
Instrumentation amplifier
LDO
Offset correction DAC with I2C interface
(±560mV offset correction range)
■■ Eight selectable voltage gains from 2V/V
to 760V/V with only ±0.5% gain error
■■ 3mV maximum input offset voltage
■■ 100pA maximum input bias current
■■ 559μA maximum supply current
■■ 2.7V to 5V analog supply voltage range
■■ 1.8V to 5V digital supply voltage range
■■ -40°C to 85°C temperature range
■■ 3.5mm x 3.5mm TQFN-24 package
The XR18910 is a unique sensor interface integrated circuit with an
onboard 8:1 multiplexer, offset correction Digital-to-Analog Converter
(DAC), instrumentation amplifier and voltage reference. The XR18910
is designed to integrate multiple bridge sensors with a Microcontroller
(MCU) or Field-Programmable Gate Array (FPGA).
The integrated offset correction DAC provides digital calibration of the
variable and in many cases substantial offset voltage generated by the
bridge sensors. The DAC is controlled by an I2C compatible 2-wire serial
interface. The serial interface also provides the user with easy controls
to the XR18910’s many functions such as input and gain selection.
A linear regulator (LDO) provides a regulated voltage to power the input
bridge sensors and is selectable, between 3V and 2.65V. The LDO
current can be sensed and a proportional voltage present at the output
of the IC for monitoring the LDO current.
The XR18910 offers 8 fixed gain settings (from 2V/V to 760V/V), each
with an error of only ±0.5%, that are selectable via the I2C interface.
It also offers less than 3mV maximum input offset voltage, 100pA
maximum input bias current, and 100pA maximum input offset current.
APPLICATIONS
■■ Bridge sensor interface
■■ Pressure and temperature sensors
■■ Strain gauge amplifier
■■ Industrial process controls
■■ Weigh scales
The XR18910 is designed to operate from 2.7V to 5V supplies, specified
over the industrial temperature range of -40°C to 85°C and is offered in
a space saving 3.5mm x 3.5mm TQFN package. It consumes less than
559μA supply current and offers a sleep mode for added power savings.
The XR18910 is well suited for industrial and consumer applications
using bridge sensors.
Typical Application
VDD
VCC
6.8μF
6.8μF
+
+
BRDG
2.5
0.1μF
0.1μF
VCC
2
VDD
1.5
0.1μF
BRIDGE 8
IN8-
INA /
PGA
8:1
MUX
BRIDGE 1
10k
ADC
µC
10nF
±560mV
OFFSET TRIM
VDD
10-BIT
DAC
PGA
IN1+
IN1-
OUT
4.7k
VDD
1
0.5
0
-0.5
-1
-1.5
-2
4.7k
SDA
-2.5
I2C
CONTROL
RTI Noise (µV)
LDO
IN8+
SCL
0
2
4
6
Time (seconds)
8
10
XR18910
AGND
DGND
Figure 1. Typical Application
Figure 2. 0.1Hz to 10Hz RTI Voltage Noise
Rev1C
1/20
XR18910
Absolute Maximum Ratings
Operating Conditions
Stresses beyond the limits listed below may cause
permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect
device reliability and lifetime.
Analog supply voltage range..................................... 2.7V to 5.25V
Analog supply voltage (VCC)........................................... 0V to 5.5V
Digital supply voltage (VDD)............................................ 0V to 5.5V
Digital input/output (VDDIO)............................................. 0V to 5.5V
VIN......................................................................................0 to VCC
Differential input voltage (current limit of 10mA)....................... VCC
Digital supply voltage range........................................1.7V to 5.25V
Operating temperature range....................................-40°C to 85°C
Junction temperature............................................................. 150°C
Storage temperature range......................................-65°C to 150°C
Lead temperature (soldering, 10s).........................................260°C
Package thermal resistance θJA.......................................50°C/W(1)
NOTE:
1. JEDEC standard, multi-layer test boards, still air.
ESD rating (HBM - human body model)....................................4kV
Rev1C
2/20
XR18910
Electrical Characteristics
TA = 25°C, VCC = 3.3V, VDD = 1.8V, RL = 10kΩ to 1.5V, G = 760, unless otherwise noted.
Symbol
Parameter
Conditions
Min
Typ
Max
Input referred
-3
±0.02
3
Units
DC Performance
VIO
Input offset voltage
dVIO
Input offset voltage average drift
IB
Input bias current
IOS
Input offset current
PSRR
Power supply rejection ratio
G
GE
3
15
100
pA
-100
1
100
pA
60
91
dB
Gain = 2
2.0
V/V
Gain = 20
20.0
V/V
Gain = 40
40.0
V/V
Gain = 80
80.0
V/V
150.0
V/V
Gain = 300
299.9
V/V
Gain = 600
599.6
V/V
Gain = 760
759.4
V/V
Gain = 150
-100
mV
μV/°C
VCC = 2.7V to 5V
Nominal, refer to Gain Register Table (pg. 8)
Gain error
-0.5
Gain error vs temperature
0.5
±10
%
ppm/°C
ISVCC
VCC supply current
No load to output, no load to LDO
435
530
μA
ISVCCD
Disable VCC supply current
No load to output, no load to LDO
48
62
μA
ISVDD
VDD supply current
No load to output, no load to LDO, I2C running
22
29
μA
ISTOTAL
Total supply current
No load to output, no load to LDO
457
559
μA
ISDTOTAL
Total disable supply current
No load to output, no load to LDO, LDO DIS
45
No load to output, no load to LDO, LDO EN
70
μA
91
μA
Input Characteristics
Input impedance
CMIR
Common mode input range
CMRR
Common mode rejection ratio
Ω || pF
1013 || 11.2
0.5
0.23 to
3.06
Input referred, VCM = 0.5 to 2.0V
75
88
2.5
V
dB
Output Characteristics
VOUT
Output voltage swing
RL = 10kΩ to 1.5V
0.1
0.04 to
3.29
3.1
V
VOO
Output offset
Offset DAC 0 00 0000 0000, G = 2
1.4
1.5
1.6
V
Offset DAC
Offset DAC range
RTI (referred to input)
Offset monotonicity
±560
8
mV
10
Bits
LDO
Output voltage
Dropout voltage
1.5k load, LDO bit LOW
-6%
3
+6%
V
1.5k load, LDO bit HIGH
-6%
2.65
+6%
V
150
mV
VCC = 2.8V, LDO = 2.65V, ILOAD = 10mA
Output current
Power supply rejection ratio
10
25
mA
Output referred, VCC = 3V to 5V, LDO = 2.65V
45
63
dB
Output referred, VCC = 3.3V to 5V, LDO = 3V
45
63
dB
0.08
0.1
Output current sense transimpedance
slope
Output voltage relative to 1.5V / LDO current, G = 2
Output current sense range clip
G=2
18.8
Rev1C
0.12
V/mA
mA
3/20
XR18910
Electrical Characteristics (Continued)
TA = 25°C, VCC = 3.3V, VDD = 1.8V, RL = 10kΩ to 1.5V, G = 760, unless otherwise noted.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Dynamic Performance
BW
-3dB bandwidth
SR
Slew rate
eNI
Input voltage noise, RTI
G = 760
66
kHz
1300
kHz
VOUT = 1VP-P, G = 2
1
V/μs
f = 10Hz
75
nV/√Hz
f = 100Hz
46
nV/√Hz
f = 1kHz
35
nV/√Hz
G=2
iN
Input current noise
f = 10Hz
0.6
fA/√Hz
eNP-P
Peak-to-peak noise
f = 0.1 to 10Hz
2
μVP-P
XTALK
Crosstalk
Channel-to-channel, f = 1kHz
90
dB
TS
Set-up time, 1% settling
Analog ready after serial register finished write
3.5
μs
TWAKE
Wake up time, 1% settling
Wake from ACK of SLEEP_OUT command
9.6
μs
Digital Characteristics (CMOS)
Max
Units
VIH
Symbol
Logic input HIGH
Parameter
Conditions
0.7 x VDD
Min
Typ
VDD
V
VIL
Logic input LOW
0
0.3 x VDD
V
IIH
Input leakage HIGH
VI = VS
10
μA
IIL
Input leakage LOW
VI = 0
CLKF
Clock rate
0.4
MHz
-10
μA
I2C Bus Timing
TA = -40 to 85°C, VDD = 1.8 to 5V, unless otherwise noted.
Symbol
Parameter
Standard Mode
I2C-BUS
Fast Mode
I2C-BUS
Min
Max
Min
Max
0
100
0
400
Units
fSCL
Operating frequency
TBUF
Bus free time between STOP and
START
4.7
1.3
μs
THD;STA
START condition hold time
4.0
0.6
μs
TSU;STA
START condition setup time
4.7
0.6
μs
THD;DAT
Data hold time
0
0
μs
TVD;ACK
Data valid acknowledge
TVD;DAT
SCL LOW to data out valid
TSU;DAT
Data setup time
250
150
ns
TLOW
Clock LOW period
4.7
1.3
μs
THIGH
Clock HIGH period
4.0
TF
Clock/data fall time
300
300
ns
TR
Clock/data rise time
1000
300
ns
TSP
Pulse width of spikes tolerance
0.6
0.6
0.6
μs
0.6
ns
0.6
0.5
0.5
Rev1C
kHz
μs
μs
4/20
XR20M1280
XR18910
I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL
SHIFTERS
REV. 1.0.0
Electrical Characteristics (Continued)
FIGURE 22. I2C-BUS TIMING DIAGRAM
START
condition
(S)
Protocol
T SU;STA
Bit 7
MSB
(A7)
T LOW
Bit 0
LSB
(R/W)
Bit 6
(A6)
T HIGH
Acknowledge
(A)
STOP
condition
(P)
1/F SCL
SCL
TF
TR
T BUF
T SP
SDA
T HD;STA
T SU;DAT
T HD;DAT
T VD;DAT
T VD;ACK
T SU;STO
Figure 3. I2C Bus Timing Diagram
FIGURE 23. WRITE TO OUTPUT
SDA
SLAVE
ADDRESS
W
A
GPIOLVL REG.
A
DATA
A
T D1
GPIOn
Rev1C
5/20
XR18910
Electrical Characteristics (Continued)
Table 1. Register List
Reg No.
R/ W/
C
Byte of
Parameter
No operation
C
0
N/A
Does not execute a function. NOP
is used to test successful I2C
communication
SW_RESET
Software reset
C
0
N/A
Resets all registers to default values
Name
Hex
Dec
0x00
0
NOP
1
Function
Parameter
Default
Code
Power-up
Condition
Remark
Reset
0x01
Read ID
0x02
2
DEVICE_ID
Read Device ID
R
2
[15:0]: report “8910” in
BCD
0x03
3
VERSION_ID
Read HW & SW
version numbers
R
2
[15:12]: reserved
[11:8]: Hardware version #
[7:0]: Software version #
SLEEP_OUT
_REG
Normal operating
mode, system
active
C
0
Instructs the XR18910 to report its
device ID 8910 in binary form
(1000 1001 0001 0000)
0x8910
N/A
Initial H/W version number is ‘0’;
Initial S/W version number is ‘01’.
Sleep in/out
0x04
0x05
4
5
SLEEP_IN
_REG
Sleep Mode
C
0
Gain
Gain select
R/W
1
Active
Puts the XR18910 into active
mode. (wake up)
N/A
Active
Puts the analog portion of the XR18910
into sleep mode.
During sleep mode, the only I2C
command that can be received/
processed is the SLEEP_OUT
command (0x04). All other register
addresses will be ignored.
0x00
Gain
=2
Eight gain settings are selectable (from
2V/V to 760V/V), refer to the Gain
Register Table for more information.
LDO
= 3V
Bit 0 controls the LDO voltage (0: 3V;
1: 2.65V).
Bit 1 (Sleep Mode only). Bit 1 controls
whether the LDO shuts down or stays
on during Sleep Mode. (0: Enable; 1:
Disable). When the XR18910 is active, the
LDO is always on.
Off
When on, the LDO current is sensed and
a proportional voltage is present at the
output of the XR18910.
Current Sense Mode remains active until
an input select command is received by the
XR18910.
N/A
Basic Config
0x06
6
[2:0]: Gain select
[0]:LDO 3V, 2.65V
0x07
0x08
7
8
LDO
LDO Current
Sense Select
LDO Settings
LDO Current Sense
R/W
1
C
0
[1]:LDO disable
0x00
N/A
Channel Switch (Input MUX Select)
0x10 16
Select_
Input_1
Select Channel 1
C
0
Select +IN1, -IN1; Channel 1
0x12 18
Select_
Input_2
Select Channel 2
C
0
Select +IN2, -IN2; Channel 2
0x14 20
Select_
Input_3
Select Channel 3
C
0
Select +IN3, -IN3; Channel 3
0x15 21
Select_
Input_4
Select Channel 4
C
0
0x18 24
Select_
Input_5
Select Channel 5
C
0
0x1A 26
Select_
Input_6
Select Channel 6
C
0
Select +IN6, -IN6; Channel 6
0x1C 28
Select_
Input_7
Select Channel 7
C
0
Select +IN7, -IN7; Channel 7
0x1E 30
Select_
Input_8
Select Channel 8
C
0
Select +IN8, -IN8; Channel 8
N/A
Rev1C
Channel
1 is
selected
Select +IN4, -IN4; Channel 4
Select +IN5, -IN5; Channel 5
6/20
XR18910
Reg No.
Hex
Dec
Name
Function
R/ W/
C
Byte of
Parameter
Parameter
Default
Code
Power-up
Condition
0x00
0mV
offset
Remark
Offset DAC Config
0x20 32
DAC1
Configures DAC
offset applied to
Channel 1
R/W
2
0x22 34
DAC2
Configures DAC
offset applied to
Channel 2
R/W
2
0x24 36
DAC3
Configures DAC
offset applied to
Channel 3
R/W
2
0x25 37
DAC4
Configures DAC
offset applied to
Channel 4
R/W
2
[10]: DAC Sign
[9:0]: DAC Range
0x28 40
DAC5
Configures DAC
offset applied to
Channel 5
R/W
2
0x2A 42
DAC6
Configures DAC
offset applied to
Channel 6
R/W
2
0x2C 44
DAC7
Configures DAC
offset applied to
Channel 7
R/W
2
0x2E 46
DAC8
Configures DAC
offset applied to
Channel 8
R/W
2
Bit 10 controls the sign of the DAC offset
voltage. Bits 9 thru 0 control the value
of the DAC offset voltage.
[10]: DAC Sign 0 = positive; 1 = negative
NOTE:
Register numbers not listed above have no function.
Table 2. DAC Registers
Hex
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Offset % of FS Input
Voltage RTI
0x3FF
0
1
1
1
1
1
1
1
1
1
1
50
560mV
0x000
0
0
0
0
0
0
0
0
0
0
0
0
0
0x7FF
1
1
1
1
1
1
1
1
1
1
1
-50
-560mV
0x400
1
0
0
0
0
0
0
0
0
0
0
0
0
DAC
Sign
10-Bit DAC Range
Table 3. Gain Registers
Hex
D2
D1
D0
Gain
0x00
0
0
0
2
0x01
0
0
1
20
0x02
0
1
0
40
0x03
0
1
1
80
0x04
1
0
0
150
0x05
1
0
1
300
0x06
1
1
0
600
0x07
1
1
1
760
Rev1C
7/20
XR18910
SDA
SCL
DGND
VCC
OUT
AGND
24
23
22
21
20
19
Pin Configuration
IN2+
4
15
IN7-
IN2-
5
14
IN7+
IN3+
6
13
IN6-
NOTE:
MaxLinear recommends grounding the exposed pad.
12
IN8+
IN6+
16
11
3
IN5-
IN1-
10
IN8-
IN5+
17
9
2
IN4-
IN1+
8
BRDG
IN4+
18
7
1
IN3-
VDD
Pin Functions
Pin Number
Pin Name
Description
1
VDD
Digital Supply
2
IN1+
Positive Input 1
3
IN1-
Negative Input 1
4
IN2+
Positive Input 2
5
IN2-
Negative Input 2
6
IN3+
Positive Input 3
7
IN3-
Negative Input 3
8
IN4+
Positive Input 4
9
IN4-
Negative Input 4
10
IN5+
Positive Input 5
11
IN5-
Negative Input 5
12
IN6+
Positive Input 6
13
IN6-
Negative Input 6
14
IN7+
Positive Input 7
15
IN7-
Negative Input 7
16
IN8+
Positive Input 8
17
IN8-
Negative Input 8
18
BRDG
BRDG Power Connection (LDO output)
19
AGND
Analog Ground
20
OUT
Output
21
VCC
Analog Supply
22
DGND
Digital Ground
23
SCL
Serial Clock Input
24
SDA
Serial Data Input/Output
Rev1C
8/20
XR18910
Typical Performance Characteristics
TA = 25°C, VCC = 3.3V, VDD = 1.8V, RL = 10kΩ to 1.5V, G = 760, unless otherwise noted.
2
3
G = 2, VOUT = 0.5VP-P
2.5
Output Voltage (V)
1.75
Output Voltage (V)
G = 2, VOUT = 2.5VP-P
1.5
1.25
2
1.5
1
0.5
1
0
10
20
30
0
40
0
10
20
Time (µs)
Figure 4. Small Signal Pulse Response at G = 2
40
Figure 5. Large Signal Pulse Response at G = 2
2
G = 300, VOUT = 2.5VP-P
3
G = 300, VOUT = 0.5VP-P
2.5
1.75
Output Voltage (V)
Output Voltage (V)
30
Time (µs)
1.5
1.25
2
1.5
1
0.5
1
0
20
40
60
80
0
100
0
20
40
Figure 6. Small Signal Pulse Response at G = 300
3
Normalized Gain (dB)
Normalized Gain (dB)
0
-3
VOUT = 0.5VP-P
VOUT = 1VP-P
-9
-12
VOUT = 2.5VP-P
1
10
100
Frequency (kHz)
1000
10000
G = 300
0
-3
-6
VOUT = 0.5VP-P
VOUT = 1VP-P
VOUT = 2.5VP-P
-9
-12
0.1
100
Figure 7. Large Signal Pulse Response at G = 300
G= 2
-6
80
Time (µs)
Time (µs)
3
60
0.1
1
10
100
1000
10000
Frequency (kHz)
Figure 8. Frequency Response at G = 2
Figure 9. Frequency Response at G = 300
Rev1C
9/20
XR18910
Typical Performance Characteristics (Continued)
TA = 25°C, VCC = 3.3V, VDD = 1.8V, RL = 10kΩ to 1.5V, G = 760, unless otherwise noted.
3.5
4
G= 2
Current Sense Mode Active
3
VLDO (V)
Output Voltage (V)
3
2.5
2
VCC = 3.3V
1.5
VCC = 5V
1
2
0
5
10
15
20
0
25
0
10
20
ILDO (mA)
Figure 10. LDO Current vs. Output Voltage
5
1.5
3
Output Voltage (V)
Output Voltage (V)
50
1.55
G= 2
2
1
0
-10
-5
0
5
1.45
G= 2
1.35
10
G = 300
1.4
G = 760
0.25
0.75
1.25
1.75
2.25
2.75
Input Common Mode Voltage (V)
Output Current (mA)
Figure 12. Output Offset Voltage vs. Output Current
Figure 13. Output Offset vs. Input Common Mode Voltage
2.5
100
90
2
G = 760
1.5
80
70
RTI Noise (µV)
Input Voltage Noise (nV/√Hz)
40
Figure 11. LDO Output Current
4
-1
30
ILDO (mA)
60
50
40
30
20
1
0.5
0
-0.5
-1
-1.5
10
-2
0
-2.5
0.01
0.1
1
10
100
1000
Frequency (kHz)
Figure 14. Input Voltage Noise vs. Frequency
0
2
4
6
Time (seconds)
8
10
Figure 15. 0.1Hz to 10Hz RTI Voltage Noise
Rev1C
10/20
XR18910
Typical Performance Characteristics (Continued)
TA = 25°C, VCC = 3.3V, VDD = 1.8V, RL = 10kΩ to 1.5V, G = 760, unless otherwise noted.
4
G= 2
Stop Time = 1% Settling
Output Voltage (V)
2
3.5
1.5
DUT Output
1
SDA
0.5
3
Output Voltage (V)
2.5
2.5
2
1
5
10
Start Time = 50% Acknowledge
0.5
Start Time = 50% Acknowledge
0
DUT Output
1.5
0
-0.5
Stop Time = 1% Settling
SDA
15
0
20
0
5
Time (µs)
Figure 16. Sleep to Wake Time (DUT Output)
3.5
3.5
3
Output Voltage (V)
Output Voltage (V)
SDA
2.5
2
1.5
LDO Output
1
Stop Time = 1% Settling
0.5
0
-0.5
50
100
150
20
2.5
LDO Output
Stop Time = 1% Settling
2
1.5
1
SDA
0.5
0
Start Time = 50% Acknowledge
0
15
Figure 17. Set-up Time - from G = 2 to G = 300
(DUT Output)
4
3
10
Time (µs)
200
-0.5
250
Time (µs)
Figure 18. LDO Enable to Disable Time
Start Time = 50% Acknowledge
0
10
20
30
Time (µs)
40
50
Figure 19. LDO Disable to Enable Time
Rev1C
11/20
XR18910
Functional Block Diagram
VCC
LDO Output
1.5V
Reference
LDO Enable
LDO Select ( 3V, 2.65V )
AGND
PGA
VDD
SDA
SCL
2:1 Differential MUX
LDO Select
Gain Select
LDO Enable
10-Bit Offset DAC
Power Down Analog
Offset -
Offset +
Output
DAC [0:9], Sign
Input [0:3]
Input 8 +/-
Current Sense Mode
Input 2 +/-
8:1 Differential MUX
Input 1 +/-
I2C Serial Digital Interface
DGND
Figure 20. Functional Block Diagram
Application Information
The XR18910 sensor interface includes a 8:1 differential
multiplexer (MUX), a programmable gain instrumentation
amplifier, a 10-bit offset correction DAC and an LDO. An
I2C interface controls the many functions and features of the
XR18910. The XR18910 is designed to integrate multiple
bridge sensors with an ADC/MCU or FPGA.
The XR18910 also provides the ability to monitor the LDO
current. When the XR18910 is in current sense mode, an
internal 2:1 MUX allows a voltage proportional to the LDO
current to be present at the output. Once all channels have
been calibrated, the LDO current can be used to indirectly
monitor any voltage or resistive changes seen by the inputs.
Each bridge sensor connected to the XR18910 has its
own inherent offset that if not calibrated out can decrease
sensitivity and overall performance of the sensor system. The
on-board DAC introduces an offset into the instrumentation
amplifier to calibrate the offset voltage generated by the
sensors. An independent offset can be set for each of the
8 channels. Only the offset voltage of the active channel is
applied to the PGA.
The XR18910 also includes an internal 1.5V reference that
is used by the internal LDO circuitry and used to set the
reference voltage for the programmable gain instrumentation
amplifier.
The programmable gain instrumentation amplifier offers 8
selectable gains from 2V/V to 760V/V to amplify the signal
such that it falls within the input range of the ADC.
An integrated LDO provides a regulated voltage to power
the input bridge sensors and is selectable, between 3V and
2.65V. The LDO can be set to turn off when the XR18910 is
in sleep mode to save power.
Rev1C
During sleep mode, the analog components of the XR18910
are powered down for added power savings.
The XR18910 offers many functions, each controlled by the
I2C compatible serial interface:
■■
■■
■■
■■
■■
■■
Input Selection
Gain Selection
Offset Correction
LDO Enable/Select
Current Sense Mode
Sleep Mode (analog power down)
12/20
XR18910
Application Information (Continued)
Power Up
After initial system power up, the I2C master must provide
one SCL clock pulse prior to the first I2C access (first start
condition). The first access to the XR18910 must be a
RESET command.
SDA
XR20M1280
REV. 1.0.0
I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
SCL
1.0 FUNCTIONAL DESCRIPTIONS
1.1
CPU Interface
2
The XR20M1280 can operate with either an I2C-bus interface or an SPI interface. The CPU interface is
selected via the I2C/SPI# input pin.
I2C-bus
Interface
I C Bus
Interface
2 interface is compliant with the Standard-mode and Fast-mode I2C-bus specifications. The I2C-bus
The I2C-bus
The I C-bus interface consists of two lines: serial data (SDA)
interface consists of two lines: serial data (SDA) and serial clock (SCL). In the Standard-mode, the serial clock
and
serialserial
data can go
up to 100
kbps and inThe
the Fast-mode,
the serial works
clock and serial
can go upand
to 400
and
clock
(SCL).
XR18910
as data
a slave
kbps. The first byte sent by an I2C-bus master contains a start bit (SDA transition from HIGH to LOW when
supports
both
standard
mode
rates (100
kbps)
and
SCL
is HIGH), 7-bit
slave address
and whether
it is a transfer
read or write transaction.
The next
byte is the
subaddress that contains the address of the register to access. The XR20M1280 responds to each write with
2 an
fast mode
transfer
rates (400
kbps)
asSCL
defined
the
acknowledge
(SDA driven
LOW by XR20M1280
for one clock
cycle when
is HIGH). Ifin
the TX
FIFOI isCfull,
2 acknowledge (SDA driven HIGH by XR20M1280 for one clock
the XR20M1280 will respond with a negative
Bus
specification.
The
I
C-bus
interface
follows
all
standard
cycle when SCL is HIGH) when the CPU tries to write to the TX FIFO. The last byte sent by an I2C-bus master
contains
a stop bit (SDA transition
from LOW
to HIGH when SCL is
is HIGH).
See Figuresbelow,
3 - 5 below.for
For
I2C protocols.
Some
information
provided
complete details, see the I2C-bus specifications.
additional information, refer to the I2C-bus specifications.
FIGURE 3.
Stop Condition
To signal the end of the data transfer, the master generates
a stop condition by pulling the SDA line from low to high
while the SCL line is high, as shown in Figure 22.
Figures 23 and 24 illustrate a write and a read cycle. For
complete details, see the I2C-bus specifications.
Figure 21. I C Power Up
2
1.1.1
I 2C
sub-address contains the address of the register to access.
The XR18910 Register List is shown in Table 1. Depending
on the register accessed, there will be up to two additional
data bytes transmitted by the master. Refer to the “Byte of
Parameter” column in the Register Table. The XR18910 will
respond to each write with an acknowledge.
START AND STOP CONDITIONS
S
SLAVE
ADDRESS
W
A
REGISTER
ADDRESS
A
nDATA
A
P
NOTES:
White Block = host to XR18910, Orange Block = XR18910 to host.
Figure 23. Master Writes to Slave (XR18910)
SLAVE
REGISTER
SLAVE
LAST
S ADDRESS W A ADDRESS A S ADDRESS R A nDATA A DATA NA P
NOTES:
White Block = host to XR18910, Orange Block = XR18910 to host.
SDA
Figure 24. Master Reads from Slave (XR18910)
SCL
S
P
START condition
STOP condition
I2C Bus Addressing
The XR18910 uses a 7-bit I2C address. For the standard
XR18910, the default address is 0x67 (110 0111). There
are three alternative addresses available to help insure that
the XR18910 can be identified from the other devices on
the I2C-bus. Table 4 shows the different addresses that are
available.
Figure 22. I2C Start and Stop Conditions
FIGURE 4. MASTER WRITES TO SLAVE (XR20M1280)
SLAVE
ADDRESS
S
W
REGISTER
ADDRESS
A
A
nDATA
A
P
The basic I2C access cycle for the XR18910 consists of:
White block: host to UART
Grey block: UART to host
A start condition
A slave address cycle
■■ Zero, one, or two data cycles - depending on the XR18910
FIGURE 5. MASTER READS FROM SLAVE (XR20M1280)
register accessed
■■ A stop condition
■■
■■
S
SLAVE
ADDRESS
W
A
REGISTER
ADDRESS
A
S
SLAVE
ADDRESS
R
A
nDATA
A
LAST DATA
Table 4. XR18910 I2C Address Map
NA
P
White block: host to UART
Grey block: UART to host
Start Condition
The master initiates data transfer by generating a start
condition. The start condition is when a high-to-low transition
occurs on the SDA line while SCL is high, as shown in
7
Figure 22.
Slave Address Cycle
After the start condition, the first byte sent by the master
is the 7-bit address and the read/write direction bit R/W
on the SDA line. If the address matches the XR18910’s
internal fixed address, the XR18910 will respond with an
acknowledge by pulling the SDA line low for one clock cycle
while SCL is high.
Data Cycle
After the master detects this acknowledge, the next byte
transmitted by the master is the sub-address. This 8-bit
Rev1C
I2C Address
Orderable Part Number
0x67
XR18910ILTR-67
0x66
XR18910ILMTR-66
0x65
XR18910ILMTR-65
0x64
XR18910ILMTR-64
A read or write transaction is determined by the bit
immediately following the I2C slave address. If this bit is
‘0’, then it is a write transaction. If this bit is a ‘1’, then it is
a read transaction.
An I2C sub-address is sent by the I2C master following the
slave address. The sub-address contains the XR18910
register address being accessed. Table 1 illustrates the
available XR18910 register addresses.
After the last read or write transaction, the I2C-bus master
will set the SCL signal back to its idle state (HIGH).
13/20
XR18910
Application Information (Continued)
Inputs and Input Selection
The XR18910 includes 8 differential inputs and a 8:1
differential MUX that is controlled by an I2C compatible 2
wire serial interface. The XR18910 is designed to accept 8
differential inputs.
■■
■■
If fewer than 4 differential inputs are required, tie the unused
inputs to GND.
If single ended inputs are required, tie the unused inputs to 1.5V.
The input common mode range of the XR18910 is typically
0.6V to 2.4V when running from a 3.3V supply. The
XR18910 offers a very wide gain range. In most cases, the
output voltage swing will be the limiting factor.
When the XR18910 is powered-up, the default input
selected is Channel 1.
2
Inputs are selected via I C using one of 8 register addresses
0x10, 0x12, 0x14, 0x15, 0x18, 0x1A, 0x1C, or 0x1E. Refer
to the Register List in Table 1.
Example: The example below illustrates how to select
Channel 4.
Step 1
0
Master sends start condition
S
Step 2
7
6
5
4
3
2
1
0
Master sends XR18910 address with
write bit
1
1
0
0
1
1
1
0
7-bit XR18910 Address
= 0x67
W
Gain Selection
The XR18910 offers 8 selectable fixed gains ranging from
2V/V to 760V/V. When the XR18910 is powered-up, the
default gain is 2V/V.
The gain is selected via I2C using the register address 0x06
followed by another byte of data to select the gain. Refer
to the Register List in Table 1 and the Gain Register list in
Table 3.
Example: The example below illustrates how to select a
gain of 150V/V.
To start communication with the XR18910, repeat steps 1-3 as
shown in the Inputs and Input Selection section on page 14.
Step 4
7
6
5
4
3
2
1
0
Master sends address of register to
access
0
0
0
0
0
1
1
0
Gain Select
register address = 0x06
Step 5
9
XR18910 sends acknowledge
A
Since the Gain Select register was accessed, the XR18910
is expecting another byte of data from the master to complete
the command. Refer to the “Byte of Parameter” column in
the Register List (Table 1). D0 thru D2 are used to select
the gain. Refer to the Gain Register list in Table 3, 150V/V
is D2 = 1, D1 = 0, and D0 = 0. This translates to a hex code
of 0x04, since a full byte of data (8-bits) will be sent.
Step 3
9
Step 6
7
6
5
4
3
2
1
0
XR18910 sends acknowledge
A
Master sends gain register data to select
G=150
0
0
0
0
0
1
0
0
Step 4
7
6
5
4
3
2
1
0
Master sends address of register to
access
0
0
0
1
0
1
0
1
Gain of 150V/V = 0x04
Select_Input 4
register address = 0x15
Step 5
9
XR18910 sends acknowledge
A
Step 6
0
Master sends stop condition
P
Step 7
9
XR18910 sends acknowledge
A
Step 8
0
Master sends stop condition
P
NOTES:
White Block = host to XR18910, Orange Block = XR18910 to host,
Grey Block = Notes.
NOTES:
White Block = host to XR18910, Orange Block = XR18910 to host,
Grey Block = Notes.
Rev1C
14/20
XR18910
Application Information (Continued)
Offset Correction
The XR18910 has a 10-bit offset correction DAC that can
be used to provide digital calibration on each of the 8 inputs.
Only the offset voltage of the active channel is applied to
the PGA.
Step 5
9
XR18910 sends acknowledge
A
The DAC offset of each channel is controlled by the I2C
compatible interface. At any time, the master can read or
write to any of the DAC offset registers. The DAC offset
for each channel is set via I2C using the register addresses
0x20 thru 0x2F followed by another two bytes of data to set
the polarity and value of the offset voltage. Refer to the
Register List in Table 1.
Since a DAC Offset register was accessed, the XR18910
is expecting another two bytes of data from the master to
complete the command. Refer to the “Byte of Parameter”
column in the Register List (Table 1). D0 thru D9 are used
to set the offset voltage and D10 is used to set the sign of
the offset voltage, 0 = positive and 1 = negative. Refer to
the DAC Offset register list in Table 2.
A ±560mV offset correction range is available. The full
range of the DAC offset is only available at a gain of 2.
At higher gains, the output voltage range of the XR18910
will be exceeded if the full range of the DAC offset is used.
The internal 10-bit DAC allows 1,024 different offset voltage
settings between 0mV and 560mV. The polarity of the
offset correction is set with an additional bit. The unit offset
is determined by the following:
To determine what DAC output level corresponds to 75mV,
use the following equation:
Desired Offse t
DAC Output Level =
Unit Offset
A decimal value of 137 corresponds to 75mV. Therefore:
■■
■■
Total Offset
560mV
Unit Offset = DAC Output Levels = 1024 = 547µ V
From Table 3:
■■
■■
■■
0x00 (hex) or 0 00 0000 0000 (binary) applies a 0mV offset
0x3FF (hex) or 0 11 1111 1111 (binary) applies a +560mV offset
0x7FF (hex) or 1 11 1111 1111 (binary) applies a -560mV offset
0x89 (hex) or 0 00 1000 1001 (binary) applies a 75mV offset
0x489 (hex) or 1 00 1000 1001 (binary) applies a -75mV offset
Step 6
15 14 13 12 11
10
9
8
Master sends 1st byte
of DAC offset register
data to select an offset
of +75mV
0
0
0
0
0
Desired Offset
x =
Unit Offset
See example below for additional information.
Example: The example below illustrates how to set the
DAC offset for channel 4 to a value of 75mV.
To start communication with the XR18910, repeat steps 1-3
as shown in the Inputs and Input Selection section on page
14.
7
6
5
4
3
2
1
0
Master sends address of register to
access
0
0
1
0
0
1
0
1
0
0
DAC4
register address = 0x25
2 MSBs of 10-bit DAC
output level that
corresponds to
137 (0x89)
Step 7
9
XR18910 sends acknowledge
A
Step 8
7
6
5
4
3
2
1
0
1
0
0
0
1
0
0
1
nd
Step 4
0
Sign
Each DAC output level provides an additional 547µV of
offset. To determine what DAC output level corresponds to
a specific desired offset, use the following equation:
75mV =
547 µV 137
=
Master sends 2 byte of DAC offset
register data to select an offset of +75mV
8 LSBs of 10-bit DAC
output level that
corresponds to 137 (0x89)
Step 9
9
XR18910 sends acknowledge
A
Step 10
0
Master sends stop condition
P
NOTES:
White Block = host to XR18910, Orange Block = XR18910 to host,
Grey Block = Notes.
Rev1C
15/20
XR18910
Application Information (Continued)
LDO Enable / Select (Power to External Bridge Sensors)
The XR18910 includes an on-board LDO that provides a
regulated voltage that can be used to power external input
bridge sensors. Two voltage options are available, 3V and
2.65V. The LDO voltage is selected via the I2C compatible
two-wire serial interface.
Step 6
7
6
5
4
3
2
1
0
Master sends code to select LDO
voltage of 2.65V and Enable LDO
during Sleep Mode
0
0
0
0
0
0
0
0
0=
Enable
1=
2.65V
When the XR18910 is powered-up, the default LDO voltage
is 3V.
When the XR18910 is active (not in sleep mode), the LDO
is always on. If the LDO voltage is not used, the LDO output
can be left floating. The LDO can either stay on or shut
down while the XR18910 is in Sleep Mode.
■■
■■
Set LDO to shut down while XR18910 is in Sleep Mode to save
power
Set LDO to stay on while XR18910 is in Sleep Mode to
improve wake-up time
The LDO voltage and disable setting are selected via I2C
using the register address 0x07 followed by another byte
of data to select the voltage and disable setting. Refer to
the Register List in Table 1 and the example below for more
information.
Step 7
9
XR18910 sends acknowledge
A
Step 8
0
Master sends stop condition
P
NOTES:
White Block = host to XR18910, Orange Block = XR18910 to host,
Grey Block = Notes.
Example: The example below illustrates how to select an
LDO voltage of 2.65V and keep the LDO enabled during
Sleep Mode.
Current Sense Mode (Monitoring the LDO Current)
Current Sense Mode is activated via I2C using the register
address 0x08. When activated, the LDO current is sensed
and a proportional voltage is present at the output of the
XR18910 (ILDO = VOUT/RL). Current Sense Mode stays
active until the XR18910 receives any input select command
(0x10, 0x12, 0x14, 0x15, 0x18, 0x1A, 0x1C, or 0x1E).
To start communication with the XR18910, repeat steps 1-3 as
shown in the Inputs and Input Selection section on page 14.
Current sense mode can be used to monitor the change
over time of the bridge impedance.
Step 4
7
6
5
4
3
2
1
0
Master sends address of register to
access
0
0
0
0
0
1
1
1
Sleep Mode (Analog Power Down)
Sleep mode is activated via I2C using the register address
0x05. When activated, the XR18910 will enter sleep mode.
During sleep mode, the analog portion of the XR18910
is disabled. All register settings are retained during sleep
mode.
LDO Settings
register address = 0x07
Step 5
9
XR18910 sends acknowledge
A
During sleep mode, the nominal supply current will drop
below 70µA (with LDO on) and below 45µA (with LDO off).
Since the LDO Settings register was accessed, the
XR18910 is expecting another byte of data from the master
to complete the command. Refer to the “Byte of Parameter”
column in the Register List (Table 1). D0 and D1 are used to
select the LDO voltage and enable/disable the LDO during
Sleep Mode. Bit 0 (D0) controls the LDO voltage (0: 3V;
1: 2.65V). Bit 1 (D1) is only applicable in Sleep Mode. Bit
1 controls whether the LDO shuts down or stays on during
sleep mode (0: Enable; 1: Disable). When the XR18910 is
active, the LDO is always on.
Rev1C
During sleep mode, the master can read the value in any
register that saves a value during sleep mode. The only
I2C commands that can be received or processed are the
SLEEP_OUT (wake up) command (0x04) and the LDO
on/off and voltage command (0x07). All other register
addresses will be ignored.
Register address 0x04 is used to return to normal operation
(exit Sleep Mode).
By default, the XR18910 is active.
16/20
XR18910
Application Information (Continued)
Typical Application – 8:1 Bridge Sensor Interface
The XR18910 was designed to interface multiple bridge sensors with a microcontroller or FPGA as illustrated in Figure 25.
The bridge output signal is differential (VO+ and VO-). Ideally, the unloaded bridge output is zero (VO+ and VO- are identical).
However, in-exact resistive values result in a difference between VO+ and VO-. This bridge offset voltage can be substantial
and vary between sensors. The XR18910 provides the ability to calibrate the bridge offset on each of the 8 bridge sensors
using the on-board DAC.
VDD
VCC
6.8μF
6.8μF
0.1μF
0.1μF
+
+
BRDG
VCC
VDD
0.1μF
BRIDGE 8
LDO
IN8+
IN8-
INA /
PGA
8:1
MUX
BRIDGE 1
10k
ADC
µC
10nF
±560mV
OFFSET TRIM
10-BIT
DAC
IN1+
IN1-
OUT
VDD
PGA
4.7k
VDD
4.7k
SDA
I2C
CONTROL
SCL
XR18910
AGND
DGND
Figure 25. 8:1 Bridge Sensor Interface
Layout Considerations
General layout and supply bypassing play major roles in high frequency performance. Follow the steps below as a basis for
high frequency layout:
■■
■■
■■
■■
■■
Include 6.8µF and 0.1µF ceramic capacitors for power supply decoupling
Place the 6.8µF capacitor within 0.75 inches of the power pin
Place the 0.1µF capacitor within 0.1 inches of the power pin
Connection to the exposed pad is not required. Exposed pad can be connected to ground (GND).
Minimize all trace lengths to reduce series inductances
Rev1C
17/20
XR18910
Mechanical Dimensions
TQFN24 3.5 x 3.5
BOTTOM VIEW
TOP VIEW
SIDE VIEW
TERMINAL DETAILS
Drawing No.: POD-00000070
Revision: B
Rev1C
18/20
XR18910
Recommended Land Pattern and Stencil
TQFN24 3.5 x 3.5
TYPICAL RECOMMENDED LAND PATTERN
TYPICAL RECOMMENDED STENCIL
Drawing No.: POD-00000070
Revision: B
Rev1C
19/20
XR18910
Ordering Information(1)
Part Number
Operating Temperature Range
Lead-Free
Package
XR18910ILTR-67
Packaging Method
Tape and Reel
XR18910ILMTR-67
XR18910ILMTR-66
Yes(2)
-40°C to 85°C
3.5mm x 3.5mm
TQFN-24
XR18910ILMTR-65
Tape and Mini Reel
XR18910ILMTR-64
XR18910ILEVB
Evaluation board
NOTES:
1. Refer to www.exar.com/XR18910 for most up-to-date Ordering Information.
2. Visit www.exar.com for additional information on Environmental Rating.
Revision History
Revision
Date
Description
1A
March 2016
Initial Release
1B
May 2016
1C
March 2018
Added clarity to I2C Bus Addressing section. Updated Table 4. Updated Step 2 in Inputs and Input
Selection section.
Updated to MaxLinear logo. Updated format and Ordering Information. Added I2C Power Up section.
Package name updated to TQFN.
Corporate Headquarters:
5966 La Place Court
Suite 100
Carlsbad, CA 92008
Tel.:+1 (760) 692-0711
Fax: +1 (760) 444-8598
www.maxlinear.com
High Performance Analog:
1060 Rincon Circle
San Jose, CA 95131
Tel.: +1 (669) 265-6100
Fax: +1 (669) 265-6101
Email: hpatechsupport@exar.com
www.exar.com
The content of this document is furnished for informational use only, is subject to change without notice, and should not be construed as a commitment by MaxLinear, Inc.. MaxLinear, Inc. assumes
no responsibility or liability for any errors or inaccuracies that may appear in the informational content contained in this guide. Complying with all applicable copyright laws is the responsibility of the
user. Without limiting the rights under copyright, no part of this document may be reproduced into, stored in, or introduced into a retrieval system, or transmitted in any form or by any means (electronic,
mechanical, photocopying, recording, or otherwise), or for any purpose, without the express written permission of MaxLinear, Inc.
Maxlinear, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support
system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless MaxLinear, Inc. receives, in writing, assurances to its satisfaction that: (a) the
risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of MaxLinear, Inc. is adequately protected under the circumstances.
MaxLinear, Inc. may have patents, patent applications, trademarks, copyrights, or other intellectual property rights covering subject matter in this document. Except as expressly provided in any written
license agreement from MaxLinear, Inc., the furnishing of this document does not give you any license to these patents, trademarks, copyrights, or other intellectual property.
Company and product names may be registered trademarks or trademarks of the respective owners with which they are associated.
© 2016 - 2018 MaxLinear, Inc. All rights reserved
XR18910_DS_042018
Rev1C
20/20
工商网监
湘ICP备2023018690号
