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XR28V382IL32-F

XR28V382IL32-F

  • 厂商:

    SIPEX(迈凌)

  • 封装:

    32-VFQFN裸露焊盘

  • 描述:

    IC DUAL UART W/FIFO 3.3V 32-QFN

  • 数据手册
  • 价格&库存
XR28V382IL32-F 数据手册
XR28V382 3.3V DUAL LPC UART WITH 128-BYTE FIFO MARCH 2018 REV. 1.0.2 GENERAL DESCRIPTION FEATURES  128 Byte Transmit and Receive FIFO  Compliant to LPC 1.1 Specifications  -40°C to +85°C Industrial Temp Operation  Watchdog Timer with WDTOUT# signal  2 independent UART channels The XR28V382 (V382) is a dual Universal Asynchronous Receiver and Transmitter (UART) for the Intel Low Pin Count (LPC) bus interface. This device can replace or supplement a Super I/O device to add additional serial ports to the system. The V382 UARTs support any 16-bit I/O address supported by the system. The register set is based on the industry standard 16550 UART, so the V382 operates with standard serial port drivers without requiring a custom driver to be installed. The 128 byte Transmit and Receive FIFOs reduce CPU overhead and minimize the chance of buffer overflow and data loss. In addition to the 16550 UART registers, there are also Configuration register set where enhanced features such as the 9-bit (multidrop) mode, IrDA mode and the Watchdog Timer can be enabled. ■ Programmable I/O mapped base addresses ■ Data rates up to 3 Mbps ■ Selectable RX FIFO interrupt trigger levels ■ Auto RS-485 Half-Duplex Control mode ■ Programmable character lengths (5, 6, 7, 8) with even, odd, or no parity ■ IrDA mode and separate IRTXA# and IRRXA# pins for the first UART channel ■ 9-bit (Multidrop) mode  External 24MHz/48MHz clock  Single 3.3V Supply Voltage ( ± 10%)  5V tolerant inputs  32-QFN package (5mm x 5mm) The V382 is available in a 32-pin QFN package. APPLICATIONS  Industrial and Embedded PCs  Factory Automation and Process Controls  Network Routers  System Board Designs FIGURE 1. XR28V382 BLOCK DIAGRAM VCC GND P C IR S T # LC LK LFR AM E# L A D [3 :0 ] S E R IR Q 3 .3 V ± 1 0 % Baud R a te G e n e ra to r LPC Bus In te rfa ce W D TO U T#/ PS_W D T C L K IN R X F IF O W a tch D og T im e r C lo ck D ivid e r T X A / P S _ 3 F 8 _ IR Q A IR T X A # / P S _ C O N F _ K E Y 0 RXA (IrD A D e cod er) IR R X A # S ta tu s a n d C o n tro l R e g iste rs G lo b a l C o n fig u ra tio n R e g iste rs T X F IF O (IrD A E nco de r) R T S A # /P S _ C O N F _ 2 E /R S 4 8 5 M o d e m IO s U AR T C hannel A Baud R a te G e n e ra to r S ta tu s a n d C o n tro l R e g iste rs C T S A # , D S R A # , C D A # , R IA # T X F IF O T X B / P S _ 2 F 8 _ IR Q B R X F IF O RXB R T S B # /P S _ C O N F _ K E Y 1 /R S 4 8 5 M o d e m IO s U AR T C hannel B 1 D T R A # /P S _ 3 E 0 _ IR Q A D T R B # /P S _ 2 E 0 _ IR Q B C TSB#, D SR B#, C D B#, R IB # XR28V382 3.3V DUAL LPC UART WITH 128-BYTE FIFO REV. 1.0.2 PCIRST# IRTXA#/PS_CONF_KEY0 IRRXA# TXA/PS_3F8_IRQA RXA DTRA#/PS_3E0_IRQA RTSA#/PS_CONF_2E/RS485 TXB/PS_2F8_IRQB FIGURE 2. PIN OUT ASSIGNMENT 32 31 30 29 28 27 26 25 GND 1 24 RXB LAD3 2 23 DTRB#/PS_2E0_IRQB LAD2 3 22 RTSB#/PS_CONF_KEY1/RS485 LAD1 4 21 VCC LAD0 5 20 GND LCLK 6 19 WDTOUT#/PS_WDT LFRAME# 7 18 CDA# 17 RIA# E_PAD 10 11 12 13 14 15 DSRB# SERIRQ CDB# RIB# CTSA# 16 DSRA# 9 CTSB# 8 CLKIN VCC XR28V382 32-pin QFN Ordering Information(1) PART NUMBER XR28V382IL32-F XR28V382IL32TR-F XR28V382IL32-0A-EB OPERATING TEMPERATURE RANGE LEAD-FREE PACKAGE -40°C to +85°C Yes(2) 32-Lead QFN XR28V382 Evaluation Board NOTES: 1. Refer to www.exar.com/XR28V382 for most up-to-date Ordering Information. 2. Visit www.exar.com for additional information on Environmental Rating. 2 PACKAGING METHOD Tray Tape and Reel XR28V382 3.3V DUAL LPC UART WITH 128-BYTE FIFO REV. 1.0.2 PIN DESCRIPTIONS Pin Description NAME 32-QFN PIN# DESCRIPTION TYPE LPC BUS INTERFACE PCIRST# 32 I Active low Reset signal. LAD3 LAD2 LAD1 LAD0 2 3 4 5 I/O LCLK 6 I LPC clock input up to 33.3MHz. LFRAME# 7 I Active low LPC Frame signal indicates start of a new cycle or termination of a broken cycle. Multiplexed address / data bus [3:0]. See ’Section 1.2, LPC Bus Interface’. 12 I/O Bi-directional pin for sending interrupts. By default this pin is tri-stated when idle. Interrupts can be active high or low. See ’Section 1.2.1, Serial IRQ’ and See ’Section 2.2.1.3, Interrupt Enable Register (IER) - Read/Write’ for more  information regarding interrupts. CTSB# 10 I UART Channel B Clear-to-Send (active low) or general purpose input. This input should be connected to VCC or GND when not used. DSRB# 11 I UART Channel BChannel B Data-Set-Ready (active low) or general purpose input. This input should be connected to VCC or GND when not used. CDB# 13 I UART Channel B Carrier-Detect (active low) or general purpose input. This input should be connected to VCC or GND when not used. RIB# 14 I UART Channel B Ring-Indicator (active low) or general purpose input. This input should be connected to VCC or GND when not used. O UART Channel B Request-to-Send (active low) or general purpose output or automatic RS485 Half Duplex control pin. See ’Section 1.4.4, Auto RS-485 Half-Duplex Control’. This pin has an internal pull-up resistor and is sampled upon power-up or reset See Table 1 ’UART Power On Configuration’. SERIRQ UART I/O INTERFACE RTSB#/PS_CONF_KEY1/RS485 22 DTRB#/ PS_2E0_IRQB 23 O UART Channel B Data-Terminal-Ready (active low) or general purpose output . This pin has an internal pull-up resistor and is sampled upon power-up or reset. This will determine the default register settings for UART channel B. The  registers can later be modified by the software. See Table 1 ’UART Power On Configuration’. RXB 24 I UART Channel B Receive data. Normal receive data input must idle at logic 1 condition. This input should be connected to VCC or GND when not used. TXB/ PS_2F8_IRQB 25 O UART Channel B Transmit Data. The TXB signal will be a logic 1 during reset or idle (no data). If it is not used, leave it unconnected. This pin has an internal pull-up resistor and is sampled upon power-up or reset. This will determine the default register settings for UART Channel B. The  registers can later be modified by the software.  See Table 1 ’UART Power On Configuration’. CTSA# 15 I UART Channel A Clear-to-Send (active low) or general purpose input. This input should be connected to VCC or GND when not used. 3 XR28V382 3.3V DUAL LPC UART WITH 128-BYTE FIFO REV. 1.0.2 Pin Description NAME 32-QFN PIN# TYPE DSRA# 16 I UART Channel A Data-Set-Ready (active low) or general purpose input. This input should be connected to VCC or GND when not used. RIA# 17 I UART Channel A Ring-Indicator (active low) or general purpose input. This input should be connected to VCC or GND when not used. CDA# 18 I UART Channel A Carrier-Detect (active low) or general purpose input. This input should be connected to VCC or GND when not used. O UART Channel A Request-to-Send (active low) or general purpose output. This pin has an internal pull-up resistor and is sampled upon power-up or reset. The registers can later be modified by the software. See Table 1 ’UART Power On Configuration’. RTSA# / PS_CONF_2E/ RS485 26 DESCRIPTION DTRA# / PS_3E0_IRQA 27 O UART Channel A Data-Terminal-Ready (active low) or general purpose output. This pin has an internal pull-up resistor and is sampled upon power-up or reset. This will determine the default register settings for UART Channel A. The  registers can later be modified by the software. See Table 1 ’UART Power On Configuration’. RXA 28 I UART Channel A Receive data.The receive data input must idle at logic 1  condition. This input should be connected to VCC or GND when not used. TXA / PS_3F8_IRQA 29 O UART Channel A Transmit Data. The TXA signal will be a logic 1 during reset or idle (no data). If it is not used, leave it unconnected. This pin has an internal pull-up resistor and is sampled upon power-up or reset. This will determine the default register settings for UART Channel A. The  registers can later be modified by the software. See Table 1 ’UART Power On Configuration’. IRRXA# 30 I Infrared Receiver input. The infrared receive data input idles at logic 0. This input should be connected to GND when not used. IRTXA# 31 O Infrared Transmitter output. The IRTXA# signal will be a logic 0 during reset or idle (no data). ANCILLARY SIGNALS CLKIN 9 I Clock input 24 MHz or 48 MHz. WDTOUT#/ PS_WDT 19 O Active low watchdog timer output. This pin is open drain and needs a pull-up resistor if it is used. The registers can later be modified by the software. See Table 1 ’UART Power On Configuration’. VCC 8, 21 Pwr 3.3V ± 10% power supply. GND 1, 20 Pwr Power supply common, ground. Pwr The center pad on the back side of the QFN package is metallic and should be connected to GND on the PCB. The thermal pad size on the PCB should be the approximate size of this center pad and should be solder mask defined. The  solder mask opening should be at least 0.0025" inwards from the edge of the PCB thermal pad. POWER SIGNALS GND Center Pad Pin type: I=Input, O=Output, I/O= Input/output, Pwr=Power supply. 4 XR28V382 3.3V DUAL LPC UART WITH 128-BYTE FIFO REV. 1.0.2 1.0 FUNCTIONAL DESCRIPTIONS 1.1 Power on Strapping Options At power-on, strapping options for each pin listed in Table 1 result in the register values based upon the pin state selected. These register values can also be modified by the software. 1.1.1 UART/Watchdog Timer Options The V382 provides five pins for power on hardware strapping options to select the settings of the UART channels and Watchdog Timer. TABLE 1: UART POWER ON CONFIGURATION REGISTER VALUES PIN NUMBER 23 25 27 29 19 PIN NAME PIN STATE ENABLE (0X30) BASE ADDRESS HIGH REGISTER (0X60) BASE ADDRESS LOW REGISTER (0X61) IRQSEL (0X70) DTRB# / PS_2E0_IRQB 1 0x1 0x2 0xE0 0x4 0 0x0 0x0 0x0 0x0 TXB / PS_2F8_IRQB 1 0x1 0x2 0xF8 0x4 0 0x0 0x0 0x0 0x0 DTRA# / PS_3E0_IRQA 1 0x1 0x3 0xE0 0x3 0 0x0 0x0 0x0 0x0 TXA / PS_3F8_IRQA 1 0x1 0x3 0xF8 0x3 0 0x0 0x0 0x0 0x0 WDTOUT# / PS_WDT 1 0x1 0x4 0x42 0x0 0 0x0 0x0 0x0 0x0 COMMENT When both pins are high, the base address will be 0x2F8. When both pins are high, the base address will be 0x3F8. After power-on, the Enable, Base Address High & Low, IRQSEL registers can be modified by the software. 1.1.2 1.1.2.1 Configuration Port and Key Selection Options Configuration Port Selection Option The configuration registers are programmed by the index port and the data port. The port address is determined by the strap pin RTSA#/PS_CONF_2E/RS485. If an external pull-down resistor is not installed, the default value of the RTSA#/PS_CONF_2E/RS485 pin is ’1’ when the system powers on. Therefore, the default index port address is 0x2E and the data port address is 0x2F. TABLE 2: CONFIGURATION PORT SELECTION RTSA#/PS_CONF_2E/RS485 (PIN 26) INDEX PORT ADDRESS DATA PORT ADDRESS 0 0x4E 0x4F 1 (default) 0x2E 0x2F 5 XR28V382 3.3V DUAL LPC UART WITH 128-BYTE FIFO 1.1.2.2 REV. 1.0.2 Configuration Entry Key Options In order to enable the configuration register access mode, the entry key needs to be written consecutively twice to the index port. The entry key is generated by the power on setting pins RTSB#/PS_CONF_KEY1/ RS485 and IRTXA#/PS_CONF_KEY0. TABLE 3: CONFIGURATION ENTRY KEY RTSB#/PS_CONF_KEY1/RS485 (PIN 22) IRTXA#/PS_CONF_KEY0 (PIN 31) ENTRY KEY 0 0 0x77 0 1 0xA0 1 0 0x87 1 1 0x67 (Default) In order to disable the configuration register access mode, 0xAA must be written to the index port. 1.1.2.3 1.1.2.3.1 Example Index port address 0x2E & Data port address 0x2F (default) write (0x2E, 0x67); write (0x2E, 0x67); //write entry key (0x67) twice to configuration port //Enable access to the configuration registers write (0x2E, 0x20); //Select the DEV_ID_M register read (0x2F); //Read the DEV_ID_M register write (0x2E, 0x21); //Select the DEV_ID_L register read (0x2F); //Read the DEV_ID_L register write (0x2E, 0x25); //Select the Clock Select Register write (0x2F, 0x1); //Select the input clock frequency 48 MHz write (0x2E, 0x7); //Select the LDN register write (0x2F, 0x1); //Select the UART Channel B write (0x2E, 0xF6); //Select the FIFO Mode Select Register of UART Channel B write (0x2F, 0x3); //Set the FIFO size 128 bytes, //RX trigger level 1, 4, 8, 14 and no delay for THR empty interrupt write (0x2E, 0x30); write (0x2F, 0x1); //Enable the UART Channel B write (0x2E, 0xAA); //Disable access to configuration registers 6 XR28V382 3.3V DUAL LPC UART WITH 128-BYTE FIFO REV. 1.0.2 1.1.2.3.2 Index port address 0x4E & Data port address 0x4F write (0x4E, 0x67); write (0x4E, 0x67); //write entry key (0x67) twice to configuration port //Enable access to the configuration registers write (0x4E, 0x23); //Select the VID_M register read (0x4F); //Read the VID_M register write (0x4E, 0x24); //Select the VID_L register read (0x4F); //Read the VID_L register write (0x4E, 0x25); //Select the Clock Select Register write (0x4F, 0x0); //Select the input clock frequency 24 MHz write (0x4E, 0x7); //Select the LDN register write (0x4F, 0x0); //Select the UART Channel A write (0x4E, 0x60); write (0x4F, 0x3); //Set the UART Channel A base address high byte as 0x3 write (0x4E, 0x61); write (0x4F, 0xF8); //Set the UART Channel A base address low byte as 0xF8 write (0x4E, 0xF6); //Select the FIFO Mode Select Register of UART Channel A write (0x4F, 0x0); //Set the FIFO size 16 bytes, //RX trigger level 1, 4, 8, 14 and no delay for THR empty interrupt write (0x4E, 0x30); write (0x4F, 0x1); //Enable the UART Channel A write (0x4E, 0xAA); //Disable access to the configuration registers 1.2 LPC Bus Interface The LPC bus interface has a 4-bit multiplexed address/data bus, 1 reset signal, 1 clock and 1 control signal. It also has one interrupt signal. The V382 implements the following signals of the LPC bus. ■ LFRAME# is used by the host to start or stop transfers. ■ LCLK is a clock used for synchronization. ■ PCIRST# is an active low reset signal. ■ LAD[3:0] signal lines communicate device address, control (read, write, wait and transfer type), and data information over the LPC bus between a host and a peripheral. ■ Interrupt requests are issued through SERIRQ. 1.2.1 Serial IRQ The V382 supports a serial IRQ scheme specified in specification for Serialized IRQ support for PCI system Rev6.0 which allows SERIRQ pin to be shared with multiple devices. The SERIRQ signal is tri-stated when idle. The SERIRQ is divided into 3 types of time slots known as Frames: Start frame, IRQ frame, and Stop frame. The SERIRQ uses LCLK for timing. There are two modes of operation for SERIRQ signal: Quiet mode and Continuous mode. These two modes are discussed in further detail in ’Section 1.2.1.1, Start Frame’. 7 XR28V382 3.3V DUAL LPC UART WITH 128-BYTE FIFO 1.2.1.1 REV. 1.0.2 Start Frame The Start frame indicates begining of the SERIRQ cycle. During this frame the SERIRQ is driven LOW for 4-8 clock cycles. It can be initiated by the host or V382 depending on the mode of operation. In the Continuous mode, only the host controller initiates the Start frame to update the SERIRQ line information. The host controller drives the SERIRQ signal low for 4 to 8 clock periods. Upon a reset, the SERIRQ signal defaults to the Continuous mode for the host controller to initiate the first Start frame. In the Quiet mode, the Start frame is initiated by the device/host. The V382 drives the SERIRQ signal active low for one clock to initiate a Start Frame, and then tri-states it immediately. The host controller will then take over driving SERIRQ signal low in the next clock and will continue driving the SERIRQ low for 3 to 7 clock periods. This makes the total number of clocks low for 4 to 8 clock periods. After these clocks, the host controller will drive the SERIRQ high for one clock and then tri-states it. A Start Frame may not be initiated while SERIRQ is active. The SERIRQ is active between Start and Stop frames while it is idle between Stop and Start frames. 1.2.1.2 IRQ Frame Once the start frame has been initiated, all the peripherals must start counting frames based on the rising edge of the clock (LCLK). Each IRQ Frame is three clocks: Sample phase, Recovery phase, and Turn-around phase. During the Sample phase, the peripheral drives SERIRQ low if the corresponding IRQ is active. If the corresponding IRQ is inactive, then SERIRQ will be left tri-stated. During the Recovery phase, the peripheral device drives the SERIRQ high. During the Turn-around phase, the peripheral device leaves the SERIRQ tristated. The V382 supports IRQ3, IRQ4, IRQ5, IRQ7, IRQ9, IRQ10, and IRQ11. TABLE 4: SERIRQ SAMPLING PERIODS IRQ/DATA FRAME SIGNAL SAMPLED NUMBER OF CLOCKS PAST START 1 IRQ0 2 2 IRQ1 5 3 SMI# 8 4 IRQ3 11 5 IRQ4 14 6 IRQ5 17 7 IRQ6 20 8 IRQ7 23 9 IRQ8 26 10 IRQ9 29 11 IRQ10 32 12 IRQ11 35 13 IRQ12 38 14 IRQ13 41 15 IRQ14 44 16 IRQ15 47 17 IOCHCK# 50 18 INTA# 53 19 INTB# 56 20 INTC# 59 21 INTD# 62 32:22 Unassigned 95 8 XR28V382 3.3V DUAL LPC UART WITH 128-BYTE FIFO REV. 1.0.2 1.2.1.3 Stop Frame After all IRQ/Data Frames have been completed, the host controller will terminate SERIRQ by a Stop frame. Only the host controller can initiate the Stop frame by driving SERIRQ low for 2 or 3 clocks. If the Stop Frame is low for 2 clocks, the next SERIRQ cycle will be the Quiet mode whereas if it is low for 3 clocks, the next SERIRQ cycle will be the Continuous mode. 1.3 Watchdog Timer (WDT) The WDT is typically used in a system to initiate any of the several types of corrective action, including processor reset, power cycling, fail-safe activation etc. The Watchdog timer of V382 is an 8 bit counter controlled by six registers. See ’Section 2.1.2.2, Watchdog Timer Registers (LDN = 0x08)’ WDTOUT#/ PS_WDT idles HIGH and will transition LOW when a time out occurs. The V382 provides three time intervals: 10 ms, 1s and 1 minute allowing for timeouts ranging from approximately 2.5 seconds to more than 4 hours. See’Section2.1.2.2.4,WDTTimerStatusandControlRegister-Read/Write’tosetuptimeinterval. 1.4 UART 1.4.1 External Clock Input (CLKIN) Along with LCLK, the V382 also needs an external clock for UART data communication. It can support any clock up to 48MHz. The 24MHz and 48MHz are the standard clock frequencies supported by the V382. See ’Section 2.1.1.5, Clock Select Register - Read/Write’. 1.4.1.1 Programmable Baud Rate Generator Each UART has its own Baud Rate Generator (BRG) with a prescaler. The prescaler is controlled by Bit[1:0] of Enhanced Multifunction Register - Read/Write. Table 5 shows the standard data rates available with a 24 MHz external clock at 16X sampling rate and internal clock frequency set to 1.8462 MHz. The divisor value can be calculated for DLL/DLM with the following equation. divisor (decimal) = (Internal clock frequency ) / (serial data rate x 16) Table 8 lists the different internal clock settings. TABLE 5: TYPICAL DATA RATES WITH A 1.8462MHZ INTERNAL CLOCK BAUD Rate (BPS) DIVISOR FOR 16x DIVISOR FOR 16x Clock (Decimal) Clock (HEX) DLM PROGRAM VALUE (HEX) DLL PROGRAM VALUE (HEX) ACTUAL BAUD RATE DATA RATE ERROR (%) 300 384 180 01 80 300.48 0.2 600 192 C0 00 C0 600.96 0.2 1200 96 60 00 60 1201.92 0.2 2400 48 30 00 30 2403.85 0.2 4800 24 18 00 18 4807.69 0.2 9600 12 0C 00 0C 9615.39 0.2 19200 6 06 00 06 19230.77 0.2 38400 3 03 00 03 38461.54 0.2 57600 2 02 00 02 57692.31 0.2 115200 1 01 00 01 115384.6 0.2 9 XR28V382 3.3V DUAL LPC UART WITH 128-BYTE FIFO 1.4.2 REV. 1.0.2 Transmitter The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and up to 128 bytes of FIFO which includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the internal sampling clock. The transmitter sends the start bit followed by the number of data bits, inserts the proper parity bit if enabled, and adds the stop bit(s). The status of the THR and TSR are reported in the Line Status Register (LSR bit-5 and bit-6). 1.4.2.1 Transmit Holding Register (THR) - Write Only The transmit holding register is an 8-bit register providing a data interface to the host processor. The host writes transmit data byte to the THR to be converted into a serial data stream including start bit, data bits, parity bit and stop bit(s). The least significant bit (Bit-0) becomes first data bit to go out. The THR is the input register to the transmit FIFO of up to 128 bytes when FIFO operation is enabled by FCR bit-0. Every time a write operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data location. 1.4.2.2 Transmitter Operation in non-FIFO Mode The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty. FIGURE 3. TRANSMITTER OPERATION IN NON-FIFO MODE Data Byte Clock Transmit Holding Register (THR) THR Interrupt (ISR bit-1) Enabled by IER bit-1 Transmit Shift Register (TSR) M S B L S B TXNOFIFO1 10 XR28V382 3.3V DUAL LPC UART WITH 128-BYTE FIFO REV. 1.0.2 1.4.2.3 Transmitter Operation in FIFO Mode The host may fill the transmit FIFO with up to 128 bytes of transmit data. The THR empty flag (LSR bit-5) is set whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the FIFO becomes empty. The transmit empty interrupt is enabled by IER bit-1. The TSR flag (LSR bit-6) is set when TSR/FIFO becomes empty. FIGURE 4. TRANSMITTER OPERATION IN FIFO MODE Transmit Data Byte Clock Transmit FIFO THR Interrupt (ISR bit-1) when TX FIFO becomes empty. FIFO is enabled by FCR bit-0=1 Transmit Data Shift Register (TSR) TXFIFO1 1.4.3 Receiver The receiver section contains an 8-bit Receive Shift Register (RSR) and up to 128 bytes of FIFO which includes a byte-wide Receive Holding Register (RHR). The RSR uses the internal sampling clock for timing. It verifies and validates every bit on the incoming character in the middle of each data bit. On the falling edge of a start or false start bit, an internal receiver counter starts counting at the clock rate. After 8 clocks the start bit period should be at the center of the start bit. At this time the start bit is sampled and if it is still a logic 0 it is validated. Evaluating the start bit in this manner prevents the receiver from assembling a false character. The rest of the data bits and stop bits are sampled and validated in this same manner to prevent false framing. If there were any error(s), they are reported in the LSR register bits 2-4. Upon unloading the receive data byte from RHR, the receive FIFO pointer is bumped and the error tags are immediately updated to reflect the status of the data byte in RHR register. RHR can generate a receive data ready interrupt upon receiving a character or delay until it reaches the FIFO trigger level. Furthermore, data delivery to the host is guaranteed by a receive data ready time-out interrupt when data is not received for 4 word lengths as defined by LCR[1:0] plus 12 bits time. This is equivalent to 3.7-4.6 character times. The RHR interrupt is enabled by IER bit-0. See Figure 5. 11 XR28V382 3.3V DUAL LPC UART WITH 128-BYTE FIFO 1.4.3.1 REV. 1.0.2 Receive Holding Register (RHR) - Read-Only The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift Register. It provides the receive data interface to the host processor. The RHR register is part of the receive FIFO of up to 128 bytes by 11-bits wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. When the FIFO is enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After the RHR is read, the next character byte is loaded into the RHR and the errors associated with the current data byte are immediately updated in the LSR bits 2-4. FIGURE 5. RECEIVER OPERATION IN NON-FIFO MODE Clock Receive Data Shift Register (RSR) Error Tags in LSR bits 4:2 Receive Data Byte and Errors Receive Data Holding Register (RHR) Data Bit Validation Receive Data Characters RHR Interrupt (ISR bit-2) RXFIFO1 FIGURE 6. RECEIVER OPERATION IN FIFO MODE C lock R eceive D ata S hift R egister (R S R) R eceive D ata C haracters E xam ple : - R X FIFO trigger level selected at 8 bytes Error Tags in LSR bits 4:2 Error Tags (Up to 128-sets) U p to 128 byte 11-bit w idth F IF O R eceive D ata B yte and E rrors D ata B it V alidation R eceive D ata FIFO FIFO Trigger=8 R H R Interrupt (IS R bit-2) program m ed for desired F IF O trigger level. F IF O is E nabled by FC R bit-0=1 R eceive D ata RXFIFO 1 12 XR28V382 3.3V DUAL LPC UART WITH 128-BYTE FIFO REV. 1.0.2 1.4.4 Auto RS-485 Half-Duplex Control The Auto RS-485 Half-Duplex Control feature changes the behavior of the RTS#/RS485 pin when enabled by Enhanced Multifunction Register - Read/Write bit-4. If enabled, by default, it de-asserts RTS#/RS485 ouput following the last stop bit of the last character that has been transmitted. This helps in turning around the transceiver to receive the remote station’s response. When the host is ready to transmit data packet, it only has to load data bytes to the transmit FIFO. The transmitter automatically asserts RTS#/RS485 output prior to sending the data. The polarity of RTS#/RS485 signal can be modified by bit-5 of Enhanced Multifunction register. 1.4.5 Normal Multidrop (9-bit) Mode Normal multidrop mode is enabled when bit-7 of Enhanced Multifunction register in the UART Device Configuration Registers is set to ’1’. In the multidrop (9-bit) mode, the parity bit becomes the address/data bit. If a data byte is received (9th bit is '0'), it will be loaded into the RX FIFO and the parity error bit will be '0'. If an address byte is received (9th bit is '1'), it will be loaded into the RX FIFO and the parity error bit will be '1'. When the address byte has been received, the software will need to examine the byte: If the address matches its slave address, the receiver will receive the subsequent data; If the address does not match its slave address, then the receiver will discard the data. 1.4.5.1 Auto Address Detection Auto Address Detection mode is enabled when bit-6 of Enhanced Multifunction register (0xF0) in UART device configuration registers set is set to ’1’. The desired slave address will need to be written into the 9-bit mode slave address register (0xF4) in the UART device configuration registers set. If the received byte is an address byte that does not match the programmed character in the 9-bit mode slave address register, the receiver will discard these data. Upon receiving an address byte that matches the 9-bit mode slave address register character, the receiver will automatically push the address byte into the RX FIFO and set the parity error bit in the LSR register. The receiver also generates an LSR interrupt if enabled. The receiver will then receive the subsequent data. If another address byte is received and does not match the programmed 9-bit mode slave address register value, then the receiver will ignore the data that follows. 13 XR28V382 3.3V DUAL LPC UART WITH 128-BYTE FIFO 1.4.6 REV. 1.0.2 Infrared Mode The V382 UART Channel A includes the infrared encoder and decoder compatible to IrDA (Infrared Data Association) version 1.0. The infrared encoder sends out a 3/16 of a bit wide or 1.6 uS HIGH pulse for each “0” bit in the transmit data stream with a data rate up to 115.2 kbps. This signal encoding reduces the on-time of the infrared LED, hence reduces the power consumption. See Figure 7. The infrared encoder and decoder are enabled by setting Infrared Mode Control Register - Read/Write bit-4 to a ’1’. The IRRXA# input assumes an idle level of logic zero after a reset and power up, see Figure 7. The IRRXA# input will assume an idle level of logic HIGH if bit-0 of the Infrared Mode Control Register - Read/ Write is set to ’1’. The IRTXA# is idle at LOW by default. The IRTXA# will be idle at HIGH if bit-1 of the Infrared Mode Control Register - Read/Write is set to ’1’. Typically, the wireless infrared decoder receives the input pulse from the infrared sensing diode on the IRRXA# pin. Each time it senses a light pulse, it returns a logic 0 to the data bit stream. FIGURE 7. INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING TX Data Transmit IR Pulse (IRTXA# Pin) 0 Stop Start Character Data Bits 1 1 0 Bit Time 0 1 0 1 1 0 1/2 Bit Time 3/16 Bit Time or 1.6 uS IrEncoder-1 Receive IR Pulse (IRRXA# Pin) Bit Time RX Data 0 1 0 1 0 0 Data Bits 1 1 0 1 Stop Start 1/16 Clock Delay Character IRdecoder-1 14 XR28V382 3.3V DUAL LPC UART WITH 128-BYTE FIFO REV. 1.0.2 1.4.7 Internal Loopback The V382 provides an internal loopback capability for system diagnostic purposes. The internal loopback mode is enabled by setting MCR register bit-4 to logic 1. Figure 8 shows how the modem port signals are reconfigured. Transmit data from the transmit shift register output is internally routed to the receive shift register input allowing the system to receive the same data that it was sending. The TX pin is held HIGH or mark condition while RTS# and DTR# are de-asserted, and CTS#, DSR# CD# and RI# inputs are ignored. Caution: the RX input must be held HIGH during loopback test else upon exiting the loopback test the UART may detect and report a false “break” signal. FIGURE 8. INTERNAL LOOPBACK VCC TX T ra n s m it S h ift R e g is te r (T H R /F IF O ) R e c e iv e S h ift R e g is te r (R H R /F IF O ) RX VCC RTS# RTS# Modem / General Purpose Control Logic Internal Data Bus Lines and Control Signals M C R b it-4 = 1 CTS# CTS# VCC DTR# DTR# DSR# DSR# O P1# R I# R I# O P2# CD# 15 CD# XR28V382 3.3V DUAL LPC UART WITH 128-BYTE FIFO 1.5 REV. 1.0.2 Serial Transceiver Interface The V382 is typically used with RS-232, RS-485 and IR transceivers. The following figure shows typical connections from the UART to the different transceivers. For more information on RS-232 and RS-485/422 transceivers, go to www.exar.com or send an e-mail to uarttechsupport@exar.com. FIGURE 9. XR28V382 TYPICAL SERIAL INTERFACE CONNECTIONS VCC UART VCC R S -2 3 2 T ra n s c e iv e r TX T 1 IN RX R1OUT DTR# T 2 IN RTS# T 3 IN CTS# R2OUT DSR# R 3O U T CD# R 4O U T R I# R5O U T GND GND R S -2 3 2 F u ll- M o d e m S e r ia l In te r fa c e VCC VCC TX DI RO RX UART RS-485 Transceiver Full-duplex RTS# NC DTR# NC TX+ TX- VCC VCC RX+ DE CTS# RXRE# DSR# CD# RI # GND RS-485 Full-Duplex Serial Interface 16 XR28V382 3.3V DUAL LPC UART WITH 128-BYTE FIFO REV. 1.0.2 FIGURE 10. XR28V382 TYPICAL SERIAL INTERFACE CONNECTIONS VCC VCC UART TX DI RX RO RTS# DE VCC NC DTR# RS-485 Transceiver Half-duplex Y Z A RE# CTS# B DSR# CD# RI # GND RS-485 Half-Duplex Serial Interface VCC UART IR Transceiver VC C IR TX A # TXD IR R X A # RXD D TR # NC RTS# NC VCC CTS# DSR# CD# R I# GND In frared C on nection 1.6 Device Reset The PCIRST# input resets the internal registers and the serial interface outputs to their default states. The PCIRST# assertion for general system reset may occur at any time and may be asynchronous to LCLK. 17 XR28V382 3.3V DUAL LPC UART WITH 128-BYTE FIFO REV. 1.0.2 2.0 REGISTER DETAILS The Register map of V382 is primarily divided into two sections:  Configuration Register set  UART internal Register set 2.1 Configuration Register There are two different sets of configuration registers: the Global Control Register set and the Device Configuration Register set. The Global Control Registers can be used to perform software reset, select clock input frequency, configure watchdog timer, configuration port selection and read Vendor ID and Device ID. The Device Configuration Registers configure all 2 UARTs to enable the UART channel, base address, IRQ channel, internal clock frequency, IR control, 9-bit mode slave address and FIFO mode. The watchdog timer can also be configured in the Device Configuration Registers set including enable the watchdog timer, configure base address, IRQ channel, timer count number and monitor the timer status.  Global Control Registers The Global Control Register set is the set of registers that are shared among all the devices of V382. Table 6 describes the list of all the Global Control Registers. TABLE 6: LPC BUS GLOBAL CONTROL REGISTERS ADDRESS [A7:A0] REGISTER READ/WRITE RESET STATE 0x02 Software Reset Register Read/Write 0x00 0x07 Logic Device Number Register (LDN) Read/Write 0x00 0x20 Device ID MSB Register (DEV_ID_M) Read-only 0x03 0x21 Device ID LSB Register (DEV_ID_L) Read-only 0x82 0x23 Vendor ID MSB Register (VID_M) Read-only 0x13 0x24 Vendor ID LSB Register (VID_L) Read-only 0xA8 0x25 Clock Select Register (CLKSEL) Read/Write 0x00 0x26 Watchdog Timer Control Register (WDT) Read/Write 0x00 0x27 Port Select Register Read/Write 0x00 18 XR28V382 3.3V DUAL LPC UART WITH 128-BYTE FIFO REV. 1.0.2  Device Configuration Registers The Device Configuration Register set is specific to each device of the V382. The V382 has two types of devices: 1) UART 2) Watchdog Timer. It has 2 UART devices and 1 Watchdog timer. All the UARTs have similar register set except UARTA. UARTA has an additional register to control IR function. The Device Configuration register set can be accessed through indirect addressing described in ’Section 1.1.2.3, Example’ . Table 7 lists the Device Configuration registers. TABLE 7: DEVICE CONFIGURATION REGISTERS ADDRESS [A7:A0] 0x30 UARTA (LDN=0x00) WDT (LDN=0x08) UART Enable Register (ENABLE) RESET STATE Base Address High Register Read/Write 0x61 Base Address Low Register Read/Write 0x70 IRQ Channel Select Register Read/Write 0xF0 Enhanced Multifunction Register Read/Write 0x00 0xF1 IR Control Register Read/Write 0x44 0xF4 9-bit Mode Slave Address Register Read/Write 0x00 0xF5 9-bit Mode Slave Address Mask Register Read/Write 0x00 0xF6 FIFO Mode Select Register Read/Write 0x00 UART Enable Register (ENABLE) See Table 1 ’UART Power On Configuration’ Read/Write 0x60 Base Address High Register Read/Write 0x61 Base Address Low Register Read/Write 0x70 IRQ Channel Select Register Read/Write 0xF0 Enhanced Multifunction Register Read/Write 0x00 0xF4 9-bit Mode Slave Address Register Read/Write 0x00 0xF5 9-bit Mode Slave Address Mask Register Read/Write 0x00 0xF6 FIFO Mode Select Register Read/Write 0x00 0x30 Watchdog Enable Register Read/Write 0x01 0x60 Base Address High Register Read/Write 0x04 0x61 Base Address Low Register Read/Write 0x42 0x70 IRQ Channel Select Register Read/Write 0x00 0xF0 Timer Status and Control Register Read/Write 0x02 0xF1 Timer Count Number Register Read/Write 0x0A 19 COMMENT Read/Write 0x60 0x30 UARTB (LDN=0x01) READ/WRITE REGISTER See Table 1 ’UART Power On Configuration’ See Table 1 ’UART Power On Configuration’ XR28V382 3.3V DUAL LPC UART WITH 128-BYTE FIFO 2.1.1 2.1.1.1 REV. 1.0.2 Global Control Registers Software Reset Register Software Reset resets the Device Configuration registers to their factory defaults. Strapping pins from Table 1 are not sampled during a software reset. Bit [0]: Software reset  Logic 0 = Disable software reset (default).  Logic 1 = Enable software reset. After the software reset, this bit will turn to ’0’ automatically. Bits [7:1]: Reserved 2.1.1.2 Logic Device Number Register - Read/Write This register selects device configuration register set among the 2 channel UARTs and the watchdog timer. Bits [7:0]: Select different device configuration register set.  0x00 = Select UART A device configuration register (default).  0x01 = Select UART B device configuration register.  0x08 = Select Watchdog Timer device configuration register. 2.1.1.3 Device ID MSB/LSB Register -Read only DEV_ID_M (0x20): This register provides upper byte device ID for XR28V382. The default value is 0x03. DEV_ID_L (0x21): This register provides lower byte device ID for XR28V382. The default value is 0x82. 2.1.1.4 Vendor ID MSB/LSB Register -Read only VID_M (0x23): This register value provides upper byte of Exar’s Vendor ID. The default value is 0x13. VID_L (0x24): This register value provides lower byte of Exar’s Vendor ID. The default value is 0xA8. 2.1.1.5 Clock Select Register - Read/Write This register selects the clock frequency. Bit [0]: Clock select  Logic 0 = The CLKIN is 24 MHz (default).  Logic 1 = The CLKIN is 48 MHz. Bits [7:1]: Reserved 2.1.1.6 Watchdog Timer Control Register - Read/Write This register controls the watchdog timer. Bit [0]: Assert a low pulse from WDTOUT#/PS_WDT pin  Logic 0 = Watchdog timer (WDT) will assert a low pulse from WDTOUT#/PS_WDT pin (default).  Logic 1 = Watchdog timer (WDT) will not assert a low pulse from WDTOUT#/PS_WDT pin, but the timeout status will be set. Bit [1]: Restart timer  Logic 0 = Read watchdog timer (WDT) will restart the timer (default).  Logic 1 = Read watchdog timer (WDT) will not restart the timer. Bits [7:2]: Reserved 20 XR28V382 3.3V DUAL LPC UART WITH 128-BYTE FIFO REV. 1.0.2 2.1.1.7 Port Select Register - Read/Write This register selects the configuration port. Bits [1:0]: Select configuration entry key The default value of these bits are determined by RTSB#/PS_CONF_KEY1/RS485 and IRTXA#/ PS_CONF_KEY0. See Table 3 ’Configuration Entry Key’.  ’00’ = The entry key is 0x77.  ’01’ = The entry key is 0xA0.  ’10’ = The entry key is 0x87.  ’11’ = The entry key is 0x67. Bits [3:2]: Reserved Bit [4]: Select configuration port The default value of this bit is determined by RTSA#/PS_CONF_2E/RS485 pin. See Table 2 ’Configuration Port Selection’.  Logic 0 = The configuration port is 0x2E/0x2F.  Logic 1 = The configuration port is 0x4E/0x4F. Bits [7:5]: Reserved 2.1.2 Device Configuration Registers In order to access Device Configuration Register set, the configuration regsiter access mode has to be enabled. The value in the LDN register determines which device’s configuration register set to access. Example: if LDN register = 0x01, modifying UART Enable Register (0x30) will modify UART Enable Register of channel B. 2.1.2.1 2.1.2.1.1 UART Registers UART Enable Register (ENABLE) - Read/Write This register enables/disables the UART selected in the LDN register. Bit [0]: Enable/Disable UART The default value of this bit is determined by the strapping options. See Table 1 ’UART Power On Configuration’. This bit can be programmed after power up.  Logic 0 = Disable the UART selected in LDN register.  Logic 1 = Enable the UART selected in LDN register. Bits [7:1]: Reserved 2.1.2.1.2 Base Address High/Low Register - Read/Write The V382 provides programmable I/O mapped address feature. Configure the MSB/LSB of 16-bit I/O address, for the UART selected in LDN register, in this register. Bits [7:0]: MSB of UART base address (0x60) The default value of this register is determined by the strapping options. See Table 1 ’UART Power On Configuration’. Bits [7:0]: LSB of UART base address (0x61) The default value of this register is determined by the strapping options. See Table 1 ’UART Power On Configuration’. 21 XR28V382 3.3V DUAL LPC UART WITH 128-BYTE FIFO 2.1.2.1.3 REV. 1.0.2 IRQ Channel Select Register - Read/Write The V382 supports different IRQ channels and modes. The IRQ modes and IRQ channel number for each device of V382 should be programmed in their respective IRQ Channel Selelct register. Each device of V382 can have same/different IRQ channel. Bits [3:0]: Select the IRQ channel The default values of these bits is determined by the strapping options See Table 1 ’UART Power On Configuration’. They can also be configured via software after power on. Bit [4]: Enable/Disable the IRQ Sharing mode  Logic 0 = Disable the IRQ sharing mode (default). The IRQ channel must be different for each UART for proper behavior.  Logic 1 = Enable the IRQ sharing mode. The IRQ channel (bits 3-0) can be different or be the same as the other UARTs. Bits [6:5]: IRQ Sharing mode These two bits are effective only when IRQ sharing mode is enabled (bit[4] = ’1’). The SERIRQ time slot is specified by bits 3-0. An interrupt will only appear on the SERIRQ pin during that time slot if MCR[3] = ’1’.  ’00’ = The IRQ Sharing mode is active LOW level (default). There will be an active low pulse continuously on the SERIRQ pin until the interrupt has been cleared.  ’01’ = The IRQ Sharing mode is active LOW edge. When there is an interrupt, there will be a single active low pulse on the SERIRQ pin.  ’10’ = The IRQ Sharing mode is active HIGH level. There will be an active high pulse continuously on the SERIRQ pin until the interrupt has been cleared.  ’11’ = Reserved. Bit [7]: Reserved 2.1.2.1.4 Enhanced Multifunction Register - Read/Write This register enables/disables the RS-485 mode, 9-bit mode, selects clock frequency and delay in the IR mode. Bits [1:0]: Internal clock frequency The V382 provides an option to select among various internal clock frequency, which is used to generate different baud values. The value of the internal clock frequency is dependent on external clock provided to the CLKIN pin and setting of Clock Select Register - Read/Write. Table 8 describes various possible internal clock frequencies derived from 24MHz/48MHz external clock. TABLE 8: INTERNAL CLOCK FREQUENCY (MHZ) BITS[1:0] EXTERNAL CLOCK = 24MHZ EXTERNAL CLOCK = 48MHZ CLKSEL=0X0 CLKSEL=0X1 CLKSEL=0X0 CLKSEL =0X1 00 1.8462 0.9231 3.6923 1.8462 01 18 9 36 18 10 24 12 48 24 11 14 7 28 14 See ’Section 1.4.1.1, Programmable Baud Rate Generator’. 22 XR28V382 3.3V DUAL LPC UART WITH 128-BYTE FIFO REV. 1.0.2 Bit [2]: IR mode TX Delay  Logic 0 = TX transmits data immedately when changing from RX to TX (default).  Logic 1 = TX delays 4 character time when changing from RX to TX. Bit [3]: IR mode RX Delay  Logic 0 = RX is enabled immediately after TX is idle (default).  Logic 1 = RX is disabled for 4 character time after TX is idle. Bit [4]: Enable/Disable Auto RS-485 Half-Duplex Control mode  Logic 0 = Disable the Auto RS-485 Half-Duplex Control mode (default). The RTS#/RS485 pin can be controlled by MCR bit-1.  Logic 1 = Enable the Auto RS-485 Half-Duplex Control mode. The RTS#/RS485 signal polarity is determined by the bit-5. Bit [5]: Invert the RTS#/RS485 signal polarity for RS-485 Half-Duplex Control mode  Logic 0 = RTS#/RS485 signal polarity is HIGH for transmission and LOW for reception (default).  Logic 1 = RTS#/RS485 signal polarity is inverted (that is, LOW for transmission and HIGH for reception). Bit [6]: Auto Address Detection  Logic 0 = All bytes received will be loaded into RX FIFO. See ’Section 1.4.4, Auto RS-485 Half-Duplex Control’.  Logic 1 = All bytes received after address byte that matches the given address or broadcast address (determined by the 9-bit mode slave address register and 9-bit mode slave address mask register) will be loaded into RX FIFO. See ’Section 1.4.5.1, Auto Address Detection’. Bit [7]: Enable/Disable the 9-bit Mode  Logic 0 = Disable the 9-bit mode (default).  Logic 1 = Enable the 9-bit mode (multi-drop mode). In the 9-bit mode, the parity bit becomes the address/data bit.See ’Section 1.4.5, Normal Multidrop (9-bit) Mode’. 2.1.2.1.5 Infrared Mode Control Register - Read/Write The V382 supports IR mode for UART channel A only. It controls infrared mode by setting this register. See ’Section 1.4.6, Infrared Mode’. Bit [0]: IR mode IRRXA# invert  Logic 0 = IRRA# idles LOW. (Default)  Logic 1 = Invert the IRRXA# for IR mode, idle at HIGH. Bit [1]: IR mode IRTXA# invert  Logic 0 = IRTXA# idles LOW. (Default)  Logic 1 = Invert the IRTXA# for IR mode, idle at HIGH. Bit [2]: IR mode Half-Duplex  Logic 0 = Enable full duplex function for IR mode.  Logic 1 = Enable half duplex function for IR mode (default). 23 XR28V382 3.3V DUAL LPC UART WITH 128-BYTE FIFO REV. 1.0.2 Bits [4:3]: IR mode Enable  ’00’ or ’01’ = Disable the IR function (default value is ’00’).  ’10’ = Enable the IR function, active pulse is 1.6 us.  ’11’ = Enable the IR function, active pulse is 3/16 bit time. Bits [7:5]: Reserved 2.1.2.1.6 9-bit Mode Slave Address Register - Read/Write This register indicates the slave address in 9-bit mode. This register along with the 9-bit mode slave address mask register will determine the given address and broadcast address in 9-bit mode. The V382 will respond to both the given address and the broadcast address. 2.1.2.1.7 9-bit Mode Slave Address Mask Register - Read/Write This register indicates the slave address mask in 9-bit mode. This register along with the 9-bit mode slave address register will determine the given address and broadcast address in 9-bit mode. The V382 will respond to both the given address and the broadcast address.  Given address: If bit n of the 9-bit mode slave address mask register is ’0’, then the corresponding bit of given address is ’do not care’.  Broadcast address: If bit n of the ORed 9-bit mode slave address register and 9-bit mode slave address mask register is ’0’, then this bit n is a ’do not care’ bit. The remaining bit which is ’1’ is compared to the received address. TABLE 9: EXAMPLE REGISTER EXAMPLE 1 EXAMPLE 2 EXAMPLE 3 EXAMPLE 4 9-bit mode slave address register (0xF4) 11110100 00001111 01010101 11100111 9-bit mode slave address mask register (0xF5) 01010101 10101010 11111111 00001111 Given address x1x1x1x0 0x0x1x1x 01010101 xxxx0111 Broadcast address 1111x1x1 1x1x1111 11111111 111x1111 2.1.2.1.8 FIFO Mode Select Register - Read/Write This register selects FIFO depth and receiver trigger levels. Bits [1:0]: FIFO size for TX/RX  ’00’ = FIFO size is 16 bytes.  ’01’ = FIFO size is 32 bytes.  ’10’ = FIFO size is 64 bytes.  ’11’ = FIFO size is 128 bytes. Bits [3:2]: Reserved Bits [5:4]: RX trigger level  ’00’ = RX trigger level is 1, 4, 8, 14 (See Table 13 ’Receive FIFO Trigger Level Selection’).  ’01’ = RX trigger level is 2, 8, 16, 28 (See Table 13 ’Receive FIFO Trigger Level Selection’).  ’10’ = RX trigger level is 4, 16, 32, 56 (See Table 13 ’Receive FIFO Trigger Level Selection’).  ’11’ = RX trigger level is 8, 32, 64, 112 (See Table 13 ’Receive FIFO Trigger Level Selection’). Note: for Bits[5:4]= ’01’,’10’ and ’11’ make sure correct FIFO size is programmed in Bits[1:0]. 24 XR28V382 3.3V DUAL LPC UART WITH 128-BYTE FIFO REV. 1.0.2 Bit [6]: Reserved Bit [7]: TX holding register (THR) empty delay  Logic 0 = No delay for THR empty interrupt (default).  Logic 1 = Delay 1 transmission clock for THR empty interrupt. 2.1.2.2 2.1.2.2.1 Watchdog Timer Registers (LDN = 0x08) WDT Enable Register - Read/Write Bit [0]: WDT Enable/Disable  Logic 0 = Disable the Watchdog Timer.  Logic 1 = Enable the Watchdog Timer. After power on or reset, if the pin WDTOUT#/PS_WDT is sampled HIGH, this bit will be set to ’1’. Otherwise, this bit will be set to ’0’. See Table 1 ’UART Power On Configuration’. Bits [7:1]: Reserved 2.1.2.2.2 WDT Base Address High/Low Register - Read/Write This register indicates the MSB/LSB of watchdog timer base address. Bits [7:0]: The MSB of watchdog timer base address (0x60). After power on or reset, if the pin WDTOUT#/PS_WDT is sampled HIGH, this byte will be set to 0x04. Otherwise, this bit will be set to 0x00. See Table 1 ’UART Power On Configuration’. Bits [7:0]: The LSB of watchdog timer base address (0x61) . After power on or reset, if the pin WDTOUT#/PS_WDT is sampled HIGH, this byte will be set to 0x42. Otherwise, this byte will be set to 0x0. See Table 1 ’UART Power On Configuration’. 2.1.2.2.3 WDT IRQ Channel Select Register - Read/Write This register enables / disables an interrupt request output from the watchdog timer. Bits [3:0]: Select the IRQ channel for watchdog timer After power on or reset, if the pin WDTOUT#/PS_WDT is sampled HIGH, this byte will be set to 0x00. Otherwise, this byte will be set to 0x0. See Table 1 ’UART Power On Configuration’. Bit [4]: Enable/Disable the watchdog timer IRQ  Logic 0 = Disable the watchdog timer IRQ (default).  Logic 1 = Enable the watchdog timer IRQ. Bits [7:5]: Reserved 2.1.2.2.4 WDT Timer Status and Control Register - Read/Write This register sets timer status and control timer events. Bit [0]: Time Out Events  Logic 0 = No time out occurred (default).  Logic 1 = Time out occurred. Write ’1’ to this bit will clear the status. 25 XR28V382 3.3V DUAL LPC UART WITH 128-BYTE FIFO REV. 1.0.2 Bits [2:1]: WDT Interval  ’00’ = Timer unit is 10 ms.  ’01’ = Timer unit is 1 second.  ’10’ = Timer unit is 1 minute.  ’11’ = Reserved. Bits [7:3]: Reserved 2.1.2.2.5 WDT Count Register - Read/Write This register programs the count value for watchdog timer. Bits [7:0]: Sets count value for watchdog timer Writing a non-zero value to this register once will disable the timer and writing the same value again will enable the timer. After power on or reset, if the pin WDTOUT#/PS_WDT is sampled HIGH, this byte will be set to 0x0A. Otherwise, this byte will be set to 0x00. See Table 1 ’UART Power On Configuration’. 2.2 UART Internal Registers The UART register set for the V382 is shown in Table 10 and Table 11. TABLE 10: UART INTERNAL REGISTERS OFFSET ADDRESSES RESET STATE REGISTER COMMENTS 16C550 COMPATIBLE REGISTERS 0x0 DLL - Divisor LSB Register 0x01 0x1 DLM - Divisor MSB Register 0x00 0x0 RHR - Receive Holding Register THR - Transmit Holding Register 0xXX 0xXX 0x1 IER - Interrupt Enable Register 0x00 0x2 ISR - Interrupt Status Register FCR - FIFO Control Register 0x01 0x00 0x3 LCR - Line Control Register 0x00 0x4 MCR - Modem Control Register 0x00 0x5 LSR - Line Status Register 0x60 0x6 Bits 3:0 = 0 Bts 7-4 = Logic Levels of the inputs inverted MSR - Modem Status Register 0x7 SPR - Scratch Pad Register 0x00 26 LCR[7] = 1 LCR[7] = 0 XR28V382 3.3V DUAL LPC UART WITH 128-BYTE FIFO REV. 1.0.2 TABLE 11: UART INTERNAL REGISTER OFFSET ADDRESS REG NAME READ/ WRITE BIT-7 BIT-6 BIT-5 BIT-4 BIT-3 BIT-2 BIT-1 BIT-0 COMMENT 16C550 Compatible Registers 0x0 RHR RD Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 0x0 THR WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 0x1 IER RD/WR 0 0 0 0 LCR[7] = 0 Modem RX Line TX RX Stat. Int. Stat. Empty Data Enable Int. Int Int. Enable Enable Enable 0x2 ISR RD FIFOs FIFOs Enabled Enabled 0 0 INT Source Bit-3 0x2 FCR WR RX FIFO RX FIFO Trigger Trigger 0 0 0 TX FIFO Reset RX FIFO Reset 0x3 LCR RD/WR Divisor Enable Set TX Break Set Parity Even Parity Parity Enable Stop Bits Word Word Length Length Bit-1 Bit-0 0x4 MCR RD/WR 0 0 0 Internal Enable OP1# Lopback Interrupts/ Enable OP2# RTS# DTR# Output Output Control Control 0x5 LSR RD RX FIFO Global Error THR & TSR Empty THR Empty RX Break RX Framing Error RX Parity Error RX Overrun Error RX Data Ready 0x6 MSR RD CD# Input RI# Input DSR# Input CTS# Input Delta CD# Delta RI# Delta DSR# Delta CTS# 0x7 SPR RD/WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 INT INT INT Source Source Source Bit-2 Bit-1 Bit-0 FIFOs Enable Baud Rate Generator Divisor 0x0 DLL RD/WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 0x1 DLM RD/WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 27 LCR[7] = 1 XR28V382 3.3V DUAL LPC UART WITH 128-BYTE FIFO 2.2.1 2.2.1.1 REV. 1.0.2 UART Internal Register Descriptions Receive Holding Register (RHR) - Read- Only SEE”RECEIVER” ON PAGE 11. 2.2.1.2 Transmit Holding Register (THR) - Write-Only SEE”TRANSMITTER” ON PAGE 10. 2.2.1.3 Interrupt Enable Register (IER) - Read/Write The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR). 2.2.1.3.1 IER versus Receive FIFO Interrupt Mode Operation When the receive FIFO (FCR BIT-0 = 1) and receive interrupts (IER BIT-0 = 1) are enabled, the RHR interrupts (see ISR bits 2 and 3) status will reflect the following: A. The receive data available interrupts are issued to the host when the FIFO has reached the programmed trigger level. It will be cleared when the FIFO drops below the programmed trigger level. B. FIFO level will be reflected in the ISR register when the FIFO trigger level is reached. Both the ISR register status bit and the interrupt will be cleared when the FIFO drops below the trigger level. C. The receive data ready bit (LSR BIT-0) is set as soon as a character is transferred from the shift register to the receive FIFO. It is reset when the FIFO is empty. 2.2.1.3.2 IER versus Receive/Transmit FIFO Polled Mode Operation When FCR BIT-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the XR28V382 in the FIFO polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). A. LSR BIT-0 indicates there is data in RHR or RX FIFO. B. LSR BIT-1 indicates an overrun error has occurred and that data in the FIFO may not be valid. C. LSR BIT 2-4 provides the type of receive data errors encountered for the data byte in RHR, if any. D. LSR BIT-5 indicates THR is empty. E. LSR BIT-6 indicates when both the transmit FIFO and TSR are empty. F. LSR BIT-7 indicates a data error in at least one character in the RX FIFO. IER[0]: RHR Interrupt Enable The receive data ready interrupt will be issued when RHR has a data character in the non-FIFO mode or when the receive FIFO has reached the programmed trigger level in the FIFO mode.  Logic 0 = Disable the receive data ready interrupt (default).  Logic 1 = Enable the receiver data ready interrupt. IER[1]: THR Interrupt Enable This bit enables the Transmit Ready interrupt which is issued whenever the THR becomes empty. If the THR is empty when this bit is enabled, an interrupt will be generated.  Logic 0 = Disable Transmit Ready interrupt (default).  Logic 1 = Enable Transmit Ready interrupt. 28 XR28V382 3.3V DUAL LPC UART WITH 128-BYTE FIFO REV. 1.0.2 IER[2]: Receive Line Status Interrupt Enable If any of the LSR register bits 1, 2, 3 or 4 is a logic 1, it will generate an interrupt to inform the host controller about the error status of the current data byte in FIFO. LSR bit-1 generates an interrupt immediately when an overrun occurs. LSR bits 2-4 generate an interrupt when the character in the RHR has an error.  Logic 0 = Disable the receiver line status interrupt (default).  Logic 1 = Enable the receiver line status interrupt. IER[3]: Modem Status Interrupt Enable  Logic 0 = Disable the modem status register interrupt (default).  Logic 1 = Enable the modem status register interrupt. IER[7:4]: Reserved 2.2.1.4 Interrupt Status Register (ISR) - Read-Only The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the ISR will give the user the current highest pending interrupt level to be serviced, others are queued up to be serviced next. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt Source Table, Table 12, shows the data values (bit 0-3) for the interrupt priority levels and the interrupt sources associated with each of these interrupt levels. 2.2.1.4.1 Interrupt Generation:  LSR is by any of the LSR bits 1, 2, 3 and 4.  RXRDY Data Ready is by RX trigger level.  RXRDY Data Time-out is by a 4-char plus 12 bits delay timer.  TXRDY is by TX FIFO empty.  MSR is by any of the MSR bits 0, 1, 2 and 3. 2.2.1.4.2 Interrupt Clearing:  LSR interrupt is cleared by a read to the LSR register.  RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level.  RXRDY Time-out interrupt is cleared by reading RHR.  TXRDY interrupt is cleared by a read to the ISR register or writing to THR.  MSR interrupt is cleared by a read to the MSR register. ] TABLE 12: INTERRUPT SOURCE AND PRIORITY LEVEL PRIORITY ISR REGISTER STATUS BITS SOURCE OF INTERRUPT LEVEL BIT-3 BIT-2 BIT-1 BIT-0 1 0 1 1 0 LSR (Receiver Line Status Register) 2 1 1 0 0 RXRDY (Receive Data Time-out) 3 0 1 0 0 RXRDY (Received Data Ready) 4 0 0 1 0 TXRDY (Transmit Ready) 5 0 0 0 0 MSR (Modem Status Register) - 0 0 0 1 None (default) 29 XR28V382 3.3V DUAL LPC UART WITH 128-BYTE FIFO REV. 1.0.2 ISR[0]: Interrupt Status  Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt service routine.  Logic 1 = No interrupt pending (default condition). ISR[3:1]: Interrupt Status These bits indicate the source for a pending interrupt at interrupt priority levels (See Interrupt Source Table 12). ISR[4]: Reserved ISR[5]: Reserved ISR[7:6]: FIFO Enable Status These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are enabled. 2.2.1.5 FIFO Control Register (FCR) - Write-Only This register is used to enable the FIFOs, clear the FIFOs, and set the receive FIFO trigger levels. The FIFO mode is defined as follows: FCR[0]: TX and RX FIFO Enable  Logic 0 = Disable the transmit and receive FIFO (default).  Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are written or they will not be programmed. See FIFO Mode Select Register - Read/Write bit [1:0] for FIFO size selection. FCR[1]: RX FIFO Reset This bit is only active when FCR bit-0 is a ‘1’.  Logic 0 = No receive FIFO reset (default).  Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not cleared or altered). This bit will return to a logic 0 after resetting the FIFO. FCR[2]: TX FIFO Reset This bit is only active when FCR bit-0 is a ‘1’.  Logic 0 = No transmit FIFO reset (default).  Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not cleared or altered). This bit will return to a logic 0 after resetting the FIFO. FCR[5:3]: Reserved 30 XR28V382 3.3V DUAL LPC UART WITH 128-BYTE FIFO REV. 1.0.2 FCR[7:6]: Receive FIFO Trigger Select (logic 0 = default, RX trigger level =1). These 2 bits are used to set the trigger level for the receive FIFO. The UART will issue a receive interrupt when the number of the characters in the FIFO crosses the trigger level. Table 13 shows the complete selections. TABLE 13: RECEIVE FIFO TRIGGER LEVEL SELECTION FIFO MODE SELECT REGISTER BIT-5 0 0 1 1 2.2.1.6 FCR BIT-7 FCR BIT-6 RECEIVE TRIGGER LEVEL 0 0 0 1 1 0 1 0 1 1 (default) 4 8 14 1 0 0 1 1 0 1 0 1 2 8 16 28 0 0 0 1 1 0 1 0 1 4 16 32 56 1 0 0 1 1 0 1 0 1 8 32 64 112 BIT-4 Line Control Register (LCR) - Read/Write The Line Control Register is used to specify the asynchronous data communication format. The word or character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. LCR[1:0]: TX and RX Word Length Select These two bits specify the word length to be transmitted or received. BIT-1 BIT-0 WORD LENGTH 0 0 5 (default) 0 1 6 1 0 7 1 1 8 31 XR28V382 3.3V DUAL LPC UART WITH 128-BYTE FIFO REV. 1.0.2 LCR[2]: TX and RX Stop-bit Length Select The length of stop bit is specified by this bit in conjunction with the programmed word length. LENGTH STOP BIT LENGTH (BIT TIME(S)) 0 5,6,7,8 1 (default) 1 5 1-1/2 1 6,7,8 2 WORD BIT-2 LCR[3]: TX and RX Parity Select Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data integrity check. See Table 14 for parity selection summary below.  Logic 0 = No parity.  Logic 1 = A parity bit is generated during the transmission while the receiver checks for parity error of the data character received. LCR[4]: TX and RX Parity Select If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR BIT-4 selects the even or odd parity format.  Logic 0 = ODD Parity is generated by forcing an odd number of logic 1’s in the transmitted character. The receiver must be programmed to check the same format (default).  Logic 1 = EVEN Parity is generated by forcing an even number of logic 1’s in the transmitted character. The receiver must be programmed to check the same format. LCR[5]: TX and RX Parity Select If the parity bit is enabled, LCR BIT-5 selects the forced parity format.  LCR BIT-5 = logic 0, parity is not forced (default).  LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit is forced to HIGH for the transmit and receive data.  LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit is forced to LOW for the transmit and receive data. TABLE 14: PARITY SELECTION LCR BIT-5 LCR BIT-4 LCR BIT-3 PARITY SELECTION X X 0 No parity 0 0 1 Odd parity 0 1 1 Even parity 1 0 1 Force parity to mark, HIGH 1 1 1 Forced parity to space, LOW LCR[6]: Transmit Break Enable When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a “space’, logic 0, state). This condition remains, until disabled by setting LCR bit-6 to a logic 0.  Logic 0 = No TX break condition. (default).  Logic 1 = Forces the transmitter output (TX) to a “space”, logic 0, for alerting the remote receiver of a line break condition. 32 XR28V382 3.3V DUAL LPC UART WITH 128-BYTE FIFO REV. 1.0.2 LCR[7]: Baud Rate Divisors Enable Baud rate generator divisor (DLL/DLM) enable.  Logic 0 = Data registers are selected (default).  Logic 1 = Divisor latch registers are selected. 2.2.1.7 Modem Control Register (MCR) or General Purpose Outputs Control - Read/Write The MCR register is used for controlling the serial/modem interface signals or general purpose inputs/outputs. MCR[0]: DTR# Output The DTR# pin is a modem control output. If the modem interface is not used, this output may be used as a general purpose output.  Logic 0 = Force DTR# output HIGH (default).  Logic 1 = Force DTR# output LOW. MCR[1]: RTS# Output The RTS# pin is a modem control output. If the modem interface is not used, this output may be used as a general purpose output.  Logic 0 = Force RTS# output HIGH (default).  Logic 1 = Force RTS# output LOW. MCR[2]: Reserved OP1# is not available as an output pin on the V382. But it is available for use during Internal Loopback Mode. In the Loopback Mode, this bit is used to write the state of the modem RI# interface signal. MCR[3]: Enable interrupts on SERIRQ / OP2# Enable or disable Interrupt outputs.  Logic 0 = Interrupts will not appear on SERIRQ pin.  Logic 1 = If enabled in IER, interrupting condition will appear on SERIRQ pin. In internal loopback mode (MCR[4] = ’1’), this bit controls the OP2# signal. See ’Section 1.4.7, Internal Loopback’. MCR[4]: Internal Loopback Enable  Logic 0 = Disable loopback mode (default).  Logic 1 = Enable local loopback mode, see loopback section and Figure 8. MCR[7:5]: Reserved 2.2.1.8 Line Status Register (LSR) - Read-Only The LSR provides the status of data transfers between the UART and the host. If IER bit-2 is enabled, LSR bit1 will generate an interrupt immediately and LSR bits 2-4 will generate an interrupt when a character with an error is in the RHR. LSR[0]: Receive Data Ready Indicator  Logic 0 = No data in receive holding register or FIFO (default).  Logic 1 = Data has been received and is saved in the receive holding register or FIFO. 33 XR28V382 3.3V DUAL LPC UART WITH 128-BYTE FIFO REV. 1.0.2 LSR[1]: Receiver Overrun Flag  Logic 0 = No overrun error (default).  Logic 1 = Overrun error. A data overrun error condition occurred in the receive shift register. This happens when additional data arrives while the FIFO is full. In this case the previous data in the receive shift register is overwritten. Note that under this condition the data byte in the receive shift register is not transferred into the FIFO, therefore the data in the FIFO is not corrupted by the error. LSR[2]: Receive Data Parity Error Tag  Logic 0 = No parity error (default).  Logic 1 = Parity error. The receive character in RHR does not have correct parity information and is suspect. This error is associated with the character available for reading in RHR. LSR[3]: Receive Data Framing Error Tag  Logic 0 = No framing error (default).  Logic 1 = Framing error. The receive character did not have a valid stop bit(s). This error is associated with the character available for reading in RHR. LSR[4]: Receive Break Tag  Logic 0 = No break condition (default).  Logic 1 = The receiver received a break signal (RX was LOW for at least one character frame time). In the FIFO mode, only one break character is loaded into the FIFO. The break indication remains until the RX input returns to the idle condition, “mark” or HIGH. LSR[5]: Transmit Holding Register Empty Flag This bit is the Transmit Holding Register Empty indicator. The THR bit is set to a logic 1 when the last data byte is transferred from the transmit holding register to the transmit shift register. The bit is reset to logic 0 concurrently with the data loading to the transmit holding register by the host. In the FIFO mode this bit is set when the transmit FIFO is empty, it is cleared when the transmit FIFO contains at least 1 byte. LSR[6]: THR and TSR Empty Flag This bit is set to a logic 1 whenever the transmitter goes idle. It is set to logic 0 whenever either the THR or TSR contains a data character. In the FIFO mode this bit is set to a logic 1 whenever the transmit FIFO and transmit shift register are both empty. LSR[7]: Receive FIFO Data Error Flag  Logic 0 = No FIFO error (default).  Logic 1 = A global indicator for the sum of all error bits in the RX FIFO. At least one parity error, framing error or break indication is in the FIFO data. This bit clears when there is no more error(s) in any of the bytes in the RX FIFO. 2.2.1.9 Modem Status Register (MSR) - Read-Only The MSR provides the current state of the modem interface input signals. Lower four bits of this register are used to indicate the modified information. These bits are set to a logic 1 whenever a signal from the modem changes state. These bits may be used for general purpose inputs when they are not used with modem signals. MSR[0]: Delta CTS# Input Flag  Logic 0 = No change on CTS# input (default).  Logic 1 = The CTS# input has changed state since the last time it was monitored. A modem status interrupt will be generated if MSR interrupt is enabled (IER bit-3). 34 XR28V382 3.3V DUAL LPC UART WITH 128-BYTE FIFO REV. 1.0.2 MSR[1]: Delta DSR# Input Flag  Logic 0 = No change on DSR# input (default).  Logic 1 = The DSR# input has changed state since the last time it was monitored. A modem status interrupt will be generated if MSR interrupt is enabled (IER bit-3). MSR[2]: Delta RI# Input Flag  Logic 0 = No change on RI# input (default).  Logic 1 = The RI# input has changed from LOW to HIGH, ending of the ringing signal. A modem status interrupt will be generated if MSR interrupt is enabled (IER bit-3). MSR[3]: Delta CD# Input Flag  Logic 0 = No change on CD# input (default).  Logic 1 = Indicates that the CD# input has changed state since the last time it was monitored. A modem status interrupt will be generated if MSR interrupt is enabled (IER bit-3). MSR[4]: CTS Input Status Normally MSR bit-4 bit is the compliment of the CTS# input. However in the loopback mode, this bit is equivalent to the RTS# bit in the MCR register. The CTS# input may be used as a general purpose input when the modem interface is not used. MSR[5]: DSR Input Status Normally this bit is the complement of the DSR# input. In the loopback mode, this bit is equivalent to the DTR# bit in the MCR register. The DSR# input may be used as a general purpose input when the modem interface is not used. MSR[6]: RI Input Status Normally this bit is the complement of the RI# input. In the loopback mode this bit is equivalent to bit-2 in the MCR register. The RI# input may be used as a general purpose input when the modem interface is not used. MSR[7]: CD Input Status Normally this bit is the complement of the CD# input. In the loopback mode this bit is equivalent to bit-3 in the MCR register. The CD# input may be used as a general purpose input when the modem interface is not used. 2.2.1.10 Scratch Pad Register (SPR) - Read/Write This is a 8-bit general purpose register for the user to store temporary data. 2.2.1.11 Baud Rate Generator Registers (DLL and DLM) - Read/Write These registers make-up the value of the baud rate divisor. The concatenation of the contents of DLM and DLL gives the 16-bit divisor value. 35 XR28V382 3.3V DUAL LPC UART WITH 128-BYTE FIFO REV. 1.0.2 ABSOLUTE MAXIMUM RATINGS Power Supply Range 4 Volts Voltage at Any Pin 6V Operating Temperature -40o to +85oC Storage Temperature -65o to +150oC Package Dissipation 500 mW ELECTRICAL CHARACTERISTICS DC ELECTRICAL CHARACTERISTICS UNLESS OTHERWISE NOTED: TA = -40O TO +85OC, VCC IS 3.3V ± 10% SYMBOL LIMITS 3.3V MIN MAX PARAMETER UNITS VIL Input Low Voltage -0.5 0.8 V VIH Input High Voltage 2.0 5.5 V 0.4 V VOL VOH VOL VOL VOH Output Low Voltage Output High Voltage IOL = 16 mA SERIRQ, LAD[3:0] 2.4 V IOH = -16 mA SERIRQ, LAD[3:0] 0.4 Output Low Voltage V IOL = 12 mA WDTOUT#/PS_WDT 0.4 Output Low Voltage Output High Voltage CONDITIONS V IOL = 8 mA All other ouputs 2.4 V IOH = -8 mA All other ouputs IIL Input Low Leakage Current -10 uA IIH Input High Leakage Current 10 uA IIL Input Low Leakage Current -110 uA IIH Input High Leakage Current 60 uA CIN Input Pin Capacitance 10 pF ICC Power Supply Current 12 mA RINT Internal pull-up resistor 110 kΩ 37 36 Pins without internal pull-up resistor. Pins with internal pullup resistor. XR28V382 3.3V DUAL LPC UART WITH 128-BYTE FIFO REV. 1.0.2 AC ELECTRICAL CHARACTERISTICS UNLESS OTHERWISE NOTED: TA = -40O TO +85OC, VCC IS 3.3V ± 10% - LIMITS 3.3V ± 10% MAX MIN PARAMETER SYMBOL External Clock 48 UNIT NOTES MHz CLKIN FIGURE 11. LPC TIMING DIAGRAM 4 nSec (max) 11 nSec (min) 4 nSec (max) 11 nSec (min) 2.4 V 2.0 V p-t-p (minimum) LCLK 0.4 V Tvalid (2-11 nSec) Bused Signal Output Delay Ton (2 nSec min) Tri-State Output Toff (28 nSec Max) Tsetup (7 nSec min) Thold (0 nSec) Bused Signal Input Inputs Valid lpc_clk 37 XR28V382 3.3V DUAL LPC UART WITH 128-BYTE FIFO REV. 1.0.2 MECHANICAL DIMENSIONS Top View Bottom View Side View Drawing No: Revision: Note: QFN32 theta ja = 30.1 OC/W, theta jc = 10.1 OC/W. All values are typical. 38 POD-00000037 B XR28V382 3.3V DUAL LPC UART WITH 128-BYTE FIFO REV. 1.0.2 RECOMMENDED LAND PATTERN AND STENCIL Drawing No: Revision: 39 POD-00000037 B XR28V382 3.3V DUAL LPC UART WITH 128-BYTE FIFO REV. 1.0.2 REVISION HISTORY DATE REVISION DESCRIPTION November 2013 1.0.0 Released Datasheet December 2013 1.0.1 Updated Package drawing March 2018 1.0.2 Updated to MaxLinear logo. Updated format and Ordering Information. Corporate Headquarters: High Performance Analog: 5966 La Place Court 1060 Rincon Circle Suite 100 San Jose, CA 95131 Carlsbad, CA 92008  Tel.: +1 (669) 265-6100 Tel.:+1 (760) 692-0711 Fax: +1 (669) 265-6101 Fax: +1 (760) 444-8598 Email: uarttechsupport@exar.com www.maxlinear.com www.exar.com The content of this document is furnished for informational use only, is subject to change without notice, and should not be construed as a commitment by MaxLinear, Inc.. MaxLinear, Inc. assumes no responsibility or liability for any errors or inaccuracies that may appear in the informational content contained ion this guide. Complying with all applicable copyright laws is the responsibility of the user.. Without limiting the rights under copyright, no part of this document may be reproduced into, stored in, or introduced into a retrieval system, or transmitted in any form or by any means (electronic, mechanical, photocopying, recording, or otherwise), or for any purpose, without the express written permission of MaxLinear, Inc. MaxLinear, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless MaxLinear, Inc. receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of MaxLinear, Inc. is adequately protected under the circumstances. MaxLinear, Inc. may have patents, patent applications, trademarks, copyrights, or other intellectual property rights covering subject matter in this document. Except as expressly provided in any written license agreement from MaxLinear, Inc., the furnishing of this document does not give you any license to these patents, trademarks, coprights, or other intellectual property. Company and product names may be registered trademarks or trademarks of the respective owners with which they are associated. © 2013 - 2018 MaxLinear, Inc. All rights reserved. 40
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