XR77103-A0R5
Universal PMIC 3-Output Buck Regulator
Description
The XR77103-A0R5 universal PMIC features three 2A synchronous
high-efficiency, buck regulators with integrated power switches. They
can operate in 5V, 9V and 12V powered systems with minimal required
external component thus providing the smallest size solution possible.
Two of the outputs may be paralleled for output currents up to 5A peak
with steady state current of up to 4A.
The output voltage of each converter can be adjusted by external
resistor divider down to voltage as low as 0.8V. With a nominal switching
frequency of 500kHz, the regulators can also be synchronized to an
external clock in applications where EMI control is critical.
XR77103-A0R5 features a supervisor circuit that monitors each
converter output. PGOOD pin is asserted once sequencing is done,
outputs are reported in regulation and the reset timer expires.
The polarity of the signal is active high. A pulse skipping mode (PSM)
reduces switching losses maintaining high efficiency when the system
is unloaded or in standby mode.
REV1D
FEATURES
■■ 4.5V to 14V wide input supply
voltage range
■■ Built-in MOSFET and synchronous rectifier
■■ 0.8V, high accuracy reference (1%)
■■ Current-mode control with simple
compensation circuit
■■ External synchronization
■■ Power good
■■ Protection
Thermal shutdown
Overvoltage transient protection
Overcurrent protection
■■ 32-pin 4mm x 4mm TQFN package
APPLICATIONS
■■ FPGA and DSP supplies
■■ Video processor supplies
■■ Applications processor power
1/19
XR77103-A0R5
Typical Application
PGOOD
28
VIN
4
Start-up
BGR
VIN = 5.5 to 14V
10
15
31
VIN
6
24
PGOOD
VCC
Internal
Supply
PGOOD
OSC
SYNC
VIN1
BST1
VIN2
LX1
VIN3
LX1
BUCK1
VFB1
32
30
BST3
COMP1
29
1
2
9
12
11
VOUT1 = 0.8 to 6V
8
7
LX3
BST2
VOUT3 = 0.8 to 6V
25
LX3
BUCK3
LX2
VFB3
BUCK2
COMP3
LX2
VFB2
COMP2
XR77103-A0R5
EN
26
AGND DGND GND
27
19
5
16
14
13
VOUT2 = 0.8 to 6V
17
18
EP
Figure 1. Typical Application
REV1D
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XR77103-A0R5
Absolute Maximum Ratings
Operating Conditions
These are stress ratings only and functional operation
of the device at these ratings or any other above those
indicated in the operation sections of the specifications
below is not implied. Stresses beyond those listed under
absolute maximum ratings may cause permanent damage
to the device. Exposure to any absolute maximum rating
condition for extended periods may affect device reliability
and lifetime.
VIN......................................................................4.5V to 14V
VIN1, VIN2, VIN3, LX1, LX2, LX3........................ -0.3V to 18V
NOTE:
1. LX# pins’ DC range is from -0.3V, transient -1V for less than 10ns.
VCC....................................................................4.5V to 5.5V
LX#.................................................................-0.3V to 14V(1)
Junction temperature range (TJ).................. -40°C to 125°C
XR77103 package power dissipation max at 25°C...... 3.4W
XR77103 thermal resistance θJA.............................. 30°C/W
EN, VCC.............................................................. -0.3V to 7V
PGOOD, SYNC.................................................. -0.3V to 7V
BST# to LX#....................................................... -0.3V to 7V
AGND, DGND to GND..................................... -0.3V to 0.3V
Storage temperature..................................... -65°C to 150°C
Junction temperature.................................................. 150°C
Power dissipation...................................... Internally Limited
Lead temperature (soldering, 10 seconds)................. 260°C
CDM............................................................................. 700V
ESD rating (HBM – human body model)........................ 2kV
Electrical Characteristics
TA = 25°C, VIN = 12V, EN = VCC, fSW = 500kHz, unless otherwise specified. Limits applying over the full operating temperature
range are denoted by a •.
Symbol
Parameter
Conditions
•
Min
•
•
Typ
Max
Units
5.5
14
V
4.5
5.5
V
Power Supply Characteristics
VIN
Input voltage range
VIN
Input voltage range
VCC tied to VIN
VUVLO
UVLO threshold
VIN rising/falling
UVLODEGLITCH
UVLO deglitch
IVIN
IVINQ
VIN supply current
4.22/4.1
V
Rising/falling
220
µs
EN = GND
250
µA
EN = high, no load
2.6
mA
Internal Supply Voltage
VCC
Internal biasing supply
ILOAD = 0mA
•
ICC
Internal biasing supply current
VIN = 12V
•
VUVLO
UVLO threshold for VCC
UVLODEGLITCH
UVLO deglitch for VCC
4.9
5
5.1
V
10
mA
VCC rising
3.8
V
VCC falling
3.6
V
Falling edge
220
µs
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XR77103-A0R5
Electrical Characteristics (Continued)
TA = 25°C, VIN = 12V, EN = VCC, fSW = 500kHz, unless otherwise specified. Limits applying over the full operating temperature
range are denoted by a •.
Symbol
Parameter
Conditions
•
TSD
Thermal shutdown temperature
HYTSD
Thermal shutdown hysteresis
Temperature rising, Non-latch off.
TSD release threshold,
temperature = TSD-HYTSD
TSD_DEGLITCH
Thermal shutdown deglitch
VOVBUCK
Threshold voltage for buck
over voltage
Min
Typ
Max
Units
Protections
160
°C
20
°C
220
µs
Output rising
(HS FET will be forced off)
109
%
Output falling
(HS FET will be allowed to switch)
107
%
500
kHz
6
ms
Buck Converter
fSW
Switching frequency
tSS
Soft-start period
ILIMx
Peak inductor current limit
accuracy
Peak inductor current limit set at
4A
RON_HSx
HS switch on-resistance
VIN = 12V
200
mΩ
RON_LS1
LS switch on-resistance of Buck1
VIN = 12V
60
mΩ
RON_LS2/3
LS switch on-resistance of Buck2/3
VIN = 12V
80
mΩ
IOx
Output current capability
Continuous loading(1)
2
A
DMAX
Maximum duty cycle
95
%
tON MIN
Minimum on time
120
ns
-30
+30
%
Line regulation (ΔVOX/ΔVINX)
VINX = 5.5 to 14V, IOX = 1A
0.5
%VO
Load regulation (ΔVOX/ΔIOX)
IO = 10 to 90%, IO = MAX
0.5
%VO/A
Output voltage accuracy
VIN = 12V
5.5V ≤ VIN ≤ 14V
•
SYNCFREQ
Synchronization frequency
SYNCD_MIN
Synchronization signal
minimum duty cycle
•
SYNCD_MAX
Synchronization signal
maximum duty cycle
•
-1
Normal
1
-2
Normal
2
%
525
kHz
40
%
60
%
NOTE:
1. Subject to thermal derating. Design must not exceed the package thermal rating.
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XR77103-A0R5
Electrical Characteristics (Continued)
TA = 25°C, VIN = 12V, EN = VCC, fSW = 500kHz, unless otherwise specified. Limits applying over the full operating temperature
range are denoted by a •.
Symbol
Parameter
Conditions
•
Min
Typ
Max
Units
Power Good Reset Generator
VUVBUCK
Threshold voltage for buck
under voltage
Output falling,
(disabled after tON_HICCUP)
85
Output rising, (PG will be asserted)
90
%
tPG_DEGLITCH
Deglitch time
Rising and falling
22
ms
tON_HICCUP
Hiccup mode on time
VUVBUCKX asserted
24
ms
tOFF_HICCUP
Hiccup mode off time
Once tOFF_HICCUP elapses,
all converters will start up again
30
ms
tRP
Minimum reset period
2
s
PGOOD output low
ISINK = 1mA
•
0.4
V
Input Threshold (SYNC, EN)
VIH
Input threshold high
VINPUT rising
•
VIL
Input threshold low
VINPUT falling
•
REV1D
2.53
V
1.36
V
5/19
XR77103-A0R5
BST3
VIN3
LX3
LX3
VIN
AGND
EN
SYNC
Pin Configuration
32
31
30
29
28
27
26
25
VFB3
1
24 PGOOD
COMP3
2
23 NC
NC
3
22 NC
VIN
4
21 NC
GND
5
20 NC
VCC
6
19 DGND
COMP1
7
18 COMP2
VFB1
8
10
11
12
13
14
15
16
BST1
VIN1
LX1
LX1
LX2
LX2
VIN2
BST2
17 VFB2
9
Pin Functions
Pin Number
Pin Name
Description
1
VFB3
2
COMP3
3
NC
No connect.
4
VIN
IC supply pin. Connect a capacitor as close as possible to this pin.
5
GND
Ground.
6
VCC
Internal supply. Connect a ceramic capacitor from this pin to ground.
7
COMP1
8
VFB1
Buck 1 feedback pin.
9
BST1
Bootstrap capacitor for Buck 1. Connect a bootstrap capacitor from this pin to LX1.
10
VIN1
Input supply for Buck 1. Connect a capacitor as close as possible to this pin.
11
LX1
Switching node for Buck 1.
12
LX1
Switching node for Buck 1.
13
LX2
Switching node for Buck 2.
14
LX2
Switching node for Buck 2.
15
VIN2
Input supply for Buck 2. Connect a capacitor as close as possible to this pin.
16
BST2
Bootstrap capacitor for Buck 2. Connect a bootstrap capacitor from this pin to LX2.
17
VFB2
Buck 2 feedback pin.
18
COMP2
19
DGND
20
NC
Buck 3 feedback pin.
Compensation pin for Buck 3. Connect a series RC circuit to this pin for compensation.
Compensation pin for Buck 1. Connect a series RC circuit to this pin for compensation.
Compensation pin for Buck 2. Connect a series RC circuit to this pin for compensation.
Digital ground.
No connect.
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XR77103-A0R5
Pin Functions (Continued)
Pin Number
Pin Name
Description
21
NC
No connect.
22
NC
No connect.
23
NC
No connect.
24
PGOOD
25
SYNC
26
EN
27
AGND
28
VIN
IC supply pin. Connect a capacitor as close as possible to this pin.
29
LX3
Switching node for Buck 3.
30
LX3
Switching node for Buck 3.
31
VIN3
Input supply for Buck 3. Connect a capacitor as close as possible to this pin.
32
BST3
Bootstrap capacitor for Buck 3. Connect a bootstrap capacitor from this pin to LX3.
-
E-PAD
Connect to power ground.
Power good output. Open drain output asserted after all converters are sequenced and
within regulation.
External clock input pin. Connect to signal ground when unused.
Enable control input. Set EN high to enable converters.
Analog ground.
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XR77103-A0R5
Typical Performance Characteristics
2
2
1.5
1.5
1
1
∆VOUT/VOUT (%)
∆VOUT/VOUT (%)
All data taken at fSW = 500kHz, TA = 25°C, no airflow, unless otherwise specified.
0.5
0
-0.5
-1
-1.5
-2
0.5
0
-0.5
-1
-1.5
0
0.4
0.8
1.2
IOUT (A)
1.6
-2
2
0
2
2
1.5
1.5
1
1
∆VOUT/VOUT (%)
∆VOUT/VOUT (%)
Figure 2. Load Regulation Channel 1,
12VIN, 3.3VOUT
0.5
0
-0.5
-1
0.8
1.6
2
1.2
1.6
2
0
-0.5
-1
-2
0
0.4
0.8
1.2
IOUT (A)
1.6
2
0
IOUT (A)
Figure 5. Load Regulation Channel 2,
5VIN, 1.8VOUT
2
2
1.5
1.5
1
1
∆VOUT/VOUT (%)
∆VOUT/VOUT (%)
0.4
1.2
IOUT (A)
Figure 3. Load Regulation Channel 1,
5VIN, 3.3VOUT
0.5
Figure 4. Load Regulation Channel 2,
12VIN, 1.8VOUT
0.5
0
-0.5
-1
0.5
0
-0.5
-1
-1.5
-1.5
-2
0.8
-1.5
-1.5
-2
0.4
-2
0
0.4
0.8
1.2
IOUT (A)
1.6
2
0
0.4
0.8
1.2
IOUT (A)
1.6
2
Figure 7. Load Regulation Channel 3,
5VIN, 1.2VOUT
Figure 6. Load Regulation Channel 3,
12VIN, 1.2VOUT
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XR77103-A0R5
Typical Performance Characteristics (Continued)
All data taken at fSW = 500kHz, TA = 25°C, no airflow, unless otherwise specified.
VOUT AC 20MHz
Enable
Channel 3
180.0mV
-172.0mV
Channel 2
IOUT
Channel 1
Di/Dt ≥ 2.5A/μs
Figure 8. Power-up Sequence
VOUT AC 20MHz
Figure 9. 12VIN, 5.0VOUT Transient Response,
0.5A to 1.0A
148.0mV
VOUT AC 20MHz
-62.0mV
-132.0mV
IOUT
IOUT
Di/Dt ≥ 2.5A/μs
Di/Dt ≥ 2.5A/μs
Figure 10. 12VIN, 3.3VOUT Transient Response,
0.5A to 1.0A
VOUT AC 20MHz
68.0mV
Figure 11. 12VIN, 1.8VOUT Transient Response,
0.5A to 1.0A
164.0mV
VOUT AC 20MHz
68.0mV
-66.0mV
-160.0mV
IOUT
IOUT
Di/Dt ≥ 2.5A/μs
Di/Dt ≥ 2.5A/μs
Figure 12. 5VIN, 3.3VOUT Transient Response,
0.5A to 1.0A
Figure 13. 5VIN, 1.8VOUT Transient Response,
0.5A to 1.0A
REV1D
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XR77103-A0R5
Typical Performance Characteristics (Continued)
100
90
80
70
60
50
40
30
20
10
0
Efficiency (%)
Efficiency (%)
Efficiency
fSW = 500kHz, TA = 25°C, no airflow, only individual channel operating, inductor losses are included.
0
0.4
0.8
1.2
IOUT (A)
1.6
2
100
90
80
70
60
50
40
30
20
10
0
0
100
90
80
70
60
50
40
30
20
10
0
0
0.4
0.8
1.2
IOUT (A)
1.6
2
100
90
80
70
60
50
40
30
20
10
0
0
0
0.4
0.8
1.2
IOUT (A)
1.6
1.2
IOUT (A)
1.6
2
0.4
0.8
1.2
IOUT (A)
1.6
2
Figure 17. Efficiency Channel 2,
5VIN 1.8VOUT
Efficiency (%)
Efficiency (%)
Figure 16. Efficiency Channel 2,
12VIN 1.8VOUT
100
90
80
70
60
50
40
30
20
10
0
0.8
Figure 15. Efficiency Channel 1,
5VIN 3.3VOUT
Efficiency (%)
Efficiency (%)
Figure 14. Efficiency Channel 1,
12VIN 3.3VOUT
0.4
2
Figure 18. Efficiency Channel 3,
12VIN 1.2VOUT
100
90
80
70
60
50
40
30
20
10
0
0
0.4
0.8
1.2
IOUT (A)
1.6
2
Figure 19. Efficiency Channel 3,
5VIN 1.2VOUT
REV1D
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XR77103-A0R5
Typical Performance Characteristics (Continued)
4
0.8
3.5
0.7
3
0.6
Power Loss (W)
Power Dissipation in Package (W)
Thermal Characteristics
2.5
2
1.5
1
0.5
0.4
0.3
0.2
0.1
0.5
0
1.2V
1.8V
3.3V
0
0
0
10 20 30 40 50 60 70 80 90 100 110 120
0.4
0.8
Figure 20. Package Thermal Derating
2
Figure 21. Channel 1 Power Loss at
fSW = 500kHz, VIN = 12V, No Airflow
0.9
0.9
1.2V
1.8V
3.3V
0.7
0.6
1.2V
1.8V
3.3V
0.8
0.7
Power Loss (W)
0.8
Power Loss (W)
1.6
IOUT (A)
TAMBIENT (°C)
0.5
0.4
0.3
0.6
0.5
0.4
0.3
0.2
0.2
0.1
0.1
0
0
0
0.4
0.8
1.2
1.6
0
2
0.4
0.8
1.2
1.6
IOUT (A)
IOUT (A)
Figure 22. Channel 2 Power Loss at
fSW = 500kHz, VIN = 12V, No Airflow
Figure 23. Channel 3 Power Loss at
fSW = 500kHz, VIN = 12V, No Airflow
2
1.4
1.4
1.2V
1.8V
3.3V
1
1.2V
1.8V
3.3V
1.2
Power Loss (W)
1.2
Power Loss (W)
1.2
0.8
0.6
0.4
1
0.8
0.6
0.4
0.2
0.2
0
0
0
0.4
0.8
1.2
1.6
0
2
0.4
0.8
1.2
1.6
IOUT (A)
IOUT (A)
Figure 24. Channel 1 Power Loss at
fSW = 500kHz, VIN = 5V, No Airflow
Figure 25. Channel 2 Power Loss at
fSW = 500kHz, VIN = 5V, No Airflow
REV1D
2
11/19
XR77103-A0R5
Typical Performance Characteristics (Continued)
Thermal Characteristics
1.4
1.2V
1.8V
3.3V
Power Loss (W)
1.2
1
0.8
0.6
0.4
0.2
0
0
0.4
0.8
1.2
1.6
2
IOUT (A)
Figure 26. Channel 3 Power Loss at
fSW = 500kHz, VIN = 5V, No Airflow
REV1D
12/19
XR77103-A0R5
Functional Block Diagram
28
VIN
Start-up
BGR
4
VIN
6
24
PGOOD
VCC
Internal
Supply
PGOOD
OSC
SYNC
BST1
VIN1
10
VIN2
15
VIN3
31
LX1
BUCK1
LX1
VFB1
32
30
29
1
2
COMP1
BST3
25
9
12
11
8
7
LX3
LX3
BST2
BUCK3
LX2
VFB3
COMP3
BUCK2
LX2
VFB2
COMP2
16
14
13
17
18
XR77103-A0R5
EN
26
AGND DGND GND
27
19
5
EP
Figure 27. Functional Block Diagram
REV1D
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XR77103-A0R5
Applications Information
Operation
XR77103-A0R5 is a power management IC with three
step-down buck converters. Both high-side and low-side
MOSFETs are integrated to provide fully synchronous
conversion with higher efficiency. XR77103-A0R5 can
support 4.5V to 14V input supply, high load current,
500kHz clocking. The buck converters have a PSM
mode which can improve power dissipation during
light loads. As load is increased, the device transitions to
its constant operating frequency of 500kHz. The SYNC pin
also provides a means to synchronize the power converter
to an external signal. Input ripple is reduced by 180 degree
out-of-phase operation among converters. All three buck
converters have peak current mode control which simplifies
external frequency compensation. Each buck converter has
peak inductor current limit of 4A. The device has a power
good comparator monitoring the output voltage. Soft-start
for each converter is 6ms. All outputs start up once EN pin
is set high.
VOUTX
XR77103-A0R5
VOUTX = 0.8V x 1 + R1
R2
VOUTX
R1
SOC
R1
RDAC
VFBX
VDAC
PVT MNT
R2
Figure 29. AVS Control
Frequency Compensation
In order to properly frequency compensate the device,
the following component selection is recommended.
Minimum On-Time tON (min) Considerations
The XR77103 can regulate with pulse widths as low as
95ns. However, to ensure sufficent control range, the
design must use 120ns as the minimum on-time as stated
in the electrical table. Failure to meet this condition can
result in overcharging of the output and VOUT not meeting
specification.
Output Voltage Setting
Output voltage is set externally using an external
resistor divider. Output voltage is determined by the
following equation.
AVS SUPPLY
VIN
(V)
VOUT
(V)
L
(μH)
COUT
(µF)
RCOMP
(kΩ)
CCOMP
(nF)
12/5.0
1.0
2.2
47 x 2
20
2.2
12/5.0
1.2
2.2
47 x 2
20
2.2
12/5.0
1.5
3.3
22 x 3
20
4.7
12/5.0
1.8
3.3
22 x 2
20
4.7
12/5.0
2.5
4.7
22 x 2
20
4.7
12/5.0
3.3
4.7
22 x 1
20
4.7
12
5.0
6.8
22 x 1
20
4.7
Synchronization
The status of the SYNC pin will be ignored during startup and the XR77103-A0R5’s control will only synchronize
to an external signal after the PGOOD signal is asserted.
When synchronization is applied, the sync pulse frequency
must be higher than the PWM oscillator frequency
(525kHz) to allow the external signal trumping the oscillator
pulse reliably. When synchronization is not applied, the
SYNC pin should be connected to signal ground.
Although the device can lock to external clock running up to
2.31MHz, doing this will alter the timing characteristics and
degrade thermal performance.
XR77103-A0R5
R2
Figure 28. Output Voltage Setting
This can make the device applicable to AVS (automatic
voltage scaling) system. Output voltage can be adjusted
automatically by external DC voltage. Figure 29 shows
application circuit of supply for AVS system.
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XR77103-A0R5
Applications Information (Continued)
Out-of-Phase Operation
Channels 1 and 2 operate in phase while channel 3 operates
180 degrees out-of-phase with the other two converters
(see Figure 30). This enables the system, having less
input ripple, to lower component cost, save board space
and reduce EMI.
LX1
Thermal Design
Proper thermal design is critical in controlling device
temperatures and in achieving robust designs. There are
a number of factors that affect the thermal performance.
One key factor is the temperature rise of the devices in
the package, which is a function of the thermal resistances
of the devices inside the package and the power
being dissipated.
The thermal resistance of the XR77103-A0R5 (30°C/W)
is specified in the Operating Conditions section of
this datasheet. The θJA thermal resistance specification is
based on the XR77103-A0R5 evaluation board operating
without forced airflow. Since the actual board design in the
final application will be different, the thermal resistances in
the final design may be different from those specified.
LX2
LX3
Figure 30. Out-of-Phase Operation
Two Buck Regulators in Parallel Operation
(Current Sharing)
The XR77103-A0R5 can be used in parallel operation
to increase output current capacity. To enable this,
a user needs:
■■ To
connect VOUT2 and VOUT3 together.
■■ To
connect COMP2 and COMP3 together.
■■ Regulate
The package thermal derating and power loss curves are
shown in Figures 20 through 26. These correspond to input
voltages of 12V and 5V.
Layout Guidelines
Proper PCB layout is crucial in order to obtain a good
thermal and electrical performance.
For thermal considerations it is essential to use a number
of thermal vias to connect the central thermal pad to the
ground layer(s).
the channels 2 and 3 to the same VOUT.
Then, the channels 2 and 3 will run in parallel and load
current is shared in average.
In order to achieve good electrical and noise performance
following steps are recommended:
LX2
BUCK2
LX2
VFB2
VOUT
the output inductor close to the LX pins
and minimize the area of the connection.
Doing this on the top layer is advisable.
■■ Central
thermal pad shall be connected to the
power ground connections to as many layers
as possible.
COMP2
COMP3
BUCK3
■■ Place
■■ Output
filtering capacitor shall share the
same power ground connection as the input
filtering capacitor. Connection to the signal
ground plane shall be done with vias placed at
the output filtering capacitors.
LX3
LX3
VFB3
■■ AC
current loops formed by input filtering
capacitors, output filtering capacitors, output
inductors, and the regulator pins shall
be minimized.
Figure 31. Parallel Operation
■■ GND,
Power Good
The PGOOD pin is an open drain output. The PGOOD
pin is pulled low when any buck converter is pulled below
85% of the nominal output voltage. The PGOOD is pulled
up when all three buck converters’ outputs are more than
90% of their nominal output voltage and the PGOOD reset
timer expires. The polarity of the PGOOD is active high. The
PGOOD reset time is 2s.
REV1D
AGND, DGND pins shall be connected to
the signal ground plane.
■■ Compensation
networks shall be placed close to
the pins and referenced to the signal ground.
■■ VCC
bypass capacitor shall be placed close to
the pin.
15/19
XR77103-A0R5
Applications Information (Continued)
Typical Applications
VOUT3
VIN
LOUT_CH3
VIN
VIN3
COUT_CH3
RT_CH3
C2_IN
FB3
CIN_CH3
EN
CBST_CH3
SYNC
C1_IN
RB_CH3
RGND
VIN3
NC
VIN
NC
5
GND
6
VCC
7
COMP1
DGND
COMP2
VFB1
VIN1
PG
23
22
21
20
19
CP_CH2
18
17
FB2
VIN2
VIN2
CIN_CH1
CIN_CH2
CBST_CH1
VOUT1
CBST_CH2
LOUT_CH1
VOUT2
LOUT_CH2
COUT_CH1
RT_CH1
RC_CH2
CC_CH2
BST2
VIN2
24
16
LX2
15
LX2
VIN1
14
13
LX1
VFB2
9
FB1
NC
XR77103-A0R5
BST1
CC_CH1
SYNC 25
NC
4
8
RC_CH1
AGND 27
EN 26
3
LX1
CP_CH1
NC
12
CVCC
COMP3
PGOOD
VIN1
VIN
VFB3
2
11
VCC
RPG
1
10
CP_CH3
LX3 29
VIN 28
CC_CH3
RC_CH3
VIN3 31
LX3 30
E-PAD 33
BST3 32
FB3
VCC
COUT_CH2
FB1
RT_CH2
FB2
RB_CH1
RB_CH2
Figure 32. Typical Applications Schematic
REV1D
16/19
XR77103-A0R5
Mechanical Dimensions
TOP VIEW
BOTTOM VIEW
SIDE VIEW
TERMINAL DETAILS
Drawing No.: POD-00000079
Revision: C
REV1D
17/19
XR77103-A0R5
Recommended Land Pattern and Stencil
TYPICAL RECOMMENDED LAND PATTERN
TYPICAL RECOMMENDED STENCIL
Drawing No.: POD-00000079
Revision: C
REV1D
18/19
XR77103-A0R5
Order Information(1)
Part Number
Operating Temperature Range
Lead-Free
Package
Packaging
Method
-40°C ≤ TJ ≤ 125°C
Yes(2)
32-pin, 4mm x 4mm
TQFN package
Tape and Reel
XR77103ELBTR-A0R5
XR77103EVB-A0R5
XR77103-A0R5 evaluation board
NOTE:
1. Refer to www/maxlinear.com/XR77103-A0R5 for most up-to-date Ordering Information.
2. Visit www.maxlinear.com for additional information on Environmental Rating.
Revision History
Revision
Date
1A
03/09/16
Description
Initial Release
1B
11/21/17
Added MaxLinear logo. Updated format and ordering information format. Changed
Packaging Description section name to Mechanical Dimensions and Recommended Land
Pattern and Stencil. Corrected typo on Mechanical Dimensions, dimension A.
1C
1/17/19
Updated Frequency Compensation table. In Electrical Characteristics: updated Output
voltage accuracy and changed power good pull-down on resistance row to PGOOD
output low. Added Minimum On-Time section. Updated Applications Information Operation
sentence. Updated input thresholds (SYNC, EN). Update Ordering Information.
1D
3/28/19
Changed peak inductor current limit to accuracy. Increased peak inductor current limit to
4A.
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