XR81102-CA02TR-F

XR81102 Universal Clock - High Frequency LVPECL Clock Synthesizer General Description FEATURES The XR81101-CA02 is a clock synthesizer operating at a 3.3V/2.5V supply with Integer divider, using a 25MHz parallel resonant crystal reference input provides a 125MHz LVPECL outputs. The device is optimized for use with a 25MHz crystal (or system clock) and generates a 125MHz output clock for GE applications. The LVPECL outputs have very low phase noise jitter of sub 150fs, while consuming extremely low power. • XR81102-CA02: Factory configured • One differential LVPECL output pair • Crystal oscillator interface which can also be overdriven using a single-ended reference clock • Output frequency: 125MHz • Crystal/input frequency: 25MHz, parallel resonant crystal • RMS phase jitter @ 125MHz, 1.875MHz - 20MHz: < 150fs • Full 3.3V or 2.5V operating supply • -40°C to 85°C ambient operating temperature • Lead-free (RoHS 6) package The application diagram below shows a typical synthesizer configuration with any standard crystal oscillating in fundamental mode. Internal load capacitors are optionally available to minimize/eliminate external crystal loads. A system clock can also be used to overdrive the oscillator for a synchronous timing system. The typical phase noise plot below shows the jitter integrated over the 1.875MHz to 20MHz range that is widely used in WAN systems. These clock devices show a very good high frequency noise floor below -150dB. The XR81102 is a family of Universal Clock synthesizer devices in TSSOP8 packages. The devices generate ANY frequency in the range of 100MHz to 1.5GHz by utilizing a highly flexible delta sigma modulator and a wide ranging VCO. These devices can be used with standard crystals or external system clock to support a wide variety of applications. This family of products has an extremely low power PLL block with core power consumption 40% less than the equivalent devices from competition. By second sourcing several of the existing sockets, these devices provides a very compelling power efficiency value benefit across all market segments. APPLICATIONS • Gigabit Ethernet • Low-jitter Clock Generation • Synchronized clock systems Ordering Information – page 8 Other clock multiplier and/or driver configurations are possible in this clock family and can be requested from the factory Typical Application XR81102PHASENOISE(dBc/Hz) XR81102ͲCA02 -40db 2.5Vor3.3V VCC Q XTAL_IN 125MHz 25MHz -80db RMS Jitter = 120.9fs Int Range 1.875MHz to 20MHz -100db XTAL_OUT Enable -60db OE Q -120db -140db VEE -160db -180db 100Hz © 2014 Exar Corporation 1/8 1KHz 10KHz 100 KHz 1MHz 10MHz exar.com/XR81102 Rev 1B XR81102 Absolute Maximum Ratings Operating Conditions Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Maximum Rating condition for extended periods may affect device reliability and lifetime. Operating Temperature Range.....................-40°C to +85°C Supply Voltage..........................................................+4.2V Input Voltage......................................-0.5V to VCC + 0.5V Output Voltage...................................-0.5V to VCC + 0.5V Reference Frequency/Input Crystal.........10MHz to 60MHz Storage Temperature................................-55°C to +125°C Lead Temperature (Soldering, 10 sec).....................300°C ESD Rating (HBM - Human Body Model)....................2kV © 2014 Exar Corporation 2/8 exar.com/XR81102 Rev 1B XR81102 Electrical Characteristics Unless otherwise noted: TA = -40°C to +85°C, VCC = 3.3V±5% or 2.5V±5%, VEE = 0V Symbol Parameter Conditions * Min Typ Max Units • 3.135 3.3 3.465 V 3.3V Power Supply DC Characteristics VCC Power Supply Voltage IEE Power Supply Current Measured at 156.25MHz and includes the output load current 68 mA 2.5V Power Supply DC Characteristics VCC Power Supply Voltage IEE Power Supply Current • 2.375 Measured at 156.25MHz and includes the output load current 2.5 2.625 58 V mA LVCMOS/LVTTL DC Characteristics VIH VIL Input High Voltage Input Low Voltage VCC = 3.465V • 2.42 VCC + 0.3 V VCC = 2.625V • 1.83 VCC + 0.3 V VCC = 3.465V • -0.3 1.03 V VCC = 2.625V • -0.3 0.785 V 15 µA IIH Input High Current (OE, FSEL[1:0]) VIN = VCC = 3.465V or 2.625V • IIL Input Low Current (OE, FSEL[1:0]) VIN = 0V, VCC = 3.465V or 2.625V • -10 µA LVPECL DC Characteristics VOH Output High Voltage • VCC - 1.3 VCC - 0.4 V VOL Output Low Voltage • VCC - 2.0 VCC - 1.6 V VSWING Peak-to-Peak Output Voltage Swing • 0.6 1.2 V Crystal Characteristics XMode Mode of Oscillations Fundamental Xf Frequency ESR Equivalent Series Resistance 50 Ω CS Shunt Capacitance 7 pF 25 MHz AC Characteristics fOUT Output Frequency tjit(I) RMS Phase Jitter 125MHz Integration Range 1.875MHz-20MHz tjit(cc) Cycle-to-Cycle Jitter Using 25MHz, 18pF resonant crystal • tR/tF Output Rise/Fall Time 20% to 80% • Odc Output Duty Cycle • 125 MHz 0.15 pS 10 pS 100 500 pS 48 52 % * Limits applying over the full operating temperature range are denoted by a “•”. © 2014 Exar Corporation 3/8 exar.com/XR81102 Rev 1B XR81102 Pin Configuration VCC 1 8 Q XTAL_out 2 7 Q XTAL_in 3 6 VCC 4 5 OE VEE Pin Assignments Pin No. Pin Name Type Description 1 VCC Supply Power supply pin. 2 XTAL_OUT Output Crystal oscillator output. 3 XTAL_IN 4 VEE Supply 5 OE Input (900K: pull-up) 6 VCC Supply Power supply pin. 7 Q Output Inverted LVPECL output. 8 Q Output Positive LVPECL output. © 2014 Exar Corporation Input Crystal oscillator input. Negative supply pin. Output enable pin - LVCMOS/LVTTL active high input. Outputs are enabled when OE = high. Outputs are disabled when OE = low. 4/8 exar.com/XR81102 Rev 1B XR81102 Functional Block Diagram OE XTAL_IN OSC VCO PDF & LPF Divide by N Q nQ XTAL_OUT Divide by M M/N = 5 Typical Performance Characteristics Figure 1 shows a typical phase noise performance plot for a 125MHz clock output. The data was taken using the industry standard Agilent E5052B phase noise instrument. The integration range is 1.875MHz to 20MHz. Figure 1: 125MHz Operation, Typical Phase Noise at 3.3V © 2014 Exar Corporation 5/8 exar.com/XR81102 Rev 1B XR81102 Application Information Output Signal Timing Definitions Termination for LVPECL Outputs The following diagrams clarify the common definitions of the AC timing measurements. The termination schemes shown in Figure 2 and Figure 3 are typical for LVPECL outputs. Matched impedance layout techniques should be used for the LVPECL output pairs to minimize any distortion that could impact your maximum operating frequency. Figure 4 is an alternate termination scheme that uses a Y-termination approach. 3.3V 3.3V 130: Q nQ tcycle n tcycle n+1 t jit(cc) = |tcycle n - tcycle n+1| 3.3V (over 1000 cycles) 130: 50: LVPECL Output Figure 5: Cycle-to-Cycle Jitter LVPECL Input 50: 82: 82: Q 80% 80% Figure 2: XR81102 3.3V LVPECL Output Termination VSWING 20% 20% nQ tR 2.5V 2.5V : tF 2.5V : Figure 6: Output Rise/Fall Time and Swing 50: LVPECL Output LVPECL Input 50: : : Q nQ t PW Figure 3: XR81102 2.5V LVPECL Output Termination tPERIOD odc = VCC tPW t PERIOD x 100% VCC Figure 7: Output Period and Duty Cycle 50: LVPECL Output LVPECL Input 50: 50: For 3.3V systems RTT = 50: For 2.5V systems RTT = 19: 50: RTT Figure 4: XR81102 Alternate LVPECL Output Termination Using Y-termination © 2014 Exar Corporation 6/8 exar.com/XR81102 Rev 1B XR81102 Mechanical Dimensions 8-Pin TSSOP T T T T Note : The side, top and landing pattern drawings are general to TSSOP packaging but the table is specific to the 8pin TSSOP © 2014 Exar Corporation 7/8 exar.com/XR81102 Rev 1B XR81102 Ordering Information Part Number Package Green Operating Temperature Range Shipping Packaging Marking XR81102-CA02-F 8-pin TSSOP Yes -40°C to +85°C Tube T02 XR81102-CA02TR-F 8-pin TSSOP Yes -40°C to +85°C Tape & Reel T02 Eval Board N/A N/A N/A XR81102EVB N/A Revision History Revision Date 1A April 2014 1B April 28, 2014 Description Initial release. Update to general description. [ECN1421-16 l 05/25/2014] For Further Assistance: Email: commtechsupport@exar.com Exar Technical Documentation: http://www.exar.com/techdoc/ Exar Corporation Headquarters and Sales Offices 48720 Kato Road Tel: +1 (510) 668-7000 Fremont, CA 95438 - USA Fax: +1 (510) 668-7001 NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained herein are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. © 2014 Exar Corporation 8/8 exar.com/XR81102 Rev 1B