XR88C92IJ-F

XR88C92 / XR88C192 Data Sheet Dual Universal Asynchronous Receiver and Transmitter General Description Features The XR88C92 and XR88C192 are Dual Universal Asynchronous Receivers and Transmitters (DUART) with an 8 byte (XR88C92) or 16 byte (XR88C192) transmit and receive FIFO. The XR88C92 and XR88C192 are each pin and functional replacements for the SC26C92, and are improved versions of the Philips SCC2692 UART with faster data access and other additional features. The operating speed of the receiver and transmitter can be selected independently from a table of eighteen fixed baud rates, a 16X clock derived from a programmable counter / timer, or an external 1X or 16X clock. The baud rate generator and counter / timer can operate directly from a crystal or from an external clock input. The XR88C92 and XR88C192 provide a power-down mode in which the oscillator is stopped but the register contents are retained. The XR88C92 and XR88C192 are fabricated in an advanced CMOS process to achieve low power and high speed requirements. Added feature in devices with top marking of "D2" and newer: Single interrupt output 7 multipurpose inputs, 8 multipurpose outputs 2.97 to 5.5 volt operation Programmable character lengths (5, 6, 7, 8) Parity, framing, and overrun error detection Programmable 16-bit timer / counter On-chip crystal oscillator IP 4 IP 5 IP 6 IP 2 36 35 34 Power-down mode VCC IP 2 40 Programmable clock source for receiver and transmitter of each channel 37 IP 6 41 Watchdog timer 38 IP 5 42 Transmit and receive trigger levels VCC IP 4 43 Non-standard baud rate of up to 1Mbps 39 VC C 44 Standard baud rates from 50bps to 230.4kbps 40 A0 N. C. 1 16 byte transmit / receive FIFO (XR88C192) 41 IP 3 A0 2 8 byte transmit / receive FIFO (XR88C92) 42 A1 IP 3 3 Enhanced Multidrop mode operation with separate storage for address and data tags (9th bit) 43 IP 1 A1 4 Pin-to-pin and functionally compatible to SC26C92 44 A2 IP 1 5 Pinout A2 ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Ordering Information - page 33 6 ■ ■  5V tolerant inputs A3 7 39 -C S A3 1 33 -C S IP 0 8 38 RE S E IP 0 2 32 RE S E -I OW 9 37 XT AL 2 -I OW 3 31 XT AL 2 -I OR 10 36 XT AL 1 -I OR 4 30 XT AL 1 RX B 11 35 RX A RX B 5 29 RX A N. C. 12 34 N. C. T XB 6 28 TXA T XB 13 33 T XA OP 1 7 27 OP0 OP 1 14 32 OP 0 OP 3 8 26 OP2 OP 3 15 31 OP 2 OP 5 9 25 OP4 OP 5 16 30 OP 4 OP 7 10 24 OP6 OP 7 17 29 OP 6 N. C. 11 23 N.C. 22 D2 D0 14 D5 21 13 D3 20 12 D1 D4 28 D0 19 27 D2 18 26 D4 D6 25 D6 -I NT 24 -I NT 17 23 N. C. GND 22 GN D 16 21 D7 D7 20 D5 • www.maxlinear.com• Rev 1.35 GND 19 D3 Figure 1: PLCC44 Package Pinout 15 18 XR88C192 D1 XR88C92 Figure 2: LQFP44 Package Pinout XR88C92 / XR88C192 Dual Universal Asynchronous Receiver and Transmitter Data Sheet Revision History Revision History Document No. Release Date Change Description Added and updated Device Status to front page. 1.30 08/2003 Added 5V tolerant input descriptions. Clarified Programming example D. Clarified SRA, SRB Bit-2 description. 1.31 09/2003 Clarified that 5V tolerant inputs are only for devices with top marking of "D2" and newer. Devices with top marking of "CC" or newer do not have 5V tolerant inputs. 1.32 02/2005 Clarified that Extended Baud Rate Tables can only be selected via MR0A for both channels. Removed discontinued packages from Ordering Information. 1.33 08/2005 Updated the 1.4mm-thick Quad Flat Pack package description from "TQFP" to "LQFP" to be consistent with JEDEC and Industry norms. 1.34 08/2016 Correct typo in PLCC44 "e" dimension and update ordering information table. Updated: 1.35 222DSR00 August 27, 2021 ■ ■ ■ "PLCC44 Package Pinout" figure. "PLCC44 Pinout" figure. "Ordering Information" table. ii Rev 1.35 XR88C92 / XR88C192 Dual Universal Asynchronous Receiver and Transmitter Data Sheet Table of Contents Table of Contents General Description............................................................................................................................................. i Pinout.................................................................................................................................................................... i Features................................................................................................................................................................ i Functional Block Diagram ................................................................................................................................. 1 Pin Information ................................................................................................................................................... 2 Pin Descriptions ............................................................................................................................................................2 Product Description ........................................................................................................................................... 5 Internal Control Logic ....................................................................................................................................................5 Communication Channels A and B ...............................................................................................................................5 Timing Logic ..................................................................................................................................................................5 Interrupt Control Logic ...................................................................................................................................................5 Data Bus Buffer (D0 - D7) .............................................................................................................................................6 Multi-Purpose Inputs (IP0 - IP6) ....................................................................................................................................6 Multi-Purpose Outputs (OP0 - OP7)..............................................................................................................................6 OP0 and OP1 .......................................................................................................................................................6 OP2 - OP7............................................................................................................................................................6 Crystal Inputs (XTAL1 and XTAL2) ...............................................................................................................................7 RESET (RESET) ...........................................................................................................................................................7 Transmitter ....................................................................................................................................................................7 TX RTS Control ....................................................................................................................................................8 Receiver ........................................................................................................................................................................8 Loopback Modes ...........................................................................................................................................................9 Automatic Echo Mode .................................................................................................................................................10 Local Loopback Mode .................................................................................................................................................10 Remote Loopback Mode ............................................................................................................................................. 10 Multidrop Mode - Enhanced with Extra A / D Tag Storage..........................................................................................10 Extra Storage for the A / D Tag .......................................................................................................................... 10 Watchdog Timer ..........................................................................................................................................................11 Counter / Timer ...........................................................................................................................................................11 Counter Mode.............................................................................................................................................................. 11 Timer Mode .................................................................................................................................................................12 Other Programming Remarks...................................................................................................................................... 12 Registers ........................................................................................................................................................... 13 Mode Register 0 (MR0A, MR0B).................................................................................................................................15 222DSR00 iii Rev 1.35 XR88C92 / XR88C192 Dual Universal Asynchronous Receiver and Transmitter Data Sheet Table of Contents Mode Register 1 (MR1A, MR1B).................................................................................................................................15 Mode Register 2 (MR2A, MR2B).................................................................................................................................16 Status Register (SRA, SRB)........................................................................................................................................17 Clock Select Register (CSRA, CSRB).........................................................................................................................17 Command Register (CRA, CRB) .................................................................................................................................19 Receive Buffer (RXA, RXB).........................................................................................................................................19 Transmit Buffer (TXA, TXB) ........................................................................................................................................19 Input Port Change Register (IPCR) .............................................................................................................................20 Auxiliary Control Register (ACR) .................................................................................................................................20 Interrupt Status Register (ISR) .................................................................................................................................... 20 Interrupt Mask Register (IMR) .....................................................................................................................................21 Counter / Timer Registers ........................................................................................................................................... 21 General Purpose Register (GPR)................................................................................................................................21 Input Port Register - Read Only ..................................................................................................................................22 Output Port Configuration Register (OPCR) - Write Only............................................................................................22 Start Counter / Timer Register (STCR) - Read Only ...................................................................................................22 Stop Counter / Timer Register (SPCR) - Read Only ...................................................................................................22 Set Output Port Register (SOPR) - Write Only............................................................................................................ 23 Reset Output Port Register (ROPR) - Write Only........................................................................................................23 Programming Examples ..............................................................................................................................................24 Example A ..........................................................................................................................................................24 Example B ..........................................................................................................................................................24 Example C ..........................................................................................................................................................25 Example D ..........................................................................................................................................................25 Specifications ................................................................................................................................................... 26 Absolute Maximum Ratings.........................................................................................................................................26 Electrical Characteristics ............................................................................................................................................. 26 DC Electrical Characteristics..............................................................................................................................26 AC Electrical Characteristics ..............................................................................................................................27 Mechanical Dimensions ................................................................................................................................... 31 PLCC44 ....................................................................................................................................................................... 31 Mechanical Dimensions ................................................................................................................................... 32 LQFP44 ....................................................................................................................................................................... 32 Ordering Information........................................................................................................................................ 33 222DSR00 iv Rev 1.35 XR88C92 / XR88C192 Dual Universal Asynchronous Receiver and Transmitter Data Sheet List of Figures List of Figures Figure 1: PLCC44 Package Pinout........................................................................................................................ i Figure 2: LQFP44 Package Pinout ........................................................................................................................ i Figure 3: Block Diagram ....................................................................................................................................... 1 Figure 4: PLCC44 Pinout...................................................................................................................................... 2 Figure 5: LQFP44 Pinout ...................................................................................................................................... 2 Figure 6: Crystal Connection ................................................................................................................................ 7 Figure 7: C/T Output in Timer and Counter Modes ............................................................................................ 11 Figure 8: Bus Timing (Read / Write Cycle) ......................................................................................................... 28 Figure 9: Input Port Timing ................................................................................................................................. 28 Figure 10: Output Port Timing ............................................................................................................................ 28 Figure 11: Receive Timing.................................................................................................................................. 29 Figure 12: Transmit Timing................................................................................................................................. 29 Figure 13: Interrupt Timing ................................................................................................................................. 30 Figure 14: External Clock Timing........................................................................................................................ 30 Figure 15: Mechanical Dimension, PLCC44....................................................................................................... 31 Figure 16: Mechanical Dimensions, LQFP44 ..................................................................................................... 32 222DSR00 v Rev 1.35 XR88C92 / XR88C192 Dual Universal Asynchronous Receiver and Transmitter Data Sheet List of Tables List of Tables Table 1: XR88C92 and XR88C192 Pin Descriptions............................................................................................ 2 Table 2: Multi-Purpose Inputs (IP0 - IP6) ............................................................................................................. 6 Table 3: Internal Registers.................................................................................................................................. 13 Table 4: Internal Register Descriptions............................................................................................................... 14 Table 5: Baud Rate Table for a 3.6864MHz Clock. Data Rates Double for a 7.3728MHz Clock. ...................... 18 Table 6: Absolute Maximum Ratings .................................................................................................................. 26 Table 7: Electrical Characteristics ...................................................................................................................... 26 Table 8: AC Electrical Characteristics ................................................................................................................ 27 Table 9: Ordering Information............................................................................................................................. 33 222DSR00 vi Rev 1.35 XR88C92 / XR88C192 Dual Universal Asynchronous Receiver and Transmitter Data Sheet Functional Block Diagram Functional Block Diagram Figure 3: Block Diagram 222DSR00 1 Rev 1.35 XR88C92 / XR88C192 Dual Universal Asynchronous Receiver and Transmitter Data Sheet Pin Information Pin Information IP 4 IP 5 IP 6 IP 2 36 35 34 IP 2 40 37 IP 6 41 VCC IP 5 42 38 IP 4 43 VCC VC C 44 39 N. C. 1 40 A0 A0 2 41 IP 3 IP 3 3 42 A1 A1 4 43 IP 1 IP 1 5 44 A2 A2 6 Pin Configurations A3 7 39 -C S A3 1 33 -C S IP 0 8 38 RE S E IP 0 2 32 RE S E -I OW 9 37 XT AL 2 -I OW 3 31 XT AL 2 -I OR 10 36 XT AL 1 -I OR 4 30 XT AL 1 RX B 11 35 RX A RX B 5 29 RX A N. C. 12 34 N. C. T XB 6 28 TXA T XB 13 33 T XA OP 1 7 27 OP0 OP 1 14 32 OP 0 OP 3 8 26 OP2 OP 3 15 31 OP 2 OP 5 9 25 OP4 OP 5 16 30 OP 4 OP 7 10 24 OP6 OP 7 17 29 OP 6 N. C. 11 23 N.C. 18 19 20 21 22 D6 D4 D2 D0 13 D3 -I NT 12 D1 17 28 D0 GND 27 D2 16 26 D4 GND 25 D6 15 24 -I NT D7 23 N. C. D5 22 Figure 4: PLCC44 Pinout 14 21 20 D5 D7 19 D3 XR88C192 GN D 18 D1 XR88C92 Figure 5: LQFP44 Pinout Pin Descriptions Table 1: XR88C92 and XR88C192 Pin Descriptions Name PLCC44 LQFP44 Type Description RXA, RXB 35, 11 29, 5 I Serial data input. The serial information (data) received from the serial port to the XR88C92 / XR88C192 receive input circuit. A mark (high) is logic one and a space (low) is logic zero. This input must be held at logic one when idle and during power down. TXA, TXB 33, 13 28, 6 O Serial data output. The serial data is transmitted via this pin with additional start, stop and parity bits. This output will be held in mark (high) state during reset, local loop back mode or when the transmitter is disabled. RESET 38 32 I Master reset (active high). A high on this pin will reset all the outputs and internal registers. The transmitter output and the receiver input will be disabled during reset time. OP0 32 27 O Multi-purpose output. General purpose output or Channel A Request-To-Send (-RTSA active low). OP1 14 7 O Multi-purpose output. General purpose output or Channel B Request-To-Send (-RTSB active low). 222DSR00 2 Rev 1.35 XR88C92 / XR88C192 Dual Universal Asynchronous Receiver and Transmitter Data Sheet Pin Descriptions Table 1: XR88C92 and XR88C192 Pin Descriptions Name OP2 OP3 OP4 PLCC44 31 15 30 LQFP44 26 8 25 Type Description O Multi-purpose output. General purpose output or one of the following functions can be selected for this output pin by programming the Output Port Configuration Register bits 1, 0: TxAClk1 - Transmit 1X clock. TxAClk16 - Transmit 16X clock. RxAClk1 - Receive 1X clock. O Multi-purpose output. General purpose output or one of the following functions can be selected for this output pin by programming the Output Port Configuration Register bits 3, 2: C/T - Counter timer output (open drain output). TxBClk1 - Transmit 1X clock. RxBClk1 - Receive 1X clock. O Multi-purpose output. General purpose output or one of the following functions can be selected for this output pin by programming the Output Port Configuration Register bit 4: -RxARDY - Receive ready signal (open drain output). -RxAFULL - Receive FIFO full signal (open drain output). OP5 16 9 O Multi-purpose output. General purpose output or one of the following functions can be selected for this output pin by programming the Output Port Configuration Register bit 5: -RxBRDY - Receive ready signal (open drain output). -RxBFULL - Receive FIFO full signal (open drain output). OP6 29 24 O Multi-purpose output. General purpose output or Transmit A holding register empty interrupt (-TxARDY open drain output). OP7 17 10 O Multi-purpose output. General purpose output or Transmit B holding register empty interrupt (-TxBRDY open drain output). A0 - A3 2, 4, 6, 7 40, 42, 44, 1 I Address select lines. To select internal registers. XTAL1 36 30 I Crystal input 1 or external clock input. A crystal can be connected between this pin and XTAL2 pin to utilize the internal oscillator circuit. An external clock can be used to clock internal circuit and baud rate generator for custom transmission rates. XTAL2 37 31 O Crystal input 2 or buffered clock output. See XTAL1. GND 22 16, 17 Pwr Signal and power ground. -INT 24 18 O Interrupt output (open drain, active low). This pin goes low upon occurrence of one or more of eight maskable interrupt conditions (when enabled by the interrupt mask register). CPU can read the interrupt status register to determine the interrupt condition(s). This output requires a pull-up resistor. IP0 8 2 I Multi-purpose input or Channel A Clear-To-Send (-CTSA active low). IP1 5 43 I Multi-purpose input or Channel B Clear-To-Send (-CTSB active low). IP2 40 34 I Multi-purpose input or Timer / Counter external clock input. IP3 3 41 I Multi-purpose input or Channel A transmit external clock port input. The transmit data is clocked on the falling edge of the clock. IP4 43 37 I Multi-purpose input or Channel A receive external clock input. The transmit data is clocked on the rising edge of the clock. IP5 42 36 I Multi-purpose input or Channel B transmit external clock input. The transmit data is clocked on the falling edge of the clock. IP6 41 35 I Multi-purpose input or Channel B receive external clock input. The transmit data is clocked on the rising edge of the clock. 222DSR00 3 Rev 1.35 XR88C92 / XR88C192 Dual Universal Asynchronous Receiver and Transmitter Data Sheet Pin Descriptions Table 1: XR88C92 and XR88C192 Pin Descriptions Name PLCC44 LQFP44 Type Description -CS 39 33 I Chip select (active low). A low at this pin enables the serial port / CPU data transfer operation. D0 - D7 28, 18, 27, 19, 26, 20, 25, 21 22, 12, 21, 13, 20, 14, 19, 15 I/O Bi-directional data bus. Eight bit, three state data bus to transfer information to or from the CPU. D0 is the least significant bit of the data bus and the first serial data bit to be received or transmitted. -IOW 9 3 I Write strobe (active low). A low on this pin will transfer the contents of the CPU data bus to the addressed register. -IOR 10 4 I Read strobe (active low). A low on this pin will transfer the contents of the XR88C92 / XR88C192 register to the CPU data bus. VCC 44 38, 39 Pwr Power supply input, 2.97 to 5.5V. N.C. 1, 12, 23, 24 11, 23 222DSR00 No connection. 4 Rev 1.35 XR88C92 / XR88C192 Dual Universal Asynchronous Receiver and Transmitter Data Sheet Product Description Product Description Internal Control Logic crystal connected across the XTAL1 and XTAL2 inputs or from an external clock of the appropriate frequency connected to XTAL1. The XTAL1 clock serves as the basic timing reference for the baud rate generator, the C/T and other internal circuits. The internal control logic of the XR88C92 / XR88C192 receives operation commands from the central processing unit (CPU) and generates appropriate signals to the internal sections to control device operation. The internal control logic takes the following inputs: ■ ■ -CS, which is the XR88C92 / XR88C192 chip select. ■ Four register select lines (A0 through A3) which are decoded to allow access to the registers within the XR88C92 / XR88C192. ■ The baud rate generator operates from the XTAL1 clock input and can generate 28 commonly used data communication baud rates (if a 3.6864MHz crystal or clock is used) ranging from 50 to 230.4kbps by producing internal clock outputs at 16 times the actual baud rate. In addition, other baud rates can be derived by connecting 16X or 1X clocks to multi-purpose input port pins IP3 - IP6 that have alternative functions as receiver or transmitter clock inputs. -IOR (read) and -IOW (write), which allow data transfers between the CPU and the XR88C92 / XR88C192 via the data bus (D0 to D7). Clock selector logic consists of the clock selector register (CSRA, CSRB), bits 0 and 2 of Mode Register 0 (MR0A, MR0B), and bit 7 of Auxiliary Control Register (ACR). These allow various combinations of these baud rates for the receiver and transmitter of each channel. See Table 5 on page 18 for more details. RESET (reset), which initializes or resets all outputs and internal registers. Communication Channels A and B The programmable 16-bit counter / timer (C / T) can produce a 16X clock for other baud rates by counting down its programmed clock source. Users can program the 16-bit C / T within the XR88C92 / XR88C192 to use one of several clock sources as its input. The output of the C / T is available to the internal clock selectors and can also be programmed to appear at output OP3. In the counter mode, the C / T can be started and stopped under program control. When stopped, the CPU can read its contents. The counter counts down the number of pulses stored in the concatenation of the C / T upper register and C / T lower register and produces an interrupt. This is a system oriented feature that can be used to record timeouts when implementing various application protocols. Each communication channel includes a full-duplex asynchronous receiver / transmitter (UART). The operating frequency for each receiver and each transmitter can be selected independently from the baud rate generator, the Counter / Timer (C / T), or from an external clock. The transmitter accepts parallel data from the CPU, converts it to a serial bit stream in the form of a character and outputs it on the Transmit Data output pin (TXA, TXB). The character consists of start, stop, and optional parity bits. The receiver accepts serial data on the Receive Data input pin (RXA, RXB), converts this serial input to parallel format, checks for a start bit, stop bit, parity bit (if any), framing error, overrun or break condition, and transfers the data byte to the CPU during read operations. Interrupt Control Logic Timing Logic The following registers are associated with the interrupt control logic: The timing logic consists of: ■ ■ ■ ■ ■ ■ ■ A crystal oscillator A baud rate generator (BRG) Clock selector logic Interrupt Status Register (ISR) Auxiliary Control Register (ACR) A single active-low interrupt output (-INT) can notify the CPU that any of eight internal events has occurred. These eight events are described in the discussion of the interrupt status register (ISR). User can program the interrupt mask A programmable 16-bit counter / timer (C/T) The crystal oscillator operates directly from a 3.6864MHz 222DSR00 Interrupt Mask Register (IMR) 5 Rev 1.35 XR88C92 / XR88C192 Dual Universal Asynchronous Receiver and Transmitter Data Sheet XR88C192 to allow a change of state in any of the inputs IP0 through IP3 to generate an interrupt to the CPU. See description of the Interrupt Status Register (ISR), (address 0x05) for details. The IPCR bits are cleared when the CPU reads the register. Also see baud rate Table 5 on page 18. register (IMR) to allow only certain conditions to cause -INT to be asserted while the CPU can read the ISR to determine all currently active interrupting conditions. In addition, users can program the parallel outputs OP3 through OP7 to provide discrete interrupt outputs for the transmitters, the receivers and the C / T. See Multi-Purpose Outputs (OP0 - OP7) for details. Multi-Purpose Outputs (OP0 - OP7) Data Bus Buffer (D0 - D7) The eight output pins (OP0 - OP7) can either be used as general purpose outputs or can be used for alternate functions representing various conditions using: The data bus buffer provides the interface between the external and internal data buses. It is controlled by the internal control logic to allow read and write data transfer operations to occur between the controlling CPU and XR88C92 / XR88C192 by way of the eight parallel data lines (D0 through D7). ■ ■ ■ ■ Multi-Purpose Inputs (IP0 - IP6) Function Programming -CTSA Set MR2A bit 4 = 1 IP1 -CTSB Set MR2B bit 4 = 1 IP2 C/T Ext.Clk Set ACR[6:4] = 000 IP3 TxA Ext.Clk Set CSRA[3:0] = 1110 or 1111 IP4 RxA Ext.Clk Set CSRA[7:4] = 1110 or 1111 IP5 TxB Ext.Clk Set CSRB[3:0] = 1110 or 1111 IP6 RxB Ext.Clk Set CSRB[7:4] = 1110 or 1111 Output Port Configuration Register (OPCR) Set Output Port Register (SOPR) Reset Output Port Register (ROPR) The output OP0 can function as the channel A request-tosend (-RTSA) output for either the transmitter (MR2A bit 5 = 1) or the receiver (MR1A bit 7 = 1). Note that only one of these bits should be set to ’1’ at a given time. See the description of the transmitter RTS and receiver RTS in the Transmitter and Receiver sections of this datasheet respectively. The output OP1 acts as the channel B request-to-send (-RTSB) output and is controlled in a similar way by the channel B registers. Table 2: Multi-Purpose Inputs (IP0 - IP6) IP0 Mode Registers 1 and 2 (MR1A, MR1B, MR2A, MR2B) OP0 and OP1 The states of the seven multi-purpose inputs (IP0 through IP6) can be read from the internal register IPR (address 0x0D). The bits in this register are the complements of the actual inputs - for example, if the IP0 is low, the corresponding bit in the IPR, bit 0 is a logic ’1’. Each of these inputs also has an alternate control function capability. The alternate functions can be enabled / disabled on a bit-by-bit basis. Table 2 shows how each of these inputs is configured for its special function: Input Data Bus Buffer (D0 - D7) OP2 - OP7 The other outputs (OP2 - OP7) are configured via the OPCR. Please see the description under the Output Port Configuration Register (OPCR) - Write Only for the details. Four change-of-state detectors are associated with inputs IP0, IP1, IP2 and IP3. If a high-to-low or low-to-high transition occurs on any of these inputs, the corresponding bit in the input port change register (IPCR - address 0x04) will be set accordingly. The sampling clock of the change detectors is the XTAL1 / 96 tap of the baud rate generator, which is 38.4kHz if XTAL1 is 3.6864MHz. A new input level must be sampled on two consecutive sampling clocks to detect a change. Also, users can program the XR88C92 / 222DSR00 6 Rev 1.35 XR88C92 / XR88C192 Data Sheet Crystal Inputs (XTAL1 and XTAL2) Crystal Inputs (XTAL1 and XTAL2) RESET (RESET) If a crystal is used, it is connected between XTAL1 and XTAL2, in which case a capacitor of approximately 22 to 47pF should be connected from each of these pins to ground. If an external CMOS-level is used, the pin XTAL2 must be left open. The XR88C92 / XR88C192 can be reset by asserting the RESET signal or by programming the appropriate internal registers. A hardware reset (assertion of RESET) clears the following registers: ■ ■ ■ ■ Status Registers A and B (SRA and SRB) Interrupt Mask Register (IMR) Interrupt Status Register (ISR) Output Port Configuration Register (OPCR) RESET also performs the following operations: ■ ■ ■ Places the outputs OP0 through OP7 in the high state Places the counter / timer in the counter mode Places channels A and B in the in active state with the transmitter serial data outputs (TXA and TXB) in the mark (high) state Reset commands can be programmed through the command registers to reset the receiver, transmitter, error status or break-change interrupts for each channel. Transmitter The transmitter converts the parallel data from the CPU to a serial bit stream on the transmitter output pin (TXA, TXB). It automatically sends a start bit followed by the programmed number of data bits, an optional parity bit and the programmed number of stop bits. The least-significant bit is sent first. Data is shifted out the transmit serial data output pin (TXA, TXB) on the falling edge of the programmed clock source (XTAL1, IP3 or IP5: see CSRA, CSRB Bits 3-0:). After the transmission of the stop bits and a new character is not available in the transmit FIFO, the transmitter serial data output (TXA, TXB) remains high. Transmission resumes when the CPU loads a new character into the transmit FIFO. If the transmitter receives a disable command (CRA, CRB bits 3:2), it will continue operating until the character in the transmit shift register is completely sent out. Other characters in the FIFO are neither sent nor discarded, but will be sent when the transmitter is re-enabled. Figure 6: Crystal Connection Note: The terms assertion and negation will be used extensively to avoid confusion when dealing with a mixture of "active low" and "active high" signals. The term assert or assertion indicates that a signal is active or true, independent of whether that level is represented by a high or low voltage. The term negate or negation indicates that a signal is inactive or false. 222DSR00 7 Rev 1.35 XR88C92 / XR88C192 Dual Universal Asynchronous Receiver and Transmitter Data Sheet Receiver TX RTS Control Receiver Users can program the transmitter to automatically negate the request-to-send (RTS) output (alternate function of OP0 and OP1 for channels A and B respectively) on completion of a message transmission (using MR2A, MR2B bit 5). If the transmitter is programmed to operate with RTS control, the RTS output must be manually asserted before each message is transmitted. Also, the transmitter needs to be disabled after all the required data is loaded into the FIFO. Then, the RTS output will be automatically negated when the transmit shift register and the TX FIFO are both empty. In automatic RTS mode, no more characters can be written to the FIFO after the transmitter is disabled. The channel A and B receivers are enabled for data reception through the respective channels command register (CRA, CRB bits 1:0). The channel’s receiver looks for the high-to-low (mark-to-space) transition of a start bit on the receiver serial data input pin. If operating in 16X clock mode, the serial input data is re-sampled on the next 7 clocks. If the receiver serial data is sampled high, the start bit is invalid and the search for a valid start bit begins again. If receiver serial data is still low, a valid start bit is assumed and the receiver continues to sample the input at one bit time intervals (at the theoretical center of the bit) until the proper number of data bits and the parity bit (if any) have been assembled and one stop bit has been detected. If a 1X clock is used, data is sampled at one bit time intervals throughout, including the start bit. Data on the receiver serial data input pin is sampled on the rising edge of the programmed clock source (XTAL1, IP4 or IP6: see Clock Select Register (CSRA, CSRB) bits 7:4). If auto clear-to-send (CTS) control is enabled (using MR2A, MR2B bit 4), the CTS input (alternate function of IP0 and IP1 for channels A and B respectively) must be asserted (low) in order for the character to be transmitted. If it gets negated (high) in the middle of a transmission, the character in the shift register is transmitted and the transmit data output (TXA, TXB) then remains in the marking state until CTSA, CTSB gets asserted again. In this process, the least significant bit is received first. The receive buffer is composed of the FIFO (8/16 locations in XR88C92 / XR88C192 respectively) and a receive shift register connected to the receiver serial data input. Data is assembled in the shift register and loaded into the bottom most empty FIFO location. If the character length is less than eight bits, the most significant unused bits are set to zero. The transmitter can also be forced to send a continuous low (space) condition by issuing the start break command (see Command Register (CRA, CRB) bits 7:4). The state of CTS is ignored by the transmitter when it is set to send a break. A start break is deferred as long as the transmitter has characters to send, but if normal character transmission is inhibited by CTS, the start break will proceed. The start break must be terminated by a stop break or a TX disable + TX reset before normal character transmissions can resume. If the stop bit is sampled as a 1, the receiver will immediately look for the next start bit. However, if the stop bit is sampled as a 0, either a framing error or a received break had occurred. If the stop bit is 0 and the data and parity (if any) are not all zero, it is a framing error. The damaged character is transferred to the FIFO with the framing error flag set. If the receiver serial data remains low for one-half of the bit period after the stop bit was sampled, the receiver operates as if a new start bit transition has been detected. If the stop bit is 0 and the data and parity (if any) bits are also all zero, it is a break. A character consisting of all zeros will be loaded into the FIFO with the received break bit (but not the framing error bit) set to one. The receiver serial data input must return to a high condition for at least one-half bit time before a search for the next start bit begins. Also at this time, the received break bit is reset. The channel A and B transmitters are enabled for data transmission through their respective command registers (see Command Register (CRA, CRB) bits 3:2). The transmit FIFO trigger levels (see Mode Register 0 (MR0A, MR0B) bits 4:5) are used to generate an interrupt request to the CPU on the -INT pin. This is also reflected in the Interrupt Status Register, ISR bit 0 for channel A and bit 4 for channel B. This is different from the TxRDY bit in the status register. The TxRDY bit in the status register (SRA, SRB bit 2) indicates if the TX FIFO has at least one empty location. This can also be programmed to appear at the output pin OP6 / OP7. The TxEMT bit (SRA, SRB bit 3) indicates if both the TX FIFO and the TX shift register are empty. The receiver can detect a break that starts in the middle of a character provided the break persists completely through the next character time or longer. When the break begins in the middle of a character, the receiver will place the damaged character in the FIFO with the framing error bit set. Then, provided the break persists through the next character time, the receiver will also place an all-zero character in the FIFO with the received break bit set. The The transmitter can be reset through a software command (CRA, CRB bits 7:4). If it is reset, operation ceases immediately and must be enabled through the command register before resuming operation. Reset also discards any characters in the FIFO. 222DSR00 8 Rev 1.35 XR88C92 / XR88C192 Dual Universal Asynchronous Receiver and Transmitter Data Sheet parity error, framing error, overrun error and received break conditions (if any) set error and break flags in the status register at the received character boundary and are valid only when the receiver ready bit (RXRDY) in the status register is set. Reading the status register (SRA, SRB) does not affect the FIFO. The FIFO is "popped" only when the receive buffer is read. If the FIFO is full when a new character is received, that character is held in the receive shift register until a FIFO position is available. If an additional character is received while this state exists, the contents of the FIFO are not affected, but the character previously in the shift register is lost and the overrun error status bit will be set upon receipt of the start bit of the new overrunning character. The receiver ready bit in the status register (SRA, SRB bit 0) is set when ever one or more characters are available to be read by the CPU. A read of the receiver buffer produces an output of data from the top of the FIFO stack. After the read cycle, the data at the top of the FIFO stack and its associated status bits are "popped" and new data can be added at the bottom of the stack by the receive shift register. The FIFO full status bit (SRA, SRB bit1) is set if all 8 (or 16) stack positions are filled with data. Either the receiver ready or the FIFO full status bits can be selected to cause an interrupt (See Mode Register 1 (MR1A, MR1B) bit 6). To support flow control, a receiver can automatically negate and reassert the request-to-send (RTS) output (RXRTS control - see Mode Register 1 (MR1A, MR1B) bit 7). The request-to-send output (at OP0 or OP1 for channel A or B respectively) will automatically be negated by the receiver when a valid start bit is received and the FIFO stack is full. When a FIFO position becomes available, the request-tosend output will be reasserted automatically by the receiver. Connecting the request-to-send output to the clear-to-send (CTS) input of a transmitting device prevents overrun errors in the receiver. The RTS output must be manually asserted the first time. Thereafter, the receiver will control the RTS output. In addition to the data byte, three status bits (parity error, framing error and the received break) are appended to each data character in the FIFO (overrun is not). By programming the error-mode control bit (MR1A, MR1B bit 5), status can be provided for "character" or "block" modes. In the "character" mode, the status register (SRA, SRB) is updated on a character by character basis and applies only to the character at the top of the FIFO. Thus, the status must be read before the character is read. Reading the character pops the data byte and its error flags off the FIFO. In the "block" mode, the status provided in the status register for the parity error, framing error, and received break conditions are the logical OR of these respective bits, for all the data bytes in the FIFO stack since the last reset error command (see Command Register (CRA, CRB) bits 7:4) was issued. That is, beginning immediately after the last reset error command was issued, a continuous logical OR function of corresponding status bits is produced in the status register as each character enters the FIFO. If the FIFO stack contains characters and the receiver is then disabled, the characters in the stack can still be read but no additional characters can be received until the receiver is again enabled. If the receiver is disabled while receiving a character, or while there is a character in the shift register waiting for a FIFO opening, these characters are lost. If the receiver is reset, the FIFO stack and all of the receiver status bits, the corresponding output ports and the interrupt request are reset. No additional characters can be received until the receiver is again enabled. Loopback Modes The block mode is useful in applications requiring the exchange of blocks of information where the software overhead of checking each character’s error flags cannot be tolerated. In this mode, entire messages can be received and only one data integrity check is performed at the end of each message. Although data reception in this manner has speed advantages, there are also disadvantages. If an error occurs within a message, the error will not be recognized until the final check is performed. Also, there is no indication of which character(s) is in error within the message. 222DSR00 Loopback Modes Besides the normal operation mode in which the receiver and transmitter operate independently, each XR88C92 / XR88C192 channel can be configured to operate in various looping modes (see Mode Register 2 (MR2A, MR2B) bits 7:6) that are useful for local and remote system diagnostic functions. 9 Rev 1.35 XR88C92 / XR88C192 Dual Universal Asynchronous Receiver and Transmitter Data Sheet Automatic Echo Mode A transmitted character from the master station consists of a start bit, the programmed number of data bits, an address / data (A / D) bit tag (replacing the parity bit used in normal operation), and the programmed number of stop bits. The A / D tag indicates to the slave station’s channel whether the character should be interpreted as an address character or a data character, The character is interpreted as an address character if the A / D tag is set to a ’1’ or interpreted as a data character if it is set to a ’0’. The polarity of the transmitted A / D tag is selected by programming MR1A, MR1B bit 2 to a ’1’ for an address character and to a ’0’ for data characters. User should program the mode register prior to loading the corresponding data or address characters into the transmit buffer. In this mode, the channel automatically re-transmits the received data on a bit by bit basis. The local CPU to receiver communication continues normally, but the CPU to transmitter link is disabled. Local Loopback Mode In this mode, the transmitter output is internally connected to the receiver input. The external TX pin is held in the mark (high) state in this mode. By sending data to the transmitter and checking that the data assembled by the receiver is the same data that was sent, proper channel operation can be assured. In this mode, the CPU to transmitter and CPU to receiver communications continue normally. As a slave station, the XR88C92 / XR88C192 receiver continuously monitors the received data stream regardless of whether it is enabled or disabled. If the receiver is disabled, it sets the receiver ready status bit and loads the character into the FIFO receive holding register stack, provided the received A / D tag is a ’1’ (address tag). The received character is discarded if the received address / data bit is a ’0’ (data tag). If the receiver is enabled, all received characters are transferred to the CPU during read operations. In either case, the data bits are loaded into the data portion of the FIFO stack while the address / data bit is loaded into the status portion of the FIFO stack normally used for parity error (SRA, SRB bit 5). Framing error, overrun error, and break detection operate normally regardless of whether the receiver is enabled or disabled. The address / data (A / D) tag takes the place of the parity bit and parity is neither calculated nor checked for characters in this mode. Remote Loopback Mode In this mode, the channel automatically re-transmits the received data on a bit-by-bit basis. The local CPU to receiver and CPU to transmitter links are disabled. This mode is useful in testing the receiver and transmitter operation of a remote channel. This mode requires the remote channel receiver to be enabled. Multidrop Mode - Enhanced with Extra A / D Tag Storage Users can program the channel to operate in a wake-up mode for Multidrop applications. In this mode of operation (set MR1A, MR1B bits 4:3 = 11), the XR88C92 / XR88C192, as a master station channel connected to several slave stations (a maximum of 256 unique slave stations), transmits an address character followed by a block of data characters targeted for one or more of the slave stations. The channel receivers within the slave stations are disabled, but they continuously monitor the data stream sent out from the master station. When the slave stations’ receivers detect an address character, each receiver notifies its respective CPU by setting receiver ready (-RXRDY) and generating an interrupt, if programmed to do so. Each slave station CPU then compares the received address to its station address and enables its receiver if the addresses match. Slave stations that are not addressed continue monitoring the data stream for the next address character. An address character marks the beginning of a new block of data. After receiving a block of data, the slave station’s CPU may disable the channel receiver and re-initiate the process. 222DSR00 Automatic Echo Mode Extra Storage for the A / D Tag The unique feature of XR88C92 / XR88C192 is that the user need not wait at all in order to change the A / D tag from address to data (whereas in the case of SC26C92, a wait of at least 2 bit times is required before changing the A / D tag). This allows the user to possibly load the entire polling packet data to the TX FIFO. 10 Rev 1.35 XR88C92 / XR88C192 Dual Universal Asynchronous Receiver and Transmitter Data Sheet Watchdog Timer Watchdog Timer Counter Mode Each of the two receivers (channel A and B) has its own ’watchdog timer’ which is separate from and independent of the Counter / Timer. The watchdog timer is used to generate a receive ready time-out interrupt. When enabled, a counter is started every time a character is transferred from the receive shift register to the receive FIFO. It times out after 64 bit times, at which point a receive interrupt is generated. This is a useful feature especially when the incoming data is not a continuous stream of data. For example, if RX trigger levels are used and the last set of characters is smaller than the trigger level, a receive timeout interrupt is generated instead of a regular receive interrupt. The watchdog timer, however, is not accurate as it uses the incoming data for its timing. For more accurate timing, the timeout mode in the Counter / Timer should be used (see below). In counter mode, the CPU can start and stop the C / T. This mode allows the C / T to function as a system stopwatch or a real-time single interrupt generator. In this mode, the C / T counts down from the pre-load value using the programmed counter clock source. When a read at the start counter command register (address 0xE) is performed, the counter is initialized to the pre-load value and begins a countdown sequence. When the counter counts from 0x0001 to 0x0000 (terminal count), the C/T ready bit in the interrupt status register (ISR bit 3) is set. Users can program the counter to generate an interrupt request for this condition on the -INT output by unmasking the bit 3 in the Interrupt Mask Register (IMR, address 0x5). After 0x0000, the count becomes 0xFFFF and the counter continues counting down from there. If the CPU changes the pre-load value, the counter will not recognize the new value until it receives the next start counter command (and is re-initialized). When a read at the stop counter command register (address 0xF) is performed, the counter stops the countdown sequence and clears ISR bit 3. The count value should only be read while the counter is stopped because only one of the count registers (either CUR, at address 0x6 or CLR, at address 0x7) can be read at a time. If the counter is running, a decrement of CLR that requires a borrow from the CUR could take place between the two register reads. Figure 7 shows the C / T output in the counter mode. OP3 can be programmed to show the C / T output. Counter / Timer The 16-bit counter / timer (C / T) can operate in a counter mode or a timer mode. In either mode, users can program the C / T input clock source to come from several sources (see Auxiliary Control Register (ACR) bits 6:4) and program the C / T output to appear on output port pin OP3 (see Output Port Configuration Register (OPCR) - Write Only bits 3:2). The (pre-load) value stored in the concatenation of the C / T upper register (CTPU, address 0x6) and the C / T lower register (CTPL, address 0x7) can be from 0x0001 through 0xFFFF and can be changed at any time. At power-up and after reset, the C / T operates in counter mode. Figure 7: C/T Output in Timer and Counter Modes 222DSR00 11 Rev 1.35 XR88C92 / XR88C192 Dual Universal Asynchronous Receiver and Transmitter Data Sheet Timer Mode In addition to the watchdog timer described above, the C / T can be used for a receive timeout function (see description in Command Register (CRA, CRB) also). The C / T is more accurate and the timeout period is programmable unlike the watchdog timer. However, only one channel can use the C / T for receive timeout at any given time. The C / T timeout mode uses the received data stream to start the counter. Each time a character is shifted from the receive shift register to the receive FIFO, the C / T is reloaded with the programmed value in CTPU and CTPL and it restarts on the next C / T clock. The timer sets the C / T ready bit in the interrupt status register (ISR bit 3) every other time it reaches the terminal count (at every rising edge of the output). Users can program the timer to generate an interrupt request for this condition (every second countdown cycle) on the -INT output. If the CPU changes the pre-load value, the timer will not recognize the new value until either: If a new character is not received before the C / T reaches terminal count (= 0x0000), a counter ready interrupt (ISR bit 3) is generated. The user can appropriately program the CTPU and CTPL for the desired timeout period. Typically, this is slightly more than one character time. Note that if C / T is used for receiver timeout, a counter ready interrupt is generated; whereas if the watchdog timer is used, a receiver ready interrupt is generated. When a read at the stop counter command address is performed, the timer clears ISR bit 3 but does not stop. Because in timer mode the C / T runs continuously, it should be completely configured (pre-load value loaded and start counter command issued) before programming the timer output to appear on OP3. (a) it reaches the next terminal count and is re-initialized automatically, or (b) it is forced to re-initialize by a start command. Other Programming Remarks Timer Mode The contents of internal registers should not be changed during receiver / transmitter operation as certain changes can produce undesired results. For example, changing the number of bits per character while the transmitter is active will result in transmitting an incorrect character. The contents of the clock select register (CSR) and ACR bit 7 should only be changed after the receiver(s) and transmitter(s) have been issued software RX and TX reset commands. Similarly, changes to the auxiliary control register (ACR bits 4-6) should only be made while the counter / timer (C / T) is not used. In the timer mode, the C / T runs continuously once the start command is issued (by reading the start C / T command register) and the CPU cannot stop it. When the stop command is issued (by reading the stop C / T command register), the CPU only resets the C / T interrupt. This mode allows the C / T to be used as a programmable clock source for channels A and B, see Clock Select Register (CSRA, CSRB), and / or a periodic interrupt generator. In this mode, the C / T generates a square-wave output (see Figure 7) derived from the programmed timer input clock source. The square wave generated by the timer has a period of 2X (pre-load value) X (period of clock source) and is available as a clock source for both channels A and B. Since the timer cannot be stopped, the values in the registers (CUR:CLR) should not be read. See the description of the Auxiliary Control Register (ACR) to see how to choose the clock source for the C / T. The mode registers of each channel MR0, MR1 and MR2 are accessed via an auxiliary pointer. The pointer is set to mode register one (MR1) by RESET. It can be set to MR0 or MR1 by issuing a "reset pointer" command (0xB0 or 0x10 respectively) via the channel’s command register. Any read or write of the mode register switches the pointer to next mode register. All accesses subsequent to reading or writing MR1 will address MR2 unless the pointer is reset to MR0 or MR1 as described above. The mode, command, clock select, and status registers are duplicated for each channel to allow independent operation and control (except that both channels are restricted to baud rates that are in the same set). When the start counter command register (STCR, address 0xE) is read, the C / T terminates the current countdown sequence and sets its output to a ’1’ (OP3 can be programmed to show this output). The C / T is then initialized to the pre-load value, and begins a new countdown sequence. When the terminal count is reached (0x0000), the C / T sets its output to a ’0’. Then, it gets reinitialized to the pre-load value and repeats the countdown sequence. See Figure 7 for the resulting waveform. 222DSR00 12 Rev 1.35 XR88C92 / XR88C192 Dual Universal Asynchronous Receiver and Transmitter Data Sheet Registers Registers Table 3: Internal Registers A3 A2 A1 A0 Read Operation Write Operation 0 0 0 0 Mode Register A (MR0A, MR1A, MR2A) Mode Register A (MR0A, MR1A, MR2A) 0 0 0 1 Status Register A (SRA) Clock Select Register A (CSRA) 0 0 1 0 Reserved Command Register A (CRA) 0 0 1 1 Receive Buffer A (RXA) Transmitter Buffer A (TXA) 0 1 0 0 Input Port Change Register (IPCR) Auxiliary Control Register (ACR) 0 1 0 1 Interrupt Status Register (ISR) Interrupt Mask Register (IMR) 0 1 1 0 Counter / Timer Upper Register (CUR) C/T Pre-load Value Upper Register (CTPU) 0 1 1 1 Counter / Timer Lower Register (CLR) C/T Pre-load Value Lower Register (CTPL) 1 0 0 0 Mode Register B (MR0B, MR1B, MR2B) Mode Register B (MR0B, MR1B, MR2B) 1 0 0 1 Status Register B (SRB) Clock Select Register B (CSRB) 1 0 1 0 Reserved Command Register B (CRB) 1 0 1 1 Receive Buffer B (RXB) Transmitter Buffer B (TXB) 1 1 0 0 General Purpose Register (GPR) General Purpose Register (GPR) 1 1 0 1 Input Port Register (IPR) Output Port Configuration Register (OPCR) 1 1 1 0 Start C/T Command (STCR) Set Output Port Register (SOPR) 1 1 1 1 Stop C/T Command (SPCR) Reset Output Port Register (ROPR) 222DSR00 13 Rev 1.35 XR88C92 / XR88C192 Dual Universal Asynchronous Receiver and Transmitter Data Sheet Registers p Table 4: Internal Register Descriptions A3 A2 A1 A0 Register [Default] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 MRA0[00] Watchdog timer RX trigger level [1] TX trigger level [1] TX trigger level [0] Not used Baud rate ext. 2 Factory test mode Baud rate ext. 1 1 0 0 0 MRB0[00] Watchdog timer RX trigger level [1] TX trigger level [1] TX trigger level [0] Not used Not used Not used Not used 0 0 0 0 MRA1[00] 1 0 0 0 MRB1[00] RX RTS control RX trigger level [0] Error mode Parity mode Parity mode Parity type Word length Word length 0 0 0 0 MRA2[00] 1 0 0 0 MRB2[00] Loopback mode select Loopback mode select TX RTS control Auto CTS control Stop bit length Stop bit length Stop bit length Stop bit length 0 0 0 1 SRA[00] 1 0 0 1 SRB[00] Received break Framing error Parity error Overrun error Tx empty Tx ready Rx FIFO full Rx ready 0 0 0 1 CSRA[00] 1 0 0 1 CSRB[00] RX clock RX clock RX clock RX clock TX clock TX clock TX clock TX clock 0 0 1 0 CRA[00] 1 0 1 0 CRB[00] Misc. command Misc. command Misc. command Misc. command TX disable TX enable RX disable RX enable 0 0 1 1 RXA[XX] 1 0 1 1 RXB[XX] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 1 1 TXA[XX] 1 0 1 1 TXB[XX] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 1 0 0 IPCR[00] Delta IP3 Delta IP2 Delta IP1 Delta IP0 IP3 input IP2 input IP1 input IP0 input 0 1 0 0 ACR[00] Baud rate set select C/T mode C/T mode C/T mode Delta IP3 int. Delta IP2 int. Delta IP1 int. Delta IP0 int. 0 1 0 1 ISR[00] Input port change Delta break B RxB ready TxB ready C/T ready Delta break A RxA ready TxA ready 0 1 0 1 IMR[00] Input port change Delta break B RxB ready TxB ready C/T ready Delta break A RxA ready TxA ready 0 1 1 0 CTPU[00] CUR[00] Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 1 1 1 CTPL[00] CLR[00] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 1 0 0 GPR[00] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 1 0 1 IPR[XX] Not used IP6 IP5 IP4 IP3 IP2 IP1 IP0 1 1 0 1 OPCR[00] OP7 OP6 OP5 OP4 OP3 OP3 OP2 OP2 1 1 1 0 STCR[XX] X X X X X X X X 1 1 1 0 SOPR[00] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 1 1 1 SPCR[XX] X X X X X X X X 1 1 1 1 ROPR[00] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 222DSR00 14 Rev 1.35 XR88C92 / XR88C192 Data Sheet Mode Register 0 (MR0A, MR0B) Mode Register 0 (MR0A, MR0B) This register is accessed only when the command is applied via the CRA, CRB registers (upper nibble = 0xB). After reading or writing to the MR0A (or MR0B) register, the mode register pointer will point to the MR1A (or MR1B) register. MR0A, MR0B Bit 6: Receive trigger level select. This bit is associated with MR1 Bit-6. MR0A Bit 0: Extended baud rate table selection for both channels. ■ ■ 0 = Normal baud rate tables MR1 Bit 6 XR88C92 0 0 1 byte in FIFO (default) 0 1 3 bytes in FIFO 1 0 6 bytes in FIFO 1 1 8 bytes in FIFO MR0 Bit 6 MR1 Bit 6 XR88C192 0 0 1 byte in FIFO (default) 0 1 6 bytes in FIFO 0 = Normal 1 0 12 bytes in FIFO 1 = Factory test mode 1 1 16 bytes in FIFO 1 = Extended baud rate tables 1 MR0A Bit 1: Special Function ■ ■ MR0 Bit 6 MR0A Bit 2: MR0A, MR0B Bit 7: Extended baud rate table selection for both channels. Receive time-out (watchdog timer). ■ ■ ■ ■ 0 = Normal baud rate tables 1 = Extend baud rate tables 2 Not Used. Any write to this bit is ignored. Mode Register 1 (MR1A, MR1B) MR0A, MR0B Bits 5-4: MR1A, MR1B are accessed after reset or by a command applied via the CRA, CRB registers (upper nibble = 0x1). After reading or writing to the MR1A (or MR1B) register, the mode register pointer will point to the MR2A (or MR2B) register. Transmit trigger level select. Bit 4 XR88C92 0 0 8 FIFO locations empty (default) 0 1 4 FIFO locations empty 1 0 6 FIFO locations empty 1 1 1 FIFO location empty Bit 5 Bit 4 XR88C192 0 0 16 FIFO locations empty (default) 0 1 6 FIFO locations empty 1 0 12 FIFO locations empty 1 1 1 FIFO location empty 222DSR00 1 = Enabled See description under Watchdog Timer. MR0A Bit 3, MR0B Bits 3-0: Bit 5 0 = Disabled (default) MR1A, MR1B Bits 1-0: Character Length 15 00 5 (default) 01 6 10 7 11 8 Rev 1.35 XR88C92 / XR88C192 Data Sheet Mode Register 2 (MR2A, MR2B) MR1A, MR1B Bit 2: MR2A, MR2B Bits 3-0: Stop Bit Length In non-Multidrop mode, this bit selects the parity. ■ ■ Stop Bit Length 0 = Even parity (default) 0000 0.563 (default) 1 = Odd parity 0001 0.625 0010 0.688 0011 0.750 0100 0.813 0101 0.875 In Multidrop mode, this bit is the Address / Data flag. ■ ■ 0 = Data (default) 1 = Address MR1A, MR1B Bit 4-3: Parity Mode Parity Mode 00 With parity (default) 01 Force parity 10 No parity 11 Multidrop mode MR1A, MR1B Bit 5: Data Error Mode ■ ■ 0.938 0111 1.000 1000 1.563 1001 1.625 1010 1.688 1011 1.750 1100 1.813 1101 1.875 1110 1.938 1111 2.000 0 = Single character mode (default) 1 = Block (FIFO) mode MR2A, MR2B Bit 4: Auto CTS Flow Control ■ ■ MR1A, MR1B Bit 6: Receive trigger levels. See description under MR0A, MR0B Bit 6: ■ ■ 0 = No RX RTS control function (default) 1 = Auto RX RTS control function 1 = Auto CTS flow control enabled 0 = No auto TX RTS control (default) 1 = Auto transmit RTS function enabled The output OP0 (OP1) serves as the -RTS signal for channel A (channel B). Note that only one of MR1 bit 7 or MR2 bit 5 should be set to '1'. The output OP0 (OP1) serves as the -RTS signal for channel A (channel B). Note that MR2 A/B bit 5 also controls OP0 (OP1). Only one of MR1 bit 7 or MR2 bit 5 should be set to '1'. MR2A, MR2B Bit 7-6: Loopback Mode Select Loopback Mode Select Mode Register 2 (MR2A, MR2B) This register is accessed after any read or write operation to the MR1A (or MR1B) register is performed. Any read or write to MR2A (or MR2B) does not change the mode register pointer. Use one of the two reset MR pointer commands, see Command Register (CRA, CRB), to reset the pointer to MR0 or MR1. 222DSR00 0 = No auto CTS flow control (default) MR2A, MR2B Bit 5: Auto Transmit RTS Control MR1A, MR1B Bit 7: Receive RTS Flow Control ■ ■ 0110 16 00 No loopback (default) 01 Automatic echo 10 Local loopback 11 Remote loopback Rev 1.35 XR88C92 / XR88C192 Dual Universal Asynchronous Receiver and Transmitter Data Sheet Status Register (SRA, SRB) Status Register (SRA, SRB) SRA, SRB Bit 0: Receive Ready SRA, SRB Bit 6: Framing Error This bit indicates that one or more character(s) has been received and is waiting in the FIFO for the CPU to be read. It is set when the first character is transferred from the receive shift register to the empty FIFO, and cleared when the CPU reads the receiver buffer and there are no more characters in the FIFO after the read. This bit is set when a stop bit was not detected when the corresponding data character in the FIFO was received. The stop bit check is made in the middle of the first stop bit position. At least one bit in the received character (data or parity) must have been a “1” to signal a framing error. After a framing error, the receiver does not wait for the line to return to the marking state (high). If the line remains low for 1/2 a bit time after the stop bit sample (that is, the nominal end of the first stop bit), the receiver treats it as the beginning of a new start bit.This bit is valid only when the RxRDY bit is set (SRA, SRB bit 0 = 1). SRA, SRB Bit 1: Receive FIFO Full This bit is set when a character is transferred from the receive shift register to the receiver FIFO and the transfer fills the FIFO. All eight (or 16 in the XR88C192) FIFO locations are occupied. It is cleared when the CPU reads the receiver buffer, unless another character is in the receive shift register waiting for an empty FIFO location. SRA, SRB Bit 7: Received Break This bit indicates a character with all data bits being zero has been received without a stop bit. This bit is valid only when the RxRDY bit is set (SRA, SRB Bit 0 = 1). Only a single FIFO position is occupied when a break is received; for longer break signals, additional entries to the FIFO are inhibited until the channel A/B receiver serial data input line returns to the marking state. The break-detect circuitry can detect a break that starts in the middle of a received character, however the break condition must persist completely through the end of the current character and the next character time to be recognized as a break signal. SRA, SRB Bit 2: Transmit Ready This bit (when set) indicates that the transmit FIFO is not full. The transmitter ready bit is set when the transmit FIFO has at least one empty location. This bit is cleared when the transmit FIFO is full. SRA, SRB Bit 3: Transmit Empty This bit will be set when the channel's transmitter is empty. It indicates that both the transmit FIFO and the transmit shift register are empty. It is set after transmission of the last stop bit of the last character in the TX FIFO. It is cleared when the CPU loads a character into the transmit FIFO or when the transmitter is disabled. Clock Select Register (CSRA, CSRB) Transmit / Receive baud rates for channels A, B can be selected via this register. SRA, SRB Bit 4: Overrun Error CSRA, CSRB Bits 3-0: This bit is set when one or more characters in the received data stream have been lost. It is set on receipt of a valid start bit when the FIFO is full and a character is already in the receive shift register waiting for an empty FIFO position. When this occurs, the character in the receive shift register (and its break detect, parity error and framing error status, if any) is overwritten. A reset error status command clears this bit. Transmit clock select (see baud rate table, Table 5). CSRA, CSRB Bits 7-4: Receive clock select (see baud rate table, Table 5). SRA, SRB Bit 5: Parity Error This bit is set when the “with parity” or “force parity” mode is programmed by MR1A (or MR1B) and an incoming character is received with incorrect parity. In the Multidrop mode, the parity error bit position stores the received address / data tag. This bit is valid only when the RxRDY bit is set (SRA, SRB bit 0 = 1). 222DSR00 17 Rev 1.35 XR88C92 / XR88C192 Data Sheet Clock Select Register (CSRA, CSRB) Table 5: Baud Rate Table for a 3.6864MHz Clock. Data Rates Double for a 7.3728MHz Clock. CSRA, CSRB Bits 7:4 or Bits 3:0 MR0A Bits 2, 0 = 0 MR0A Bit 0 = 1, Bit 2 = 0 (extended table 1) MR0A Bit 0 = 0, Bit 2 = 1 (extended table 2) Set 1 ACR Bit 7 = 0 Set 1 ACR Bit 7 = 0 Set 1 ACR Bit 7 = 0 Set 2 ACR Bit 7 = 1 Set 2 ACR Bit 7 = 1 Set 2 ACR Bit 7 = 1 0000 (default) 50 75 300 450 4800 7200 0001 110 110 110 110 880 880 0010 134.5 134.5 134.5 134.5 1076 1076 0011 200 150 1200 900 19.2k 14.4k 0100 300 300 1800 1800 28.8k 28.8k 0101 600 600 3600 3600 57.6k 57.6k 0110 1200 1200 7200 7200 115.2k 115.2k 0111 1050 2000 1050 2000 1050 2000 1000 2400 2400 14.4k 14.4k 57.6k 57.6k 1001 4800 4800 28.8k 28.8k 4800 4800 1010 7200 1800 7200 1800 57.6k 14.4k 1011 9600 9600 57.6k 57.6k 9600 9600 1100 38.4k 19.2k 230.4k 115.2k 38.4k 19.2k 1101 Timer Timer Timer Timer Timer Timer (1) IP3 - 16X (CSRA 3:0), IP4 - 16X (CSRA 7:4), IP5 - 16X (CSRB 3:0), IP6 - 16X (CSRB 7:4) (1) IP3 - 1X (CSRA 3:0), IP4 - 1X (CSRA 7:4), IP5 - 1X (CSRB 3:0), IP6 - 1X (CSRB 7:4) 1110 1111 1. Baud rate is independent of MR0 bit 0 and bit 2 and ACR bit 7 settings. 222DSR00 18 Rev 1.35 XR88C92 / XR88C192 Data Sheet Command Register (CRA, CRB) Command Register (CRA, CRB) The CRA, CRB register is used to supply commands to channels A and B respectively. Multiple commands can be specified in a single write to CRA, CRB as long as commands are non-conflicting. 1010 Set timeout mode on. The receiver in this channel will restart the C / T as each receive character is transferred from the shift register to the receive FIFO. The C / T is placed in the counter mode, the START / STOP counter commands are disabled, the counter is stopped and the counter ready bit, ISR Bit 3 is reset. (See also Watchdog Timer description). 1011 Set MR pointer to MR0. 1100 Disable timeout mode. This command returns control of the C / T to the regular Start / Stop counter commands. It does not stop the counter or clear any pending interrupts. After disabling the timeout mode, a “Stop Counter” command should be issued to force a reset of the ISR Bit-3. 1101 Not used. 1110 Enable power down mode. In this mode, the DUART oscillator is stopped and all functions requiring this clock are suspended. The execution of commands other than disable power down mode (1111) requires an XTAL1. While in the power down mode, do not issue any commands to the CRA or CRB except the disable power down mode command. The contents of all registers will be saved while in this mode. It is recommended that the transmitter and receiver be disabled prior to placing the DUART into power down mode. This command is in CRA only. 1111 Disable power down mode. This command restarts the oscillator. After invoking this command, wait for the oscillator to start up before writing further commands to the CRA/B. For maximum power reduction all input pins should be at GND or VCC. This command is in CRA only. CRA, CRB Bits 1-0: Receiver Commands Receiver Commands 00 No action, stays in present mode (default) 01 Receiver enabled 10 Receiver disabled 11 Don’t use CRA, CRB Bits 3-2: Transmitter Commands Transmitter Commands 00 No action, stays in present mode (default) 01 Transmitter enabled 10 Transmitter disabled 11 Don’t use CRA, CRB Bits 7-4: Miscellaneous Commands Miscellaneous Commands 0000 No command (default) 0001 Reset MR pointer to MR1 0010 Reset receiver. Receiver is disabled and FIFO is flushed. 0011 Reset transmitter. Transmitter is disabled and FIFO is flushed. 0100 Reset error status. Clears channel A/B, break, parity, and overrun error bits in the status register. 0101 Reset channel's break-change interrupt. Clears channel A/B break detect change bit in the interrupt status register (ISR bit-2 for channel A and ISR bit-6 for channel B). 0110 Start break. Forces the transmitter output to go low and stay low. If transmitter is empty, the start of the break condition will be delayed up to two bit times. If transmitter is active, all the characters in the FIFO are transmitted before break signal is sent. Transmitter must be enabled for this command to work. 0111 Stop break. Transmit output will go high within two bit times. 1000 Set -RTS output to low (assertion). 1001 Reset -RTS output to high (negation). 222DSR00 Receive Buffer (RXA, RXB) The receive buffer consists of an 8-character deep FIFO in the XR88C92 and a 16-character deep FIFO in the XR88C192. The received characters are transferred from the shift register one at a time to the FIFO and are stored there until read by the CPU or flushed by a reset receiver command. Transmit Buffer (TXA, TXB) The transmit buffer consists of an 8-character deep FIFO in the XR88C92 and a 16-character deep FIFO in the XR88C192. Once loaded in the FIFO, the characters are transferred to the transmit shift register one at a time and transmitted unless the transmitter is disabled. 19 Rev 1.35 XR88C92 / XR88C192 Data Sheet Input Port Change Register (IPCR) Input Port Change Register (IPCR) This is a read-only register which gives the state and the change-of-state information of the multi-purpose inputs IP0, IP1, IP2 and IP3. IPCR Bits 3-0: Levels of IP3 - IP0 These show the current state of IP3, IP2, IP1 and IP0 respectively. ■ ■ 0 = Low 1 = High ACR Bits 6:4 C/T Mode Clock Source 000 Counter External (IP2) 001 Counter TXA Clk1 - Transmit A 1X clock 010 Counter TXB Clk1 - Transmit B 1X clock 011 Counter Crystal or external clock (XTAL1 / CLK) divided by 16 100 Timer External (IP2) 101 Timer External (IP2) divided by 16 110 Timer Crystal or external clock (XTAL1 / CLK) Timer Crystal or external clock (XTAL1 / CLK) divided by 16 111 IPCR Bits 7-4: Transitions of IP3 - IP0 These indicate if there has been a change of state in IP3, IP2, IP1 and IP0 respectively. They are cleared when the register is read by the CPU. ■ ■ ACR Bit 7: Baud Rate Table Select This bit is used to select between two sets of baud rate tables. See baud rate table, Table 5. It should be changed only after both channels have been reset and disabled. 0 = No 1 = Yes ■ ■ Auxiliary Control Register (ACR) 1 = Set 2 Interrupt Status Register (ISR) ACR Bits 3-0: This field selects which bits of the input port change register (IPCR) cause the interrupt status register (ISR) bit 7 to be set. For example, if bit 0 = 1, then a change of state in IP0 will set ISR bit 7. If bit 0 and bit 2 are both '1', then whenever IP0 or IP2 changes state, ISR bit 7 will be set. ■ ■ 0 = Set 1 This register provides the status of all potential interrupt sources. The contents of this register are logically “AND”-ed with the contents of the interrupt mask register, and the results are “OR”-ed. The resulting signal is inverted to produce the -INT output. All active interrupt sources are visible by reading the ISR, regardless of the contents of the interrupt mask register. Reading the ISR has no effect on any interrupt source. Each active interrupt source must be cleared in a source specific fashion to clear the ISR. All interrupt sources are cleared when the XR88C92 / XR88C192 is reset.4 0 = Disabled (default) 1 = Enabled ACR Bits 6-4: Counter / Timer Mode and Clock Source These bits should not be altered while the C / T is in use. Prior to changing these bits, the C / T must be stopped if in counter mode. If the C / T is in timer mode, its output must be disabled and its interrupt must be masked. The following table shows how to select the clock source for the C / T when used in counter mode or timer mode. ISR Bit 0: Transmit Ready A This bit is set when channel A's transmit buffer (FIFO) is filled below the programmed transmit trigger level (see MR0A bits 5-4). For example, if a TX trigger level of '4' is chosen, this bit will be set whenever the TX FIFO has four or more empty locations. This bit can be cleared by loading the TX FIFO above the trigger level. ISR Bit 1: Receive Ready A This bit is set when channel A's receive buffer (FIFO) is filled above the programmed receive trigger level condition (see MR0A bit 6 and MR1A bit 6). For example, if an RX 222DSR00 20 Rev 1.35 XR88C92 / XR88C192 Data Sheet Interrupt Mask Register (IMR) Interrupt Mask Register (IMR) trigger level of '6' is chosen, this bit will be set whenever the RX FIFO contains six or more bytes. This bit can be cleared by reading the data out of the FIFO until it falls below the trigger level. This register selects which bits in the interrupt status register can cause an interrupt output. If a bit in the interrupt status register is a “1” and the corresponding bit in this register is also a “1”, the -INT output will be asserted. If the corresponding bit in this register is a zero, the state of the bit in the interrupt status register has no effect on the -INT output. Note that the interrupt mask register does not have any effect on the programmable interrupt outputs OP7 through OP3 or the value read from the interrupt status register. ISR Bit 2: Channel A Change in Break This bit is set when the channel A receiver detects the beginning or the end of a break condition. It is reset when the CPU issues a channel A reset break change interrupt command (CRA bits 7-4 = 0x5). ISR Bit 3: Counter / Timer (C / T) Ready ■ ■ In counter mode, this bit is set when the C / T reaches terminal count. In timer mode, this bit is set each time the C / T output switches from low to high (rising edge - see Figure 7). In either mode, this bit is cleared by a stop counter command. 1 = Enable interrupt output for the event controlled by the corresponding bit in ISR. Counter / Timer Registers ISR Bit 4: Transmit Ready B The preload value Upper (CTPU) and Lower (CTPL) registers hold the most-significant byte and the least significant byte, respectively, of the value to be used by the C/T (in both counter and timer modes). The C/T Upper (CUR) and Lower Registers (CLR) give the current value of the C / T at the time that they are read. In the counter mode, the CUR and CLR should only be read when the counter is stopped. Upon receiving a start command after a stop command, the counter starts a fresh cycle and begins counting down from the original (preload) value written to CTPU and CTPL. Also changing the value of these registers does not take effect until the current cycle is stopped and a subsequent start command is issued. This bit is set when channel B's transmit buffer (FIFO) is filled below the programmed transmit trigger level (see MR0B bits 5-4). For example, if a TX trigger level of '4' is chosen, this bit will be set whenever the TX FIFO has four or more empty locations. This bit can be cleared by loading the TX FIFO above the trigger level. ISR Bit 5: Receive Ready B This bit is set when channel B's receive buffer (FIFO) is filled above the programmed receive trigger level condition (see MR0B bit-6 and MR1B bit-6). For example, if an RX trigger level of '6' is chosen, this bit will be set whenever the RX FIFO contains six or more bytes. This bit can be cleared by reading the data out of the FIFO until it falls below the trigger level. In the timer mode, the CUR and CLR registers cannot be read by the CPU. A stop command will not stop the timer, but will only clear the counter ready status bit in ISR (bit 3). Changing the value of the CTPU and CTPL registers when the timer is running will change the waveform after the current half-period of the square wave. For more details, see the Counter / Timer section. ISR Bit 6: Channel B Change in Break This bit is set when channel B receiver detects the beginning or the end of a break condition. It is reset when the CPU issues a channel B reset break change interrupt command (CRB bits 7-4 = 0x5). General Purpose Register (GPR) ISR Bit 7: Input Port Change Status This is a general purpose scratchpad register which can be used to store and retrieve one byte of user information. This bit is set when a change of state has occurred at the IP0, IP1, IP2, or IP3 inputs, and that event has been enabled to cause an interrupt by programming ACR Bits 3-0. This bit is cleared when the CPU reads the input port change register. 222DSR00 0 = Interrupt output (-INT) disabled (default) 21 Rev 1.35 XR88C92 / XR88C192 Data Sheet Input Port Register - Read Only Input Port Register - Read Only If OP3 is to be used for the timer output (a square wave of the programmed frequency), program the counter / timer for timer mode (ACR Bit 6 = 1), initialize the counter / timer pre-load registers (CTPU and CTPL), and read the 'Start C / T Command Register' (STCR) before setting OPCR Bits 3-2 = 01. In the counter mode, the output remains high until the terminal count is reached, at which time it goes low. The output becomes high again when the counter is stopped by a stop counter command. The current state of the multi-purpose inputs (IP0 - IP6) can be read via this register. IPR Bit 0-6: ■ ■ 0 = Inputs are in low state 1 = Inputs are in high state OP4 Output Select (Bit 4): IPR Bit 7: ■ ■ Not used and is set to “0”. Output Port Configuration Register (OPCR) - Write Only ■ ■ 0 0 Controlled by SOPR and ROPR (default) 0 1 TxA Clk16 - Transmit A 16X clock 1 0 TxA Clk1 - Transmit A 1X clock 1 1 RxA Clk1 - Receive A 1X clock ■ ■ Bit 2 0 0 Controlled by SOPR and ROPR (default) 0 1 C/T output 1 0 TxB Clk1 - Transmit B 1X clock 1 1 RxB Clk1 - Receive B 1X clock 222DSR00 1 = -RxBRDY which is the complement of ISR bit 5 0 = Controlled by SOPR and ROPR (default) 1 = -TxARDY which is the complement of ISR bit 0 OP7 Output Select (Bit 7): ■ ■ 0 = Controlled by SOPR and ROPR (default) 1 = -TxBRDY which is the complement of ISR bit 4 Start Counter / Timer Register (STCR) - Read Only OP3 Output Select Bit 3 0 = Controlled by SOPR and ROPR (default) OP6 Output Select (Bit 6): OP2 Output Select Bit 0 1 = -RxARDY which is the complement of ISR bit 1 OP5 Output Select (Bit 5): This register selects the following options for the multipurpose outputs OP2 to OP7.4Alternate functions of OP1 and OP0 are controlled by the mode registers, not the OPCR: MR1A Bit 7 and MR2A Bit 5 control OP0; MR1B Bit 7 and MR2B Bit 5 control OP1. For more details on these, see Multi-Purpose Outputs (OP0 - OP7). Bit 1 0 = Controlled by SOPR and ROPR (default) Reading from this register will start the C / T. Data values returned should be ignored. Stop Counter / Timer Register (SPCR) - Read Only Reading from this register will stop the C / T. Data values returned should be ignored. 22 Rev 1.35 XR88C92 / XR88C192 Data Sheet Set Output Port Register (SOPR) - Write Only Set Output Port Register (SOPR) Write Only Reset Output Port Register (ROPR) Write Only Output ports (OP0-OP7), when used as general purpose outputs, can be asserted (set to low) by writing a “1” to the corresponding bit in this register. Once an output is asserted, it can be negated only by issuing a command through the Reset Output Port Register (ROPR) - Write Only. Each output port bit can be changed to a high state by writing a “1” to each individual bit. ROPR Bit 0-7: ■ ■ However, note that SOPR and ROPR cannot be used to assert and negate outputs that are programmed for alternate functions (see description under Output Port Configuration Register (OPCR) - Write Only). For example, if OP0 is programmed to output -RTSA, see Multi-Purpose Outputs (OP0 - OP7), it cannot be controlled by SOPR or ROPR. In that case, commands from the Command Register should be issued to assert (CRA bits 7:4 = 0x8) and negate (CRA bits 7:4 = 0x9) OP0. 0 = No change (same state) 1 = Negate the corresponding output (set it high) SOPR Bit 0-7: ■ ■ 0 = No change (same state) 1 = Assert the corresponding output (set it low) 222DSR00 23 Rev 1.35 XR88C92 / XR88C192 Dual Universal Asynchronous Receiver and Transmitter Data Sheet Programming Examples Programming Examples The following examples show how to initialize the XR88C92 / XR88C192 for various operating conditions: Example A Initialize channel A of an XR88C92 device for regular RX / TX. The operating parameters will be 9600 baud, 8 word length, no parity, and 1 stop bit. Operation Register Value Remarks Write CRA 0x20 ; reset RX (receiver) Write CRA 0x30 ; reset TX (transmitter) Write CRA 0x40 ; reset error status Write CRA 0xB0 ; reset MR pointer to MR0 Write MR0A 0x00 ; use normal baud rate table. Now MR pointer points to MR1. Write MR1A 0x13 ; select word length & parity. Now MR pointer points to MR2. Write MR2A 0x07 ; normal mode (not loopback) & 1 stop bit Write CSRA 0xBB ; 9600 baud for RX & TX - clock source is XTAL1 Write CRA 0x05 ; enable RX & TX Read SRA ; should get a value 0x0C Example B How to use hardware flow control for both RX (RTS via OP0) and TX (CTS via IP0): Operation Register Value Remarks Write CRA 0x10 ; reset MR pointer to MR1 Write MR1A 0x93 ; select auto RTS control. The -RTS signal is sent via output OP0. Write MR2A 0x17 ; select auto CTS control. The input IP0 serves as the -CTS signal. 222DSR00 24 Rev 1.35 XR88C92 / XR88C192 Dual Universal Asynchronous Receiver and Transmitter Data Sheet Programming Examples Example C Configure clock sources for TX and RX of both channels and C / T. Specifically, XTAL1 will be used as channel A's TX clock; IP4 as channel A's 16X RX clock; IP5 as channel B's 1X TX clock and XTAL1 as channel B's RX clock. Also, the C / T will be initialized in the timer mode and IP2 will be used as its clock source. Some of these will be programmed to appear at the multi-purpose output pins: Operation Register Value Remarks Write ACR 0x40 ; C / T initialized in timer mode & IP2 chosen as its clock source ; also, bit-7 = 0, therefore baud rate Set1 has been selected Write CTPU 0x00 ; It is essential to program CTPU & CTPL before programming OP3 Write CTPL 0x05 ; as C / T output (see below) Write CSRA 0xEB ; channel A RX clock source: IP4-16X, TX clock source: XTAL1 (if MR0A ; bits 2 and 0 = 0, the TX baud rate is 9600) Write CSRB Read STCR Write OPCR 0xBF ; channel B RX clock source: XTAL1 (9600 baud), TX clock source: IP5-1X ; Start the C / T 0x06 ; C / T output appears at OP3 and channel A's TX 1X clock (this is XTAL1 ; clock divided by 16) at OP2. Example D Configure and run channel B's transmitter in a multi-drop application. Note that all other relevant parameters should be configured already, such as baud rate etc. Operation Register Value Remarks Write CRB 0x10 ; reset MR pointer to MR1 Write MR1B 0x1B ; word length = 8 and use A / D tag in the place of parity Write CRB 0x04 ; Enable transmitter of channel B Write TXB address ; Send the address first (A / D tag = 1) Write CRB 0x10 ; reset MR pointer to MR1 Write MR1B 0x13 ; change A / D tag = 0 Write TXB data ; You can load the data (A / D tag = 0) immediately after the address. There ; is no need to wait until the transmitter is empty. Load all the data. Read SRB ; Check to see if the transmitter is empty & ready. You need to do this ; before you can load the next address. ; Repeat the last 5 steps to load different addresses and their data. 222DSR00 25 Rev 1.35 XR88C92 / XR88C192 Dual Universal Asynchronous Receiver and Transmitter Data Sheet Specifications Specifications Absolute Maximum Ratings Table 6: Absolute Maximum Ratings Parameter Minimum Maximum Units 7.0 V GND - 0.3 VCC + 0.3V V 0 70 °C –65 150 °C Power supply range Voltage at any pin Operating temperature Storage temperature Package dissipation 500 mW Electrical Characteristics DC Electrical Characteristics TA = 0°C - 70°C, VCC = 3.3V - 5.0V ± 10% unless otherwise specified. Table 7: Electrical Characteristics Test Condition Limits (3.3V) Limits (5.0V) Parameter Symbol Clock input low level VILCK –0.3 0.6 –0.5 0.6 V Clock input high level (top mark date code of "CC" and older) VIHCK 2.4 VCC 3.0 VCC V Clock input high level VIHCK (top mark date code of "D2" and newer) 2.4 5.5 3.0 5.5 V Minimum Maximum Minimum Maximum Units Input low level VIL –0.3 0.8 –0.5 0.8 V Input high level (top mark date code of "CC" and older) VIH 2.0 VCC 2.2 VCC V Input high level VIH (top mark date code of "D2" and newer) 2.0 5.5 2.2 5.5 V 0.4 V Output low level on all outputs VOL IOL = 8mA Output low level on all outputs VOL IOL = 5mA Output high level VOH IOH = -8mA Output high level VOH IOH = -1mA Input leakage IIL ±10 ±10 µA Clock leakage ICL ±10 ±10 µA Average power supply current ICC 1.0(1) 1.5(1) mA Average power-down supply current IPD XR88C92 40(1) 70(1) µA Average power-down supply current IPD XR88C192 100(1) 150(1) µA Input capacitance CP 5 5 pF 0.4 V 2.4 V 2.4 V 1. All inputs tied to VCC / GND. 222DSR00 26 Rev 1.35 XR88C92 / XR88C192 Data Sheet Electrical Characteristics AC Electrical Characteristics TA = 0°C - 70°C, VCC = 3.3V - 5.0V ± 10% unless otherwise specified. Table 8: AC Electrical Characteristics Limits 5.0V Symbol Clock pulse duration T1W, T2W Oscillator / clock Frequency T3W Address valid to -CS low TAS 0 0 ns -CS high to address invalid TAH 0 0 ns -IOR / -IOW setup time to -CS low TRWS 0 0 ns -IOR / -IOW hold time to -CS high TRWH 0 0 ns -CS low to data valid (read) TDD Data valid to -CS high (write) TDS 20 10 ns -CS high to data invalid (write) TDH 1 1 ns -CS high to data hi-Z (read) TDF -CS low pulse width TCSL 100 70 ns -CS high pulse width TCSH 100 70 ns Port input setup time T9S 0 0 ns Port input hold time T9H 0 0 ns Delay from IOW# to output T10d 110 110 ns Delay to reset interrupt from -IOR / -IOW T11d 100 100 ns Reset pulse width TR 2 Baud rate divisor N 1 222DSR00 Test Condition Limits 3.3V Parameter Minimum Maximum Minimum 17 17 8 32 30 20 2 216 - 1 1 Units ns 24 51 27 Maximum MHz ns ns clks 216 - 1 clks Rev 1.35 XR88C92 / XR88C192 Dual Universal Asynchronous Receiver and Transmitter Data Sheet Electrical Characteristics Figure 8: Bus Timing (Read / Write Cycle) IP6-IP0 T 9s T 9h -IOR XR92-IP Figure 9: Input Port Timing -IOW T10d OP7-OP0 O ld D a ta N e w D a ta XR92-OP Figure 10: Output Port Timing 222DSR00 28 Rev 1.35 XR88C92 / XR88C192 Dual Universal Asynchronous Receiver and Transmitter Data Sheet RX D1 D2 D8 D9 D10 D11 Electrical Characteristics D12 D13 D12, D13 Will be lost due to RX disable RX ENABLE -RxRDY -FFULL -RxRDY/ -FFULL -IOR Status Data (D1) D11 Will be lost due to overrun OVERRUN ERROR Status Data (D2) Status Data (D3) Status Data (D10) Reset by command -RTS XR92-RX Figure 11: Receive Timing TX D1 D2 D3 Break D4 D5 TX ENABLE -TxRDY -IOW -CTS -RTS XR692-TX Figure 12: Transmit Timing 222DSR00 29 Rev 1.35 XR88C92 / XR88C192 Dual Universal Asynchronous Receiver and Transmitter Data Sheet Electrical Characteristics -IOW -IOR T11d -INT T11d XR92-NT Figure 13: Interrupt Timing T1w T2w ExCLK XR92-CK T3w Figure 14: External Clock Timing 222DSR00 30 Rev 1.35 XR88C92 / XR88C192 Dual Universal Asynchronous Receiver and Transmitter Data Sheet Mechanical Dimensions Mechanical Dimensions PLCC44 TOP VIEW SIDE VIEW 1 SIDE VIEW 2 TERMINAL DETAILS Drawing No.: POD-000000151 Revision: A Figure 15: Mechanical Dimension, PLCC44 222DSR00 31 Rev 1.35 XR88C92 / XR88C192 Dual Universal Asynchronous Receiver and Transmitter Data Sheet Mechanical Dimensions Mechanical Dimensions LQFP44 B Figure 16: Mechanical Dimensions, LQFP44 222DSR00 32 Rev 1.35 XR88C92 / XR88C192 Dual Universal Asynchronous Receiver and Transmitter Data Sheet Disclaimer Ordering Information Table 9: Ordering Information Ordering Part Number Operating Temperature Range Package Packaging Method Lead-Free XR88C92CJ-F 0°C to 70°C PLCC44 Tube Yes XR88C192CV-F 0°C to 70°C LQFP44 Tray Yes Note: For the most up-to-date ordering information and additional information on environmental rating, go to www.maxlinear.com/XR88C92 and www.maxlinear.com/XR88C192. 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