XRA1200 / XRA1200P
8-bit I2C / SMBUS GPIO Expander
February 2, 2022
Rev. 1.0.2
GENERAL DESCRIPTION
FEATURES
1.65V to 3.6V operating voltage
8 General Purpose I/Os (GPIOs)
5V tolerant inputs
Maximum stand-by current of 1uA at +1.8V
The XRA1200/1200P is an 8-bit GPIO expander with
After power-up, the
an I2C/SMBus interface.
XRA1200 has internal 100K ohm pull-up resistors on
each I/O pin that can be individually enabled. The
XRA1200P have the internal pull-up resistors
enabled upon power-up in case it is necessary for the
inputs to be in a known state.
I2C/SMBus bus interface
I2C clock frequency up to 400kHz
Noise filter on SDA and SCL inputs
In addition, the GPIOs on the XRA1200/1200P can
individually be controlled and configured. As outputs,
the GPIOs can be outputs that are high, low or in
three-state mode. The three-state mode feature is
useful for applications where the power is removed
from the remote devices, but they may still be
connected to the GPIO expander.
As inputs, the internal pull-up resistors can be
enabled or disabled and the input polarity can be
inverted. The interrupt can be programmed for
different behaviors.
The interrupts can be
programmed to generate an interrupt on the rising
edge, falling edge or on both edges. The interrupt
can be cleared if the input changes back to its original
state or by reading the current state of the inputs.
The XRA1200/1200P are enhanced versions of other
8-bit GPIO expanders with an I2C/SMBus interface.
The XRA1200 is pin and software compatible with the
CAT9534 and PCA9534. The XRA1200P is pin and
software compatible with the CAT9554 and
PCA9554.
The XRA1200/1200P are also pin
compatible with the PCA9554A and TCA9554A.
Up to 32 I2C Slave Addresses
Individually programmable inputs
Internal pull-up resistors
Polarity inversion
Individual interrupt enable
Rising edge and/or Falling edge interrupt
Input filter
Individually programmable outputs
Output Level Control
Output Three-State Control
Open-drain active low interrupt output
Pin and software compatible with CAT9534,
CAT9554, PCA9534, and PCA9554
3kV HBM ESD protection per JESD22-A114F
200mA latch-up performance per JESD78B
APPLICATIONS
Personal Digital Assistants (PDA)
Cellular Phones/Data Devices
Battery-Operated Devices
Global Positioning System (GPS)
Bluetooth
The XRA1200/1200P are available in 16-pin QFN
and 16-pin TSSOP packages.
TSSOP-16 versions available,
QFN-16 versions obsolete
1
XRA1200 / XRA1200P
8-bit
I2C
/ SMBUS GPIO Expander
FIGURE 1. XRA1200 BLOCK DIAGRAM
VCC
(1.65V – 3.6V)
SCL
SDA
I2C/
SMBus
Interface
A2
A1
A0
GPIO
Control
Registers
P0
P1
P2
P3
P4
P5
P6
P7
GPIOs
IRQ#
GND
ORDERING INFORMATION
PART NUMBER
NUMBER OF
GPIOS
OPERATING TEMPERATURE
RANGE
PACKAGE
PACKAGE
METHOD
LEAD-FREE
XRA1200IG16TR-F
8
-40°C to +85°C
TSSOP-16
Tape and Reel
Yes
XRA1200PIG16TR-F
8
-40°C to +85°C
TSSOP-16
Tape and Reel
Yes
NOTE: For more information about part numbers, as well as the most up-to-date ordering information and additional information on
environmental rating, go to www.maxlinear.com/XRA1200 and www.maxlinear.com/XRA1200P.
SDA
16 15 14 13
15 SDA
A2 3
14 SCL
A0
16 VCC
A1 2
A1
A0 1
12 SCL
A2
1
P0
P1
2 XRA1200/ 11 IRQ#
XRA1200P
3 16-Pin QFN 10 P7
P2
4
P0 4
P1 5
9 P6
P5
P4
GND
5 6 7 8
P3
228DSR00
VCC
FIGURE 2. PIN OUT ASSIGNMENTS TSSOP-16 VERSIONS AVAILABLE, QFN-16 VERSIONS OBSOLETE
2
XRA1200/
XRA1200P
16-Pin TSSOP
13 IRQ#
12 P7
P2 6
11 P6
P3 7
10 P5
GND 8
9 P4
Rev. 1.0.2
2
XRA1200 / XRA1200P
8-bit I C / SMBUS GPIO Expander
PIN DESCRIPTIONS
Pin Description TSSOP-16 versions available, QFN-16 versions obsolete
NAME
QFN-16 TSSOP-16
TYPE
PIN#
PIN#
DESCRIPTION
I2C INTERFACE
SDA
13
15
I/O
SCL
12
14
I
IRQ#
11
13
OD
A0
A1
A2
15
16
1
1
2
3
I
I
I
2
3
4
5
7
8
9
10
4
5
6
7
9
10
11
12
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
General purpose I/Os P0-P7. All GPIOs are configured as inputs upon
power-up. After power-up, the internal pull-up resistors are enabled for the
XRA1200P. The internal pull-up resistors are disabled for the XRA1200.
I2C-bus data input/output (open-drain).
I2C-bus serial input clock.
Interrupt output (open-drain, active LOW).
These pins select the I2C slave address. See Table 1.
GPIOs
P0
P1
P2
P3
P4
P5
P6
P7
ANCILLARY SIGNALS
VCC
14
16
Pwr
1.65V to 3.6V VCC supply voltage.
GND
6
8
Pwr
Power supply common, ground.
GND
Center
Pad
-
Pwr
The exposed pad at the bottom surface of the package is designed for thermal
performance. Use of a center pad on the PCB is strongly recommended for thermal conductivity as well as to provide mechanical stability of the package on the
PCB. The center pad is recommended to be solder masked defined with opening size less than or equal to the exposed thermal pad on the package bottom to
prevent solder bridging to the outer leads of the device. Thermal vias must be
connected to GND plane as the thermal pad of package is at GND potential.
Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.
228DSR00
3
Rev. 1.0.2
XRA1200 / XRA1200P
8-bit
1.0
I2C
/ SMBUS GPIO Expander
FUNCTIONAL DESCRIPTIONS
I2C-bus Interface
1.1
The I2C-bus interface is compliant with the Standard-mode and Fast-mode I2C-bus specifications. The I2C-bus
interface consists of two lines: serial data (SDA) and serial clock (SCL). In the Standard-mode, the serial clock
and serial data can go up to 100 kbps and in the Fast-mode, the serial clock and serial data can go up to 400
kbps.
The first byte sent by an I2C-bus master contains a start bit (SDA transition from HIGH to LOW when SCL is
HIGH), 7-bit slave address and whether it is a read or write transaction. The next byte is the sub-address that
contains the address of the register to access. The XRA120x responds to each write with an acknowledge
(SDA driven LOW by XRA1200/1200P for one clock cycle when SCL is HIGH). The last byte sent by an I2Cbus master contains a stop bit (SDA transition from LOW to HIGH when SCL is HIGH). See Figures 3 - 5
below. For complete details, see the I2C-bus specifications.
FIGURE 3. I2C START AND STOP CONDITIONS
SDA
SCL
S
P
START condition
STOP condition
FIGURE 4. MASTER WRITES TO SLAVE
S
SLAVE
ADDRESS
W
A
COMM AND
BYTE
A
DATA
BYTE
A
P
W h ite b lo c k : h o s t to X R A 1 2 0 x
G re y b lo c k : X R A 1 2 0 x to h o s t
FIGURE 5. MASTER READS FROM SLAVE
S
SLAVE
ADDRESS
W
A
COMMAND
BYTE
A
S
SLAVE
ADDRESS
R
A
nDATA
A
LAST DATA
NA
P
White block: host to XRA120x
Grey block: XRA120x to host
228DSR00
4
Rev. 1.0.2
2
XRA1200 / XRA1200P
8-bit I C / SMBUS GPIO Expander
1.1.1
I2C-bus Addressing
There could be many devices on the I2C-bus. To distinguish itself from the other devices on the I2C-bus, the
XRA1200/1200P has up to 32 I2C slave addresses using the A2-A0 address lines. Table 1 below shows the
different addresses that can be selected.
TABLE 1: I2C ADDRESS MAP
228DSR00
A2
A1
A0
I2C ADDRESS
GND
SCL
GND
0x20 (0010 000X)
GND
SCL
VCC
0x22 (0010 001X)
GND
SDA
GND
0x24 (0010 010X)
GND
SDA
VCC
0x26 (0010 011X)
VCC
SCL
GND
0x28 (0010 100X)
VCC
SCL
VCC
0x2A (0010 101X)
VCC
SDA
GND
0x2C (0010 110X)
VCC
SDA
VCC
0x2E (0010 111X)
GND
SCL
SCL
0x30 (0011 000X)
GND
SCL
SDA
0x32 (0011 001X)
GND
SDA
SCL
0x34 (0011 010X)
GND
SDA
SDA
0x36 (0011 011X)
VCC
SCL
SCL
0x38 (0011 100X)
VCC
SCL
SDA
0x3A (0011 101X)
VCC
SDA
SCL
0x3C (0011 110X)
VCC
SDA
SDA
0x3E (0011 111X)
GND
GND
GND
0x40 (0100 000X)
GND
GND
VCC
0x42 (0100 001X)
GND
VCC
GND
0x44 (0100 010X)
GND
VCC
VCC
0x46 (0100 011X)
VCC
GND
GND
0x48 (0100 100X)
VCC
GND
VCC
0x4A (0100 101X)
VCC
VCC
GND
0x4C (0100 110X)
VCC
VCC
VCC
0x4E (0100 111X)
GND
GND
SCL
0x50 (0101 000X)
GND
GND
SDA
0x52 (0101 001X)
GND
VCC
SCL
0x54 (0101 010X)
GND
VCC
SDA
0x56 (0101 011X)
VCC
GND
SCL
0x58 (0101 100X)
VCC
GND
SDA
0x5A (0101 101X)
VCC
VCC
SCL
0x5C (0101 110X)
VCC
VCC
SDA
0x5E (0101 111X)
5
Rev. 1.0.2
XRA1200 / XRA1200P
8-bit
I2C
/ SMBUS GPIO Expander
I2C Read and Write
1.1.2
A read or write transaction is determined by bit-0 of the slave address. If bit-0 is ’0’, then it is a write
transaction. If bit-0 is ’1’, then it is a read transaction.
I2C Command Byte
1.1.3
An I2C command byte is sent by the I2C master following the slave address. The command byte indicates the
address offset of the register that will be accessed. Table 2 below lists the command bytes for each register.
TABLE 2: I2C COMMAND BYTE (REGISTER ADDRESS)
COMMAND BYTE
REGISTER NAME DESCRIPTION
READ/WRITE
DEFAULT VALUES
0x00
GSR - GPIO State
Read-Only
0xXX
0x01
OCR - Output Control
Read/Write
0xFF
0x02
PIR - Input Polarity Inversion
Read/Write
0x00
0x03
GCR - GPIO Configuration
Read/Write
0xFF
0x04
PUR - Input Internal Pull-up Resistor Enable/Disable
Read/Write
0x00 (XRA1200)
0xFF (XRA1200P)
0x05
IER - Input Interrupt Enable
Read/Write
0x00
0x06
TSCR - Output Three-State Control
Read/Write
0x00
0x07
ISR - Input Interrupt Status
Read
0x00
0x08
REIR - Input Rising Edge Interrupt Enable
Read/Write
0x00
0x09
FEIR - Input Falling Edge Interrupt Enable
Read/Write
0x00
0x0A
IFR - Input Filter Enable/Disable
Read/Write
0xFF
228DSR00
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Rev. 1.0.2
2
XRA1200 / XRA1200P
8-bit I C / SMBUS GPIO Expander
1.2
Interrupts
The table below summarizes the interrupt behavior of the different register settings for the XRA1200/1200P.
TABLE 3: INTERRUPT GENERATION AND CLEARING
GCR IER REIR FEIR IFR
BIT BIT BIT
BIT
BIT
1
1
0
1
X
0
X
0
1
1
1
0
1
1
0
1
INTERRUPT GENERATED BY:
X
No interrupts enabled (default)
N/A
0
A rising or falling edge on the input
1
A rising or falling edge on the input and
remains in the new state for more than
1075ns
Reading the GSR register or if the input
changes back to its previous state (state of
input during last read to GSR)
0
A rising edge on the input
1
A rising edge on the input and remains high
for more than 1075ns
0
A falling edge on the input
1
A falling edge on the input and remains low
for more than 1075ns
0
A rising or falling edge on the input
Reading the GSR register
Reading the GSR register
1
1
1
1
1
A rising or falling edge on the input and
remains in the new state for more than
1075ns
0
x
x
x
x
No interrupts in output mode
228DSR00
INTERRUPT CLEARED BY:
7
Reading the GSR register
N/A
Rev. 1.0.2
XRA1200 / XRA1200P
8-bit
2.0
2.1
I2C
/ SMBUS GPIO Expander
REGISTER DESCRIPTION
GPIO State Register (GSR) - Read-Only
The status of P7 - P0 can be read via this register. A read will show the current state of these pins (or the
inverted state of these pins if enabled via the PIR Register). Reading this register will clear an input interrupt
(see Table 3 for complete details). Reading this register will also return the last value written to the OCR
register for any pins that are configured as outputs (ie. this is not the same as the state of the actual output pin
since the output pin can be in three-state mode). A write to this register has no effect. The MSB of this register
corresponds with P7 and the LSB of this register corresponds with P0.
2.2
Output Control Register (OCR) - Read/Write
When P7 - P0 are defined as outputs, they can be controlled by writing to this register. Reading this register
will return the last value written to it, however, this value may not be the actual state of the output pin since
these pins can be in three-state mode. The MSB of this register corresponds with P7 and the LSB of this
register corresponds with P0.
2.3
Input Polarity Inversion Register (PIR) - Read/Write
When P7 - P0 are defined as inputs, this register inverts the polarity of the input value read from the Input Port
Register. If the corresponding bit in this register is set to ’1’, the value of this bit in the GSR Register will be the
inverted value of the input pin. If the corresponding bit in this register is set to ’0’, the value of this bit in the
GSR Register will be the actual value of the input pin. The MSB of this register corresponds with P7 and the
LSB of this register corresponds with P0.
2.4
GPIO Configuration Register (GCR) - Read/Write
This register configures the GPIOs as inputs or outputs. After power-up, the GPIOs are inputs. Setting these
bits to ’0’ will enable the GPIOs as outputs. Setting these bits to ’1’ will enable the GPIOs as inputs. The MSB
of this register corresponds with P7 and the LSB of this register corresponds with P0.
2.5
Input Internal Pull-up Enable/Disable Register (PUR) - Read/Write
This register enables/disables the internal pull-up resistors for an input. After power-up, the internal pull-up
resistors are disabled for the XRA1200. Writing a ’1’ to these bits will enable the internal pull-up resistors.
After power-up, the internal pull-up resistors are enabled for the XRA1200P. Writing a ’0’ to these bits will
disable the internal pull-up resistors. The MSB of this register corresponds with P7 and the LSB of this register
corresponds with P0.
2.6
Input Interrupt Enable Register (IER) - Read/Write
This register enables/disables the interrupts for an input. After power-up, the interrupts are disabled. Writing a
’1’ to these bits will enable the interrupt for the corresponding input pins. See Table 3 for complete details of
the interrupt behavior for various register settings. No interrupts are generated for outputs when GCR bit is 0.
The MSB of this register corresponds with P7 and the LSB of this register corresponds with P0.
2.7
Output Three-State Control Register (TSCR) - Read/Write
This register can enable/disable the three-state mode of an output. Writing a ’1’ to these bits will enable the
three-state mode for the corresponding output pins. The MSB of this register corresponds with P7 and the LSB
of this register corresponds with P0.
2.8
Input Interrupt Status Register (ISR) - Read-Only
This register reports the input pins that have generated an interrupt. See Table 3 for complete details of the
interrupt behavior for various register settings. The MSB of this register corresponds with P7 and the LSB of
this register corresponds with P0.
228DSR00
8
Rev. 1.0.2
2
XRA1200 / XRA1200P
8-bit I C / SMBUS GPIO Expander
2.9
Input Rising Edge Interrupt Enable Register (REIR) - Read/Write
Writing a ’1’ to these bits will enable the corresponding input to generate an interrupt on the rising edge. See
Table 3 for complete details of the interrupt behavior for various register settings. The MSB of this register
corresponds with P7 and the LSB of this register corresponds with P0.
2.10
Input Falling Edge Interrupt Enable Register (FEIR) - Read/Write
Writing a ’1’ to these bits will enable the corresponding input to generate an interrupt on the falling edge.
Writing a ’1’ to these bits will make that input generate an interrupt on the rising edge only. See Table 3 for
complete details of the interrupt behavior for various register settings. The MSB of this register corresponds
with P7 and the LSB of this register corresponds with P0.
2.11
Input Filter Enable Register (IFR) - Read/Write
By default, the input filters are enabled (IFR = 0xFF). When the input filters are enabled, any pulse that is
greater than 1075ns will generate an interrupt (if enabled). Pulses that are less than 225ns will be filtered and
will not generate an interrupt. Pulses in between this range may or may not generate an interrupt. Writing a ’0’
to these bits will disable the input filter for the corresponding inputs. With the input filters disabled, any change
on the inputs will generate an interrupt (if enabled). See Table 3 for complete details of the interrupt behavior
for various register settings. The MSB of this register corresponds with P7 and the LSB of this register
corresponds with P0.
228DSR00
9
Rev. 1.0.2
XRA1200 / XRA1200P
8-bit
I2C
/ SMBUS GPIO Expander
ABSOLUTE MAXIMUM RATINGS
Power supply voltage
3.6 Volts
Supply current
160 mA
Ground current
200 mA
External current limit of each GPIO
25 mA
Total current limit for GPIO[7:0]
100 mA
Total supply current sourced by all GPIOs
160 mA
Operating Temperature
-40o to +85oC
Storage Temperature
-65o to +150oC
Power Dissipation
200 mW
TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%)
Thermal Resistance (16-QFN)
theta-ja = 40oC/W, theta-jc = 26oC/W
Thermal Resistance (16-TSSOP)
theta-ja = 105oC/W, theta-jc = 20oC/W
TSSOP-16 versions available, QFN-16 versions obsolete
228DSR00
10
Rev. 1.0.2
2
XRA1200 / XRA1200P
8-bit I C / SMBUS GPIO Expander
ELECTRICAL CHARACTERISTICS
DC ELECTRICAL CHARACTERISTICS
UNLESS OTHERWISE NOTED: TA = -40O TO +85OC, VCC IS 1.65V TO 3.6V
LIMITS
SYMBOL
LIMITS
1.8V 10%
PARAMETER
2.5V 10%
LIMITS
3.3V 10%
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
CONDITIONS
VIL
Input Low Voltage
-0.3
0.3VCC
-0.3
0.3VCC
-0.3
0.3VCC
V
Note 1
VIL
Input Low Voltage
-0.3
0.2
-0.3
0.5
-0.3
0.8
V
Note 2
VIH
Input High Voltage
1.3
VCC
1.8
VCC
2.3
VCC
V
Note 1
VIH
Input High Voltage
1.4
5.5
1.8
5.5
2.0
5.5
V
Note 2
VOL
Output Low Voltage
0.4
V
V
V
IOL = 3 mA
0.4
0.4
IOL = 3 mA
IOL = 3 mA
Note 3
Output Low Voltage
VOL
0.5
0.5
0.5
V
IOL = 8 mA
Note 4
Output Low Voltage
VOL
0.4
0.4
0.4
V
V
V
IOL = 6 mA
IOL = 4 mA
IOL = 1.5 mA
Note 5
Output High Voltage
VOH
2.6
V
V
V
1.8
1.2
IOH = -8 mA
IOH = -8 mA
IOH = -8 mA
Note 4
IIL
Input Low Leakage Current
±10
±10
±10
uA
IIH
Input High Leakage Current
±10
±10
±10
uA
ICC
Power Supply Current
50
100
200
uA
Test 1
ICC
Power Supply Current
150
250
500
uA
Test 2
ICCS
Standby Current
1
2
5
uA
Test 3
CIN
Input Pin Capacitance
5
5
5
pF
140
k
RGPIO
GPIO pull-up resistance
60
140
60
140
60
100k 40%
NOTES:
1.
For I2C input signals (SDA, SCL);
2.
For GPIOs, A0, A1 and A2 signals;
3.
For I2C output signal SDA;
4.
For GPIOs;
5.
For IRQ# signal;
Test 1: SCL frequency is 400 KHz with internal pull-ups disabled. All GPIOs are configured as inputs. All inputs are steady
at VCC or GND. Outputs are floating or in the tri-state mode.
228DSR00
11
Rev. 1.0.2
XRA1200 / XRA1200P
8-bit
I2C
/ SMBUS GPIO Expander
Test 2: SCL frequency is 400 KHz with internal pull-ups enabled. All GPIOs are configured as inputs. All inputs are steady
at VCC or GND. Outputs are floating or in the tri-state mode.
Test 3: All inputs are steady at VCC or GND to minimize standby current. If internal pull-up is enabled, input voltage level
should be the same as VCC. All GPIOs are configured as inputs. SCL and SDA are at VCC. Outputs are left floating or in
tri-state mode.
AC ELECTRICAL CHARACTERISTICS
Unless otherwise noted: TA=-40o to +85oC, Vcc=1.65V - 3.6V
SYMBOL
STANDARD MODE
FAST MODE
I2C-BUS
I2C-BUS
MIN
MAX
PARAMETER
MIN
fSCL
Operating frequency
TBUF
Bus free time between STOP and START
4.7
1.3
s
THD;STA
START condition hold time
4.0
0.6
s
TSU;STA
START condition setup time
4.7
0.6
s
THD;DAT
Data hold time
0
0
ns
TVD;ACK
Data valid acknowledge
0.6
0.6
s
TVD;DAT
SCL LOW to data out valid
0.6
0.6
ns
TSU;DAT
Data setup time
250
150
ns
TLOW
Clock LOW period
4.7
1.3
s
THIGH
Clock HIGH period
4.0
0.6
s
TF
Clock/data fall time
300
300
ns
TR
Clock/data rise time
1000
300
ns
TSP
Pulse width of spikes tolerance
TD1
I2C-bus GPIO output valid
0.2
0.2
s
TD4
I2C input pin interrupt valid
4
4
s
TD5
I2C input pin interrupt clear
4
4
s
TD15
SCL delay after reset
228DSR00
0
MAX
100
50
3
12
0
400
UNIT
50
3
kHz
ns
s
Rev. 1.0.2
XRA1200 / XRA1200P
2
8-bit I C / SMBUS GPIO Expander
FIGURE 6. I2C-BUS TIMING DIAGRAM
START
condition
(S)
Protocol
Bit 7
MSB
(A7)
T SU;STA
T LOW
Bit 0
LSB
(R/W)
Bit 6
(A6)
T HIGH
Acknowledge
(A)
STOP
condition
(P)
1/F SCL
SCL
TF
TR
T BUF
T SP
SDA
T HD;STA
T SU;DAT
T HD;DAT
T VD;DAT
T VD;ACK
T SU;STO
FIGURE 7. WRITE TO OUTPUT
SDA
SLAVE
ADDRESS
W
A
COMMAND
BYTE
A
DATA
A
T D1
GPIOn
FIGURE 8. GPIO PIN INTERRUPT
A C K from slave
SDA
SLAVE
ADDRESS
W
A
COMMAND
BYTE
A
A C K from slave
S
S LA V E
ADDRESS
R
A
A C K from m aste r
DATA
A
P
IN T #
TD4
TD5
Px
228DSR00
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Rev. 1.0.2
XRA1200 / XRA1200P
8-bit
I2C
/ SMBUS GPIO Expander
MECHANICAL DIMENSIONS (16 PIN QFN - 3 X 3 X 0.9 mm, 0.50 PITCH)
QFN-16 VERSION OBSOLETE
16X L
TOP VIEW
16X b
BOTTOM VIEW
SIDE VIEW
TERMINAL DETAILS
Drawing No.: POD- 00000138
Revision: A
Note: The control dimension is in millimeter.
228DSR00
14
Rev. 1.0.2
2
XRA1200 / XRA1200P
8-bit I C / SMBUS GPIO Expander
RECOMMENDED LAND PATTERN AND STENCIL (16 PIN QFN - 3 X 3 X 0.9 mm, 0.50 PITCH)
QFN-16 VERSION OBSOLETE
TYPICAL RECOMMENDED LAND PATTERN
TYPICAL RECOMMENDED STENCIL
Drawing No.: POD- 00000138
Revision: A
Note: The control dimension is in millimeter.
228DSR00
15
Rev. 1.0.2
XRA1200 / XRA1200P
8-bit
I2C
/ SMBUS GPIO Expander
MECHANICAL DIMENSIONS (16 PIN TSSOP - 4.4 mm)
Top View
Front View
Side View
POD-00000117
Drawing No:
Revision:
A
Note: The control dimension is in millimeter.
228DSR00
16
Rev. 1.0.2
XRA1200 / XRA1200P
2
8-bit I C / SMBUS GPIO Expander
REVISION HISTORY
DATE
REVISION
DESCRIPTION
September 2011
1.0.0
Final Datasheet.
August 2020
1.0.1
Update to MaxLinear Logo. Update Ordering Information.
February 2, 2022
1.0.2
Updated:
In the "TSSOP-16 versions available, QFN-16 versions obsolete" table,
GPIOs parameter description.
"GPIO Configuration Register (GCR) - Read/Write" section.
"Input Internal Pull-up Enable/Disable Register (PUR) - Read/Write"
section.
"Input Interrupt Enable Register (IER) - Read/Write" section.
"Mechanical Dimensions (16 pin QFN)" figure.
"Recommended and Pattern and Stencil (16 pin QFN)" figure.
"Mechanical Dimensions (16 pin TSSOP)" figure.
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