XRA1404
8-Bit SPI GPIO Expander with Integrated Level Shifters
February 4, 2022
Rev. 1.0.1
GENERAL DESCRIPTION
FEATURES
The XRA1404 is an 8-bit GPIO expander with an SPI
interface. After power-up, the XRA1404 has internal
100K ohm pull-up resistors on each I/O pin that can
be individually enabled.
1.65V to 3.6V operating voltage
Integrated level shifters
8 General Purpose I/Os (GPIOs)
5V tolerant inputs
Maximum stand-by current of 1uA at +1.8V
SPI bus interface
In addition, the GPIOs on the XRA1404 can
individually be controlled and configured. As outputs,
the GPIOs can be outputs that are high, low or in
three-state mode. The three-state mode feature is
useful for applications where the power is removed
from the remote devices, but they may still be
connected to the GPIO expander.
■
Individually programmable inputs
As inputs, the internal pull-up resistors can be
enabled or disabled and the input polarity can be
inverted. The interrupt can be programmed for
different behaviors.
The interrupts can be
programmed to generate an interrupt on the rising
edge, falling edge or on both edges. The interrupt
can be cleared if the input changes back to its original
state or by reading the current state of the inputs.
■
■
■
■
■
Internal pull-up resistors
Polarity inversion
Individual interrupt enable
Rising edge and/or Falling edge interrupt
Input filter
Individually programmable outputs
The XRA1404 is available in 16-pin QFN and 16-pin
TSSOP packages.
QFN-16 version available,
obsolete
SPI Clock Frequency up to 26MHz
■
■
Output Level Control
Output Three-State Control
Open-drain active low interrupt output
3kV HBM ESD protection per JESD22-A114F
200mA latch-up performance per JESD78B
TSSOP-16 version
APPLICATIONS
Personal Digital Assistants (PDA)
Cellular Phones/Data Devices
Battery-Operated Devices
Global Positioning System (GPS)
Bluetooth
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XRA1404
8-Bit SPI GPIO Expander with Integrated Level Shifters
FIGURE 1. XRA1404 BLOCK DIAGRAM
VCC
(1.65V – 3.6V)
VCCP
(1.65V – 3.6V)
CS#
P0
P1
P2
P3
P4
P5
P6
P7
SCL
SI
GPIO
Control
Registers
SPI Bus
Interface
SO
Integrated
Level
Shifters
GPIOs
IRQ#
GND
ORDERING INFORMATION
PART NUMBER
NUMBER OF
GPIOS
OPERATING TEMPERATURE
RANGE
PACKAGE
PACKAGE METHOD
LEAD FREE
XRA1404IL16TR-F
8
-40°C to +85°C
QFN-16
Tape and Reel
Yes
NOTE: For more information about part numbers, as well as the most up-to-date ordering information and additional
information on environmental rating, go to www.maxlinear.com/XRA1404.
SI
1
P0
2
SO
VCCP
VCC 1
16 VCCP
16 15 14 13
CS# 2
15 SO
12 SCL
P1
XRA1404 11 IRQ#
16-Pin QFN 10 P7
3
P2
4
8
14 SCL
SI 3
P0 4
P1 5
9 P6
13 IRQ#
12 P7
11 P6
P3 7
10 P5
GND 8
2
XRA1404
16-Pin TSSOP
6
P2
P5
P4
6 7
GND
5
P3
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VCC
CS#
FIGURE 2. PIN OUT ASSIGNMENTS - XRA1404 QFN-16 VERSION AVAILABLE, TSSOP-16 VERSION OBSOLETE
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P4
Rev. 1.0.1
XRA1404
8-Bit SPI GPIO Expander with Integrated Level Shifters
PIN DESCRIPTIONS
Pin Description QFN-16 version available, TSSOP-16 version obsolete
NAME
QFN-16 TSSOP-16
TYPE
PIN#
PIN#
DESCRIPTION
SPI INTERFACE
SO
13
15
O
SPI serial data output.
SCL
12
14
I
SPI serial input clock.
IRQ#
11
13
OD
CS#
16
2
I
SPI bus chip select.
SI
1
3
I
SPI serial data input.
2
3
4
5
7
8
9
10
4
5
6
7
9
10
11
12
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
General purpose I/Os P0-P7. All GPIOs are configured as inputs upon
power-up.
Interrupt output (open-drain, active LOW).
GPIOs
P0
P1
P2
P3
P4
P5
P6
P7
ANCILLARY SIGNALS
VCCP
14
16
Pwr
1.65V to 3.6V VCC supply voltage for GPIOs.
VCC
15
1
Pwr
1.65V to 3.6V VCC supply voltage for SPI bus interface.
GND
6
8
Pwr
Power supply common, ground.
GND
Center
Pad
-
Pwr
The exposed pad at the bottom surface of the package is designed for thermal
performance. Use of a center pad on the PCB is strongly recommended for thermal conductivity as well as to provide mechanical stability of the package on the
PCB. The center pad is recommended to be solder masked defined with opening size less than or equal to the exposed thermal pad on the package bottom to
prevent solder bridging to the outer leads of the device. Thermal vias must be
connected to GND plane as the thermal pad of package is at GND potential.
Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.
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8-Bit SPI GPIO Expander with Integrated Level Shifters
1.0
1.1
FUNCTIONAL DESCRIPTIONS
SPI bus Interface
The SPI interface consists of four lines: serial clock (SCL), chip select (CS#), slave output (SO) and slave input
(SI). The serial clock, slave output and slave input can be as fast as 26 MHz. To access the device in the SPI
mode, the CS# signal is asserted by the SPI master, then the SPI master starts toggling the SCL signal with
the appropriate transaction information. The first bit sent by the SPI master includes whether it is a read or
write transaction and the register being accessed. See Table 1 below.
TABLE 1: SPI COMMAND BYTE FORMAT
BIT
FUNCTION
7
Read/Write#
Logic 1 = Read
Logic 0 = Write
6:1
Command Byte
0
Reserved
FIGURE 3. SPI WRITE
SCL
SI
0
0
0
A3
A2
A1
A0
X
1
0
0
A3
A2
A1
A0
X
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
FIGURE 4. SPI READ
SC L
SI
SO
After the last read or write transaction, the SPI master will set the SCL signal back to its idle state (LOW).
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8-Bit SPI GPIO Expander with Integrated Level Shifters
1.1.1
SPI Command Byte
An SPI command byte is sent by the SPI master following the slave address. The command byte indicates the
address offset of the register that will be accessed. Table 2 below lists the command bytes for each register.
TABLE 2: COMMAND BYTE (REGISTER ADDRESS)
COMMAND BYTE
1.2
REGISTER NAME DESCRIPTION
READ/WRITE
DEFAULT VALUES
0x00
GSR - GPIO State
Read-Only
0xXX
0x01
OCR - Output Control
Read/Write
0xFF
0x02
PIR - Input Polarity Inversion
Read/Write
0x00
0x03
GCR - GPIO Configuration
Read/Write
0xFF
0x04
PUR - Input Internal Pull-up Resistor Enable/Disable
Read/Write
0x00
0x05
IER - Input Interrupt Enable
Read/Write
0x00
0x06
TSCR - Output Three-State Control
Read/Write
0x00
0x07
ISR - Input Interrupt Status
Read
0x00
0x08
REIR - Input Rising Edge Interrupt Enable
Read/Write
0x00
0x09
FEIR - Input Falling Edge Interrupt Enable
Read/Write
0x00
0x0A
IFR - Input Filter Enable/Disable
Read/Write
0xFF
Interrupts
The table below summarizes the interrupt behavior of the different register settings for the XRA1404.
TABLE 3: INTERRUPT GENERATION AND CLEARING
GCR IER REIR FEIR IFR
BIT BIT BIT BIT BIT
1
1
1
1
0
1
1
1
X
0
1
0
X
0
0
1
INTERRUPT GENERATED BY:
X
No interrupts enabled (default)
N/A
0
A rising or falling edge on the input
1
A rising or falling edge on the input and
remains in the new state for more than
1075ns
Reading the GSR register or if the input
changes back to its previous state (state of
input during last read to GSR)
0
A rising edge on the input
1
A rising edge on the input and remains high
for more than 1075ns
0
A falling edge on the input
1
A falling edge on the input and remains low
for more than 1075ns
0
A rising or falling edge on the input
Reading the GSR register
Reading the GSR register
1
1
1
1
1
A rising or falling edge on the input and
remains in the new state for more than
1075ns
0
x
x
x
x
No interrupts in output mode
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INTERRUPT CLEARED BY:
5
Reading the GSR register
N/A
Rev. 1.0.1
XRA1404
8-Bit SPI GPIO Expander with Integrated Level Shifters
2.0
2.1
REGISTER DESCRIPTION
GPIO State Register (GSR) - Read-Only
The status of P7 - P0 can be read via this register. A read will show the current state of these pins (or the
inverted state of these pins if enabled via the PIR Register). Reading this register will clear an input interrupt
(see Table 3 for complete details). Reading this register will also return the last value written to the OCR
register for any pins that are configured as outputs (ie. this is not the same as the state of the actual output pin
since the output pin can be in three-state mode). A write to this register has no effect. The MSB of this register
corresponds with P7 and the LSB of this register corresponds with P0.
2.2
Output Control Register (OCR) - Read/Write
When P7 - P0 are defined as outputs, they can be controlled by writing to this register. Reading this register
will return the last value written to it, however, this value may not be the actual state of the output pin since
these pins can be in three-state mode. The MSB of this register corresponds with P7 and the LSB of this
register corresponds with P0.
2.3
Input Polarity Inversion Register (PIR) - Read/Write
When P7 - P0 are defined as inputs, this register inverts the polarity of the input value read from the Input Port
Register. If the corresponding bit in this register is set to ’1’, the value of this bit in the GSR Register will be the
inverted value of the input pin. If the corresponding bit in this register is set to ’0’, the value of this bit in the
GSR Register will be the actual value of the input pin. The MSB of this register corresponds with P7 and the
LSB of this register corresponds with P0.
2.4
GPIO Configuration Register (GCR) - Read/Write
This register configures the GPIOs as inputs or outputs. Upon power-up, the GPIOs are configured as inputs
by default. Setting these bits to ’0’ will enable the GPIOs as outputs. Setting these bits to ’1’ will enable the
GPIOs as inputs. The MSB of this register corresponds with P7 and the LSB of this register corresponds with
P0.
2.5
Input Internal Pull-up Enable/Disable Register (PUR) - Read/Write
This register enables/disables the internal pull-up resistors for an input. Upon power-up, the internal pull-up
resistors are disabled by default. Writing a ’1’ to these bits will enable the internal pull-up resistors. Writing a
’0’ to these bits will disable the internal pull-up resistors. The MSB of this register corresponds with P7 and the
LSB of this register corresponds with P0.
2.6
Input Interrupt Enable Register (IER) - Read/Write
This register enables/disables the interrupts for an input. Upon power-up, the interrupts are disabled by
default. Writing a ’1’ to these bits will enable the interrupt for the corresponding input pins. See Table 3 for
complete details of the interrupt behavior for various register settings. No interrupts are generated for outputs
when GCR bit is 0. The MSB of this register corresponds with P7 and the LSB of this register corresponds with
P0.
2.7
Output Three-State Control Register (TSCR) - Read/Write
This register can enable/disable the three-state mode of an output. Writing a ’1’ to these bits will enable the
three-state mode for the corresponding output pins. The MSB of this register corresponds with P7 and the LSB
of this register corresponds with P0.
2.8
Input Interrupt Status Register (ISR) - Read-Only
This register reports the input pins that have generated an interrupt. See Table 3 for complete details of the
interrupt behavior for various register settings. The MSB of this register corresponds with P7 and the LSB of
this register corresponds with P0.
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8-Bit SPI GPIO Expander with Integrated Level Shifters
2.9
Input Rising Edge Interrupt Enable Register (REIR) - Read/Write
Writing a ’1’ to these bits will enable the corresponding input to generate an interrupt on the rising edge. See
Table 3 for complete details of the interrupt behavior for various register settings. The MSB of this register
corresponds with P7 and the LSB of this register corresponds with P0.
2.10
Input Falling Edge Interrupt Enable Register (FEIR) - Read/Write
Writing a ’1’ to these bits will enable the corresponding input to generate an interrupt on the falling edge.
Writing a ’1’ to these bits will make that input generate an interrupt on the rising edge only. See Table 3 for
complete details of the interrupt behavior for various register settings. The MSB of this register corresponds
with P7 and the LSB of this register corresponds with P0.
2.11
Input Filter Enable Register (IFR) - Read/Write
By default, the input filters are enabled (IFR = 0xFF). When the input filters are enabled, any pulse that is
greater than 1075ns will generate an interrupt (if enabled). Pulses that are less than 225ns will be filtered and
will not generate an interrupt. Pulses in between this range may or may not generate an interrupt. Writing a ’0’
to these bits will disable the input filter for the corresponding inputs. With the input filters disabled, any change
on the inputs will generate an interrupt (if enabled). See Table 3 for complete details of the interrupt behavior
for various register settings. The MSB of this register corresponds with P7 and the LSB of this register
corresponds with P0.
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8-Bit SPI GPIO Expander with Integrated Level Shifters
ABSOLUTE MAXIMUM RATINGS
Power supply voltage
3.6 Volts
Supply current
160 mA
Ground current
200 mA
External current limit of each GPIO
25 mA
Total current limit for GPIO[7:0]
100 mA
Total supply current sourced by all GPIOs
160 mA
Operating Temperature
-40o to +85oC
Storage Temperature
-65o to +150oC
Power Dissipation
200 mW
TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%)
Thermal Resistance (16-QFN)
theta-ja = 40oC/W, theta-jc = 26oC/W
Thermal Resistance (16-TSSOP)
theta-ja = 105oC/W, theta-jc = 20oC/W
QFN-16 version available, TSSOP-16 version obsolete
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8-Bit SPI GPIO Expander with Integrated Level Shifters
ELECTRICAL CHARACTERISTICS
DC ELECTRICAL CHARACTERISTICS
UNLESS OTHERWISE NOTED: TA = -40O TO +85OC, VCC IS 1.65V TO 3.6V
LIMITS
SYMBOL
PARAMETER
LIMITS
1.8V 10%
2.5V 10%
LIMITS
3.3V 10%
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
CONDITIONS
VIL
Input Low Voltage
-0.3
0.2
-0.3
0.5
-0.3
0.8
V
Note 1
VIH
Input High Voltage
1.4
5.5
1.8
5.5
2.0
5.5
V
Note 1
VOL
Output Low Voltage
0.4
V
V
V
IOL = 6 mA
0.4
0.4
IOL = 4 mA
IOL = 1.5 mA
Note 2 &
Note 4
VOL
Output Low Voltage
0.5
0.5
0.5
V
IOL = 8 mA
Note 3
VOH
Output High Voltage
2.0
V
V
V
1.8
1.4
IOL = -4 mA
IOL = -2 mA
IOL = -0.2 mA
Note 2
VOH
Output High Voltage
2.6
V
V
V
1.8
1.2
IOH = -8 mA
IOH = -8 mA
IOH = -8 mA
Note 3
IIL
Input Low Leakage Current
±10
±10
±10
uA
IIH
Input High Leakage Current
±10
±10
±10
uA
CIN
Input Pin Capacitance
5
5
5
pF
ICC
Power Supply Current
0.5
1.0
2.0
mA
Test 1
ICC
Power Supply Current
0.6
1.2
2.4
mA
Test 2
ICCS
Standby Current
1
2
5
uA
Test 3
140
k
100k 40%
RGPIO
GPIO pull-up resistance
60
140
60
140
60
NOTE: The Vcc comes from VCCP pin for the GPIOs and the VCC pin for the other signals;
NOTES:
1. For SPI input signals (SI, SCL) & GPIOs, A0, A1 and A2 signals;
2. For SPI output signal SO;
3. For GPIOs;
4. For IRQ# signal;
Test 1: SCL frequency is 10 MHz with internal pull-ups disabled. All GPIOs are configured as inputs. All inputs are steady at
VCC or GND. Outputs are floating or in the tri-state mode.
Test 2: SCL frequency is 10 MHz with internal pull-ups enabled. All GPIOs are configured as inputs. All inputs are steady at
VCC or GND. Outputs are floating or in the tri-state mode.
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8-Bit SPI GPIO Expander with Integrated Level Shifters
Test 3: All inputs are steady at VCC or GND to minimize standby current. If internal pull-up is enabled, input voltage level
should be the same as VCC. SCL and SI are at GND. CS# is at VCC. All GPIOs are configured as inputs. Outputs are left
floating or in tri-state mode.
AC ELECTRICAL CHARACTERISTICS - SPI-BUS TIMING SPECIFICATIONS
Unless otherwise noted: TA=-40o to +85oC, Vcc=1.65V - 3.6V
LIMITS
SYMBOL
LIMITS
1.8V 10%
PARAMETER
MIN
TYP
MAX
2.5V 10%
MIN
TYP
3.3V 10%
MIN
TYP
TCSS
CS# to SCL setup time
20
20
20
ns
TCSH
CS# to SCL hold time
20
20
20
ns
TDO
SCL fall to SO valid time
TDS
SI to SCL setup time
20
20
20
ns
TDH
SI to SCL hold time
20
20
20
ns
TCP
SCL period
66
38
38
ns
TCH
SCL HIGH time
30
15
15
ns
TCL
SCL LOW time
30
15
15
ns
CS# HIGH pulse width
30
30
30
ns
SPI output data valid time
TD13
SPI input pin interrupt clear
100
26
100
10
10
200
100
10
200
CONDITIONS
MAX
Operating frequency
TD9
26
UNIT
fSCL
TCSW
15
MAX
LIMITS
MHz
ns
CL = 30 pF
TCH + TCL
ns
200
ns
NOTE: The Vcc comes from the VCC pin.
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8-Bit SPI GPIO Expander with Integrated Level Shifters
FIGURE 5. SPI-BUS TIMING
CS#
...
T CSH
T CSS
T CH
T CL
T CSH
T CSW
...
SCLK
T DH
T DS
...
SI
T DO
T TR
...
SO
FIGURE 6. READ INPUT PORT TO CLEAR GPIO INT
CS#
SCL
SI
1
0
0
A3
A2
A1
A0
X
SO
D7
D6
D5
D4
D3
D2
D1
D0
TD 13
INT #
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8-Bit SPI GPIO Expander with Integrated Level Shifters
FIGURE 7. SPI WRITE OUT TO GPIO SWITCH
CS#
SCL
SI
0
0
0
A3
A2
A1
A0
X
D7
D6
D5
D4
D3
D2
D1
D0
TD9
GPIOn
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8-Bit SPI GPIO Expander with Integrated Level Shifters
MECHANICAL DIMENSIONS (16 PIN QFN - 3 X 3 X 0.9 mm)
16X L
TOP VIEW
16X b
BOTTOM VIEW
SIDE VIEW
TERMINAL DETAILS
Drawing No.: POD- 00000138
Revision: A
Note: The control dimension is in millimeter.
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8-Bit SPI GPIO Expander with Integrated Level Shifters
RECOMMENDED LAND PATTERN AND STENCIL (16 PIN QFN - 3 X 3 X 0.9 mm)
TYPICAL RECOMMENDED LAND PATTERN
TYPICAL RECOMMENDED STENCIL
Drawing No.: POD- 00000138
Revision: A
Note: The control dimension is in millimeter.
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8-Bit SPI GPIO Expander with Integrated Level Shifters
MECHANICAL DIMENSIONS (16 PIN TSSOP - 4.4 mm)
16 PIN TSSOP VERSION OBSOLETE
Top View
Front View
Side View
POD-00000117
Drawing No:
Revision:
A
Note: The control dimension is in millimeter.
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8-Bit SPI GPIO Expander with Integrated Level Shifters
REVISION HISTORY
DATE
REVISION
DESCRIPTION
September 2011
1.0.0
Final Datasheet.
February 4, 2022
1.0.1
Updated:
■
■
■
■
■
■
■
In the "Pin Description" table, GPIOs parameter description.
"GPIO Configuration Register (GCR) - Read/Write" section.
"Input Internal Pull-Up Enable/Disable Register (PUR) - Read/Write" section.
"Input Interrupt Enable Register (IER) - Read/Write" section.
"Mechanical Dimensions (16 Pin QFN)" figure.
"Recommended Land Pattern and Stencil (16 Pin QFN)" figure.
"Mechanical Dimensions (16 Pin TSSOP)" figure.
Added:
■ In the "AC Electrical Characteristics - SPI-Bus Timing Specifications" table,
"TD9" parameter and "TYP" columns.
■ "SPI Write out to GPIO Switch" figure.
Removed:
■ In the "Features" section, "Active-low reset input" feature.
■ In the "Ordering Information" table, XRA1404IL16-F, XRA1404IG16-F, and
XRA1404IG16TR-F obsolete part numbers.
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Fax: +1 (760) 444-8598
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may be reproduced into, stored in, or introduced into a retrieval system, or transmitted in any form or by any means (electronic, mechanical, photocopying,
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