XRD9824
14-Bit Linear CIS/CCD Sensor
Signal Processor with Serial Control
May 2000-3
APPLICATIONS
FEATURES
·
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·
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14-Bit Resolution, No Missing Codes
One-channel 6MSPS Pixel Rate
Triple-channel 2MSPS Pixel Rate
6-Bit Programmable Gain Amplifier
8-Bit Programmable Offset Adjustment
CIS or CCD Compatibility
Internal Clamp for CIS or CCD AC Coupled
Configurations
Color and Grayscale Flatbed Scanners
Color and Grayscale Sheetfed Scanners
Multifunction Peripherals
Digital Color Copiers
General Purpose CIS or CCD Imaging
Low Cost Data Acquisition
Simple and Direct Interface to Canon 600 DPI
Sensors
5V Operation
Serial Load Control Registers
Low Power CMOS: 200mW-typ
Low Cost 20-Lead Packages
USB Compliant
GENERAL DESCRIPTION
The XRD9824 is a complete linear CIS or CCD sensor
signal processor on a single monolithic chip. The
XRD9824 includes a high speed 14-bit resolution
ADC, a 6-bit Programmable Gain Amplifier with gain
adjustment of 1 to 10, and 8-bit programmable input
referred offset calibration range of 800mV.
order to use the full range of the ADC. In the CIS
configuration the input can also be AC coupled similar
to the CCD configuration. This enables CIS signals
with large black levels to be internally clamped to a DC
reference equal to the black level. The DC reference
is internally subtracted from the input signal.
In the CCD configuration the input signal is AC
coupled with an external capacitor. An internal clamp
sets the black level. In the CIS configuration, the
clamp switch can be disabled and the CIS output
signal is DC coupled from the CIS sensor to the
XRD9824. The CIS signal is level shifted to VRB in
The CIS configuration can also be used in other
applications that do not require CDS function, such as
low cost data acquisition.
ORDERING INFORMATION
Package Type
20-Lead SOIC
Temperature Range
0°C to +70°C
Part Number
XRD9824ACD
20-Lead SSOP
0°C to +70°C
XRD9824ACU
Rev. 2.00
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
XRD9824
VBG
* CIS REF Circuit
AVDD
Power
Down
CLAMP
RED
GRN
Triple
S/H
&
3-1
* CIS REF Circuit
DVDD
+
MUX
VREF+
VRT
BUFFER
BLU
_
DC Reference
RL14-BIT
ADC
PGA
14
V
DCREF
VDCEXT
DATA
I/O
PORT
8
DB7:0
VRB
INT/EXT_V DCREF
6
G
DGND
CLP
6-BIT GAIN
REGISTERS
DC/AC
R
G
Power
Down
B
8-BIT DAC
AVDD
AGND
AGND
AGND
8
SYNCH
O
CIS/CCD
8-BIT OFFSET
REGISTERS
R
VRT
CIS
CCD
G
B
Note: * For Canon CIS Sensor
Figure 1. Functional Block Diagram
Rev. 2.00
2
CLAMP
TIMING
&
CONTROL LOGIC
ADCCLK
XRD9824
PIN CONFIGURATION
DVDD 1
20 AVDD
DB0
2
19 RED
DB1
3
18 GRN
DB2
4
17 BLU
DB3
5
16 VDCEXT
XRD9824ACD
DB4
6
15 VREF+
DB5/SCLK
7
14 AGND
DB6/SDATA
8
13 SYNCH
DB7/LD
9
12 CLAMP
11 ADCCLK
DGND 10
20-Lead SOIC
PIN DESCRIPTION
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Symbol
DVDD
DB0
DB1
DB2
DB3
DB4
DB5/SCLK
DB6/SDATA
DB7/LD
DGND
ADCCLK
CLAMP
SYNCH
AGND
VREF+
VDCEXT
BLU
GRN
RED
AVDD
Description
Digital VDD (for Output Drivers)
Data Output Bit 0
Data Output Bit 1
Data Output Bit 2
Data Output Bit 3
Data Output Bit 4
Data Output Bit 5 & Data Input SCLK
Data Output Bit 6 & Data Input SDATA
Data Output Bit 7 & LD
Digital Ground (for Output Drivers)
A/D Converter Clock
Clamp and Video Sample Clock
Start of New Line and Serial Data Input Control
Analog Ground
A/D Positive Reference for Decoupling Cap
External DC Reference
Blue Input
Green Input
Red Input
Analog Power Supply
Rev. 2.00
3
XRD9824
ELECTRICAL CHARACTERISTICS
Test Conditions: AVDD=DVDD=5V, ADCCLK=6MHz, 50% Duty Cycle, TA=25°C unless otherwise specified.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Conditions
V
(Note 2)
DVDD < AVDD
Power Supplies
AVDD
Analog Power Supply
3.0
3.3
5.5
DVDD
Digital I/O Power Supply
3.0
3.3
5.5
V
40
55
mA
VDD=5V
50
µA
VDD=5V
IDD
Supply Current
IDDPD
Power Down Power Supply Current
ADC Specifications
RES
Fs
Resolution
14
Bits
Maximum Sampling Rate
12
MSPS
DNL
Differential Non-Linearity
-3.0
±1.5
3.0
LSB
VRT
Top Reference Voltage
3.50
AVDD/1.3
3.90
V
VRB
Bottom Reference Voltage
AVDD/10
V
0.3
0.67AVDD
V
300
600
DVREF
Differential Reference Voltage
(VRT - VRB)
Ladder Resistance
RL
780
Ω
PGA & Offset DAC Specifications
PGARES
PGA Resolution
PGAGMIN
Minimum Gain
0.950
1.0
1.050
V/V
PGAGMAX
Maximum Gain
9.5
10.0
10.50
V/V
PGAGD
VBLACK
DACRES
6
Bits
Gain Adjustment Step Size
Black Level Input Range
Offset DAC Resolution
0.14
-100
V/V
500
8
mV
DC Configuration
Bits
OFFMIN
Minimum Offset Adjustment
-250
-200
-150
OFFMAX
Maximum Offset Adjustment
+500
+600
+700
mV
Mode 111, D5=0
OFFMIN
Minimum Offset Adjustment
-450
-400
-350
mV
Mode 111, D5=1 (Note 1)
OFFMAX
Maximum Offset Adjustment
+350
+400
+450
mV
Mode 111, D5=1
OFF∆
Offset Adjustment Step Size
Note 1:
Note 2:
3.14
mV
Mode 111, D5=0 (Note 1)
mV
The additional ±100 mV of adjustment with respect to the black level input range is needed to compensate
for any additional offset introduced by the XRD9824 Buffer/PGA internally.
It is not recommended to operate the part between 3.6V and 4.4V.
Rev. 2.00
4
XRD9824
ELECTRICAL CHARACTERISTICS (CONT'D)
Test Conditions: AVDD=DVDD=5V, ADCCLK=6MHz, 50% Duty Cycle, TA=25°C unless otherwise specified.
Symbol
Parameter
Min.
Typ.
Max.
Unit
100
Conditions
Buffer Specifications
IIL
CIN
VINPP
Input Leakage Current
Input Capacitance
AC Input Voltage Range
0
AVDD-1.4
nA
pF
V
AC Input Voltage Range
0
DVREF
V
DC Input Voltage Range
-0.1
AVDD-1.4
V
DC Input Voltage Range
VDCEXT-0.1
VDCEXT+
DVREF
V
VDCEXT
Pin 16=Input
External DC Reference
0.3
AVDD/2
V
VDCEXT
Pin 16=Output
Internal DC Reference
1.17
1.34
V
-50
MHz
dB
VIN
VINBW
VINCT
10
Input Bandwidth (Small Signal)
Channel to Channel Crosstalk
10
-60
CIS AC; INT VDCREF
Config Reg
=> XXX010XX
Gain=1 (Note 1)
CCD AC; INT VDCREF
Config Reg
=> XXX011XX
Gain=1 (Note 1)
CIS DC; INT VDCREF
Config Reg
=> XXX000XX
Gain=1 (Note 2)
CIS DC; EXT VDCREF
Config Reg
=> XXX100XX
Gain=1 (Note 3)
VDCEXT+DVREF < AVDD
CIS DC; EXT VDCREF
Config Reg Mode 110
=> XXX100XX
Internal CIS Reference
Circuit
Config Reg Mode 111
=> XXX1XXXX
fin=3MHz
Internal Clamp Specifications
VCLAMP
Clamp Voltage
3.5
RINT
ROFF
Clamp Switch On Resistance
Clamp Switch Off Resistance
10
AGND
VRT
100
50
150
mV
V
Ω
MΩ
CIS (AC) Config
CCD (AC) Config
Note 1: VINPP is the signal swing before the external capacitor tied to the MUX inputs.
Note 2: The -0.1V minimum is specified in order to accommodate black level signals lower than the external DC
reference (clamp) voltage.
Note 3: The VDCEXT-0.1V minimum is specified in order to accommodate black level signals lowerthan the external DC
reference voltage.
Rev. 2.00
5
XRD9824
ELECTRICAL CHARACTERISTICS (CONT'D)
Test Conditions: AVDD=DVDD= 5V, ADCCLK=6MHz, 50% Duty Cycle, TA=25°C unless otherwise specified.
Symbol
Parameter
Min.
Typ.
Max.
Unit
System Specifications (MUX + Buffer + PGA + ADC)
SYSDNL
System DNL
SYSLIN
System Linearity
SYSGE
System Gain Error
IRN
-1.0
Conditions
Note 1
±0.5
+2.3
±6.0
-5.0
LSB
LSB
+5.0
%
Input Referred Noise
1.5
mVrms
Gain=1
Input Referred Noise
0.5
mVrms
Gain=10
System Timing Specifications
tcklw
ADCCLK Low Pulse Width
50
83
ns
tckhw
ADCCLK High Pulse Width
70
83
ns
166
tckpd
ADCCLK Period
120
tsypw
SYNCH Pulse Width
30
ns
trars
Rising ADCCLK to rising
SYNCH
0
tclpw
CLAMP Pulse Width
30
ns
ns
SYNCH must rise equal to
or after ADCCLK, See Figure 18
Note 2
Write Timing Specifications
tsclkw
SCLK Pulse Width
40
ns
tdz
LD Low to SCLK High
20
ns
tds
Input Data Set-up Time
20
ns
tdh
Input Data Hold Time
0
ns
tdl
SCLK High to LD High
50
ns
ADC Digital Output Specifications
tap
Aperture Delay
tdv
Output Data Valid
40
10
ns
tsa
SYNCH to ADCCLK
15
ns
3ch Pixel Md
tlat
Latency
8
cycles
Config 00, 11
tlat
Latency
6
pixels
Config 01, 10
ns
Digital Input Specifications
VIH
Input High Voltage
VIL
Input Low Voltage
AVDD-2.5
V
IIH
High Voltage Input Current
5
µA
IIL
Low Voltage Input Current
5
µA
CIN
Input Capacitance
10
pF
1
V
Note 1:
System performance is specified for typical digital system timing specifications.
Note 2:
The actual minimum ‘tclpw’ is dependent on the external capacitor value, the CIS output impedance.
During ‘clamp’ operation, sufficient time needs to be allowed for the external capacitor to charge up to the
correct operating level. Refer to the description in Theory of Operation, CIS Config.
Rev. 2.00
6
XRD9824
ELECTRICAL CHARACTERISTICS (CONT'D)
Test Conditions: AVDD=DVDD=5V, ADCCLK=6MHz, 50% Duty Cycle, TA=25°C unless otherwise specified.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Conditions
Digital Output Specifications
VOH
DVDD
VOL
DVDD
IOZ
Output High Voltage
80
(%)
IL=1mA
Output Low Voltage
20
(%)
10
µA
IL=-1mA
Output High-Z Leakage Current
COUT
Output Capacitance
SR
Slew Rate (10% to 90% DVDD)
-10
10
2
pF
15
Rev. 2.00
7
ns
CL=10pF, DVDD=3.3V
XRD9824
THEORY OF OPERATION
CIS Configuration (Contact Image Sensor)
The XRD9824 has two configurations for CIS applications. Each configuration is set by the control registers
accessed through the serial port.
Mode 1. DC Coupled
If the CIS does not have leading or trailing black pixels as shown in Figure 2, then DC couple the CIS output to the
XRD9824 input.
Optically Shielded
Pixels
Valid Pixels
Figure 2. Typical Output CIS Mode
Adjust the offset of the CIS (-100 mV to 500 mV) by setting the internal registers of the XRD9824 to set the black
pixel value when the LEDs of the CIS are off. When the LEDs are on, use the XRD9824 Programmable Gain to
maximize the ADCs dynamic range. Figure 3 shows a typical application for a CIS with an offset of -100mV to
500mV.
Rev. 2.00
8
XRD9824
XRD9824
VDD
VRT
C
I
S
RED
N/C
N/C
N/C
M
U
X
RL
VRB
Figure 3. Application with Offset in the Range (-100mv to 500mv)
beyond the offset range of the XRD9824 (see Offset
Control DAC, Pg. 28) set the internal mode registers to
external reference. An external reference voltage
equal to the value of the CIS offset voltage can be
applied to VDCEXT (Figure 4) in order to meet the
dynamic range of the XRD9824. Figure 4 is a diagram
of the XRD9824 in the external reference mode for
CIS, DC coupled applications.
The input is added to VRB before the signal passes
through the ADC. If the CIS output is zero, then the
output of the ADC will be zero code. This enables the
CIS to be referenced to the bottom ladder reference
voltage to use the full range of the ADC.
Some CIS sensors have an output with an offset
voltage of greater than 500mV. If the CIS output is
Rev. 2.00
9
XRD9824
XRD9824
VDD
VRT
C
I
S
RED
N/C
N/C
M
U
RL
X
VDCEXT
DC
REFERENCE
VRB
Figure 4. Application with Offset Greater Than (-100mv to 500mv)
The DC reference voltage applied to VDCEXT does
not have to be accurate. The internal offset DAC
voltage is still used in this mode for fine adjustment.
VDCEXT cannot be used as an input from the CIS. Any
signal applied to VDCEXT will be subtracted from the
output signal of the multiplexer.
Rev. 2.00
10
XRD9824
VCC (5V - 15V)
19
N/C
18
N/C
17
16
0.1uF
15
GRN
BLU
VDCEXT
VREF+
DB7/LD
DB6/SDATA
DB5/SCLK
DB4
DB3
DB2
DB1
DB0
9
8
7
6
5
4
3
2
11
DIGITAL
ADCCLK
12
ASIC
CLAMP
SYNCH
13
14
AVDD
DVDD
AGND
DGND
XRD9824
AGND
1
10
0.01uF
DVDD (3V - 5V)
20
0.1uF
0.01uF
0.1uF
AVDD
0.1uF
1K
C
I
S
4K
AVDD
RED
DGND
Figure 5. Typical Application Circuitry CIS DC Coupled Non-Inverted Mode
Rev. 2.00
11
XRD9824
CIS Mode Timing -- DC Coupled
(CLAMP disabled)
Pixel N-1
Pixel N
Pixel N+1
tap
tap
CIS
tckpd
tckhw
tcklw
ADCCLK
tdv
DB
tdv
N-8
MSB
[5:0]
[11:6]
N-8
LSB
N-7
MSB
N-7
LSB
N-6
MSB
N-6
LSB
N-5
MSB
N-5
LSB
Figure 6. Timing Diagram for Figure 5
ADCCLK
↓
↑
HI
LO
Events
ADC Sample & PGA Start Tracking next Pixel
MSB Data Out
LSB Data Out
ADC Track PGA Output
ADC Hold/Convert
Table 1.
Mode 2. AC Coupled
If the CIS signal has a black reference for the video
signal, an external capacitor CEXT is used. When
CLAMP (clamp) pin is set high an internal switch allows
one side of the external capacitor to be set to ground.
It then is level shifted to correspond to the bottom
ladder reference voltage of the ADC (Figure 7).
Rev. 2.00
12
XRD9824
XRD9824
VDD
VRT
C
I
S
REXT CEXT
RED
N/C
N/C
N/C
M
U
X
RL
CLAMP
VRB
RINT
Figure 7. CIS AC Coupled Application
Therefore, Tc =1/RINTCEXT
This value corresponds to the black reference of the
image sensor. When the CLAMP pin is set back to low,
the ADC samples the video signal with respect to the
black reference. The typical value for the external
capacitor is 100pF. This value should be adjusted
according to the time constant (Tc) needed in a particular application. The CLAMP pin has an internal 150
ohm impedance (RINT) which is in series with the
external capacitor (CEXT).
If the input to the external capacitor has a source
impedance (REXT), then:
Tc=1/(RINT+REXT)CEXT
Rev. 2.00
13
XRD9824
VCC (5V - 15V)
19 RED
DB7/LD
DB6/SDATA
DB5/SCLK
DB4
DB3
DB2
DB1
DB0
100PF
18 GRN
N/C
17 BLU
N/C
16 VDCEXT
15 VREF+
11
DIGITAL
ADCCLK
12
ASIC
CLAMP
SYNCH
0.1uF
0.01uF
0.1uF
20
AVDD
DVDD
14 AGND
DGND
XRD9824
1
10
0.01uF
DVDD (3V - 5V)
AVDD
AGND
13
0.1uF
C
I
S
N/C
9
8
7
6
5
4
3
2
DGND
Figure 8. Typical Application Circuitry CIS AC Coupled Non-Inverted
Rev. 2.00
14
XRD9824
CIS Mode Timing -- AC Coupled
(CLAMP enabled)
Pixel N-1
Pixel N
Pixel N+1
tap
tap
CIS
tckpd
tckhw
tcklw
ADCCLK
tdv
DB
tdv
N-8
MSB
[5:0]
[11:6]
N-8
LSB
N-7
MSB
N-7
LSB
N-6
MSB
tclpw
CLAMP
Figure 9. Timing Diagram for Figure 8
ADCCLK
↓
↑
HI
LO
Events
ADC Sample & PGA Start Track of next Pixel
MSB Data Out
LSB Data Out
ADC Track PGA Output
ADC Hold/Convert
Table 3.
CLAMP
HI
LO
Events
PGA Tracks VCLAMP & CEXT is Charged to
VBLACK - VCLAMP, which is equal to VBLACK
PGA Tracks VINPP
Table 4.
Rev. 2.00
15
N-6
LSB
N-5
MSB
N-5
LSB
XRD9824
Internal CIS Reference Circuit (DB 4 = 1)
The XRD9824 has an internal register reserved for
interfacing to the Canon CIS model number CVA60216K. When this register is selected, the VDCEXT
(Pin 16) becomes an output voltage of 1.24 volts. This
voltage can be directly connected to the VREF (Pin 15)
of the Canon sensor. This reduces the amount of
components needed for biasing the Canon CIS sensor
(the external diodes and resistors typically used in this
application have been included inside the XRD9824 for
this mode of operation). Below is a typical application
circuit using the XRD9824 and the Canon CVA60216K CIS sensor.
VCC (5V)
CANON CIS
SENSOR
DVDD (3V - 5V)
1
2
3
47uF
4
N/C
18
N/C
17
RED
GRN
DB7/LD
DB6/SDATA
DB5/SCLK
DB4
DB3
DB2
DB1
DB0
9
8
7
6
5
4
3
2
6
7
8
9
10K
19
5
10
BLU
VDCEXT
ADCCLK
CLAMP
VREF+
SYNCH
12
NPN
12
MODE
AGND
VCC
VREF
SP
CLK
LED COM
LED BLU
LED GRN
LED RED
FGND
47uF
DGND
13
NPN
10K
15
DIGITAL
ASIC
11
10K
11
16
VOUT
0.1uF
AGND
DVDD (3V - 5V)
AVDD
DGND
AVDD
AGND
DVDD
DGND
1
10
0.01uF
NPN
0.01uF
14
0.1uF
0.1uF
0.01uF
20
100uF
DGND
AGND
XRD9824
DGND
DGND
CVA-60216K
Figure 10. Typical Application Circuitry Internal CIS Reference Circuit Mode
CANON CIS Sensor, Model #CVA=60216k
Rev. 2.00
16
XRD9824
CIS Line-By-Line Rotating Gain and Offset
(Configuration DB1 = 1, DB0 = 1)
through line-by-line so that the gain and offset do not
have to be loaded in between lines. Below is the typical
application circuit and timing for this configuration.
Line-by-line rotating gain and offset minimizes the
amount of write cycles per scan. Pre-loaded values of
gain and offset can be loaded for each color before the
first line is scanned. Each gain and offset is cycled
VCC (5V - 15V)
19
18
C
I
S
17
16
N/C
RED
DB7/LD
DB6/SDATA
DB5/SCLK
DB4
DB3
DB2
DB1
DB0
GRN
BLU
DIGITAL
VDCEXT
ADCCLK
CLAMP
15
9
8
7
6
5
4
3
2
VREF+
SYNCH
ASIC
11
12
13
0.1uF
DVDD (3V - 5V)
AVDD
DVDD
AGND
DGND
1
10
0.01uF
14
AVDD
0.1uF
0.1uF
0.01uF
20
XRD9824
AGND
DGND
Figure 11. Typical Application Circuitry Internal CIS Rotating
Gain and Offset Line-By-Line
Rev. 2.00
17
XRD9824
CIS Rotating Gain and Offset
Line-By-Line (Md 11)
CIS
Red Pixel Line Scan
Grn Pixel Line Scan
Blu Pixel Line Scan
ADCCLK
tsypw
SYNCH
tsa
GAIN/
Red Gain/Offset Cycle
OFFSET
Grn Gain/Offset Cycle
Blu Gain/Offset Cycle
Tri-State (SYNCH = LO)
LD
Reset Internal Mux Color to Red Channel (LD = 110YYYYYY11)
Note: Y = Previous State
Figure 12. Timing Diagram for Figure 11
CCD Configuration (Charge Coupled Device)
Mode 1. AC Coupled
In the CCD configuration of operation, an external
capacitor needs to be chosen according to the equations below. The typical value for the external capacitor is 100pF. This value should be adjusted according
to the time constant (Tc) needed in a particular application. The CLAMP pin has an internal 150 ohm
impedance (RINT) which is in series with the external
capacitor (CEXT).
When CLAMP (clamp) pin is set high an internal switch
allows one side of the external capacitor to be set to
VRT (Figure 13). This value corresponds to the black
reference of the CCD. When the CLAMP pin is set
back to low, the ADC samples the video signal with
respect to the black reference. The difference between
the black reference and the video signal is the actual
pixel value of the video content. Since this value is
referenced to the top ladder reference voltage of the
ADC a zero input signal would yield a full scale output
code. Therefore, the output of the conversion is
inverted (internally) to correspond to zero scale output
code.
Therefore, Tc =1/RINTCEXT
If the input to the external capacitor has a load impedance (REXT), then
Tc=1/(RINT+REXT)CEXT
Rev. 2.00
18
XRD9824
XRD9824
VDD
CLAMP
VRT
AREA
or
LINEAR
CCD
RED
N/C
N/C
N/C
M
U
X
RL
VRB
Figure 13. CCD AC Coupled Application
Area or Linear CCD Applications
pixel values have been sampled, the gain and offset
are adjusted at the beginning of the next line. For
example, if there is a line-to-line variation between the
black reference pixels, the offset is adjusted. The gain
is always adjusted for the highest color intensity.
Figure 13 is a block diagram for applications with Area
or Linear CCDs (The timing for Area CCDs and B/W
CCDs is the same). For Area or Linear CCD applications, a global offset is loaded into the serial port at the
beginning of a line. The gain is set to adjust for the
highest color intensity of the CCD output. Once the
Rev. 2.00
19
XRD9824
VCC (5V - 15V)
19
RED
DB7/LD
DB6/SDATA
DB5/SCLK
DB4
DB3
DB2
DB1
DB0
100PF
N/C
18
N/C
17
N/C
16
GRN
BLU
VDCEXT
ADCCLK
CLAMP
15
VREF+
SYNCH
12
13
DVDD (3V - 5V)
14
AVDD
DVDD
AGND
DGND
1
10
0.01uF
20
0.1uF
0.01uF
AVDD
0.1uF
DIGITAL
ASIC
11
0.1uF
C
C
D
9
8
7
6
5
4
3
2
XRD9824
AGND
DGND
Figure 14. Typical Application Circuitry Single
Channel CCD AC Coupled Inverted Mode
Rev. 2.00
20
XRD9824
AREA, LINEAR or B/W CCD -- AC Coupled
(CLAMP Enabled)
Pixel N-1
Pixel N
Pixel N+1
CCD
Channel N
tckpd
tckhw
tap
tap
tcklw
ADCCLK
tclpw
CLAMP
tdv
DB
[5:0]
tdv
N-8
MSB
[11:6]
N-8
LSB
N-7
MSB
N-7
LSB
N-6
MSB
N-6
LSB
Figure 15. Timing Diagram for Figure 14
Triple Channel CCD Application
input. The gain and offset is automatically rotated to
adjust for each channel input. The MSBs are available
on the output bus on the falling edge of ADCCLK. The
LSBs are available on the rising edge of ADCCLK.
Figure 16, is a block diagram for pixel-by-pixel applications with triple channel CCDs. During the optically
shielded section of a pixel, CLAMP must go high to
store the black reference on each capacitor to the
Rev. 2.00
21
XRD9824
XRD9827
VDD
CLAMP
VRT
RED/GRN/BLU
C
C
M
D
U
N/C
RL
X
VRB
Figure 16. CCD AC Coupled Application
Rev. 2.00
22
XRD9824
VCC (5V - 15V)
19
RED
DB7/LD
DB6/SDATA
DB5/SCLK
DB4
DB3
DB2
DB1
DB0
100PF
18
GRN
100PF
C
C
D
17
9
8
7
6
5
4
3
2
BLU
100PF
16
N/C
VDCEXT
ADCCLK
CLAMP
15
VREF+
SYNCH
14
AVDD
DVDD
AGND
DGND
1
10
0.01uF
0.1uF
0.01uF
0.1uF
13
DVDD (3V - 5V)
20
AGND
ASIC
12
0.1uF
AVDD
DIGITAL
11
XRD9824
DGND
Figure 17. Typical Application Circuitry Triple Channel CCD
AC Coupled Inverted Mode
Rev. 2.00
23
XRD9824
PIXEL-BY-PIXEL 3 CHANNEL CCD -- AC Coupled
(CLAMP Enabled)
RED
N Pixel
N+1 Pixel
N Pixel
N+1 Pixel
GRN
tclp=10ns
tclp=10ns
BLU
N Pixel
N+1 Pixel
tap
ADCCLK
TRACK
RED (N)
CONVERT
RED (N)
CONVERT
GRN (N)
TRACK
GRN (N)
CONVERT
BLU (N)
TRACK
BLU (N)
trars
tdv
tdv
RED (N-6)
MSB
DATA
tdv
RED (N-6)
LSB
tdv
GRN (N-6)
MSB
GRN (N-6)
LSB
tdv
BLU (N-6)
MSB
tsa
tsypw
SYNCH
Figure 18. Timing Diagram for Figure 17
ADCCLK
3rd ↓
All ↓
↑
HI
LO
CLAMP
HI
LO
SYNCH
HI
LO
CONVERT
RED (N+1)
Simultaneous
Sample
CLAMP
CLAMP
TRACK
RED (N+1)
Events
Simultaneous RED/GRN/BLU Sample Every 3rd CLK.
Convert RED, S/H GRN, S/H BLU.
MSB Data Out
LSB Data Out
ADC Track PGA Output
ADC Hold/Convert
Events
Internal Clamp Enabled
Internal RED/GRN/BLU Tracking Enabled
Events
Reset Internal Mux to Red, Output Bus is Tri-stated
Increment Mux Color on Falling Edge of ADCCLK
Table 5.
Rev. 2.00
24
BLU (N-6)
LSB
XRD9824
VRT
S1 S2 S3
From CCD RED
S1, S2 and S3 close when
CLAMP is high and open
when CLAMP is low
S6
Channel
C EXT R
12-Bit ADC
S9 closes at rising edge and opens
at falling edge of ADCCLK
From CCD
S4
VRT - VPIX
S7
GRN Channel
C EXTG
S9
PGA
+
T/H
T/H
From CCD BLU
S5
S8
VRT
Channel
VCDS = PGAG * [VRT - (VRT - VPIX)]
= PGAG * VPIX
C EXT B
T/H
XRD9827
VBLK
CCD
Waveform
VPIX
VBLK - VPIX
CLAMP
S8 Opens, S4,
S5 and S6
close at this
rising edge
ADCCLK
S6 opens, S7
closes at this
rising edge
Track
RED
Convert
RED
S8 Opens, S4,
S5 and S6
close at this
rising edge
S7 opens, S8
closes at this
rising edge
Track
GRN
Convert
GRN
Track
BLU
Figure 19. CDS Timing (Triple Channel)
Mode: 110 00001110
Rev. 2.00
25
Convert
BLU
S4 and S5 open
at this falling
edge
Track
RED
Convert
RED
XRD9824
Mode 2. DC Coupled
PGA GAIN TRANSFER CURVE
GAIN 1 - 10
10
Typical CCDs have outputs with black references.
Therefore, DC Coupled is not recommended for CCD
applications.
9
8
GAIN
7
Offset Control DAC
6
5
4
3
The offset DAC is controlled by 8 bits. The offset range
is 800 mV ranging from -200 mV to +600 mV (when
DB5 is set to 0) and -400 mV to +400 mV (when DB5
is set to 1). Therefore, the resolution of the 8-Bit offset
DAC is 3.14 mV. However, the XRD9824 has +/- 100
mV reserved for internal offsets. Therefore, the effective range for adjusting for CIS offsets or black reference is 600 mV. The offset adjustment is used primarily to correct for the difference between the black level
of the image sensor and the bottom ladder reference
voltage (VRB) of the ADC. By adjusting the black level
to correspond to VRB, the entire range of the ADC can
be used.
2
1
0
10
20
30
40
50
60
CODE
Figure 20. Transfer Curve for the 6-Bit PGA
After the signal is level shifted to correspond with the
bottom ladder reference voltage, the system can be
calibrated such that a white video pixel can represent
the top ladder reference voltage to the ADC. This
allows for a full scale conversion maximizing the resolution of the ADC.
If the offset of the CIS output is greater than 500 mV an
external reference can be applied to VDCEXT. The
external reference can be used to adjust for large
offsets only when the internal mode is configured
through the serial port.
Analog to Digital Converter
The ADC is a 14-bit, 10 MSPS analog-to-digital converter for high speed and high accuracy. The ADC
uses a subranging architecture to maintain low power
consumption at high conversion rates. The output of
the ADC is on 8-bit databus. The 8-bit databus supports 8x6 output data. ADCCLK samples the input on
its falling edge. After the input is sampled, the MSB is
latched to the output drivers. On the rising edge of the
ADCCLK, the LSB is latched to the output drivers. The
output needs to be demultiplexed with external circuitry
or a digital ASIC. There is an 8 clock cycle latency
(Config 00, 11) or 6 pixel count latency (Config 01, 10)
for the analog-to-digital converter.
Since the offset DAC adjustment is done before the
gain stage, it is gain-dependent. For example, if the
gain needs to be changed between lines (red to blue,
etc.), the offset is calibrated before the signal passes
through the PGA.
PGA (Programmable Gain Amplifier) DAC
The gain of the input waveform is controlled by a 6-Bit
PGA. The PGA is used along with the offset DAC for
the purpose of using the entire range of the ADC. The
PGA has a linear gain from 1 to 10. Figure 19 is a plot
of the transfer curve for the PGA gain.
The VRT and VRB reference voltages for the ADC are
generated internally, unless the external VRT is selected. In the external VRT mode, the VRT voltage is set
through the VREF+ pin. This allows the user to select
the dynamic range of the ADC.
Rev. 2.00
26
XRD9824
Serial Load Control Registers
The first three MSBs choose which internal register will
be selected. The remaining 8 LSBs contain the data
needed for programming the internal register for a
particular configuration.
The serial load registers are controlled by a three wire
serial interface through the bi-directional parallel port
to reduce the pin count of this device. When SYNCH
is set to high, the output bus is tri-stated and the serial
interface is activated. DB7/LD, DB5/SCLK and DB6/
SDATA are the three input signals that control this
process. The DB7/LD signal is set low to initiate the
loading of the internal registers.
Power-Up State of the Internal Registers
The control register settings upon initial power-up are
for CIS, DC Coupled configuration (VRT is set to
internal, Input DC Reference=AGND and the input to
the ADC is selected through the RED channel). Gain
is unity and Offset is set to zero. The test modes are
disabled in the power-up state.
There are internal registers that are accessed via an
11-bit data string. Data is shifted in on the rising edge
of SCLK and loaded to the registers on the rising edge
of LD. The data on pin DB6/SDATA is latched
automatically after eleven DB5/SCLKs have been
counted. If eleven clocks are not present on DB5/
SCLK before the DB7/LD signal returns high, no data
will be loaded into the internal registers. If more than
11 clocks are present on DB5/SCLK, the additional
clocks will be ignored. The data corresponding to the
first eleven DB5/SCLKs will be loaded only.
SYNCH
tsclkw
DB7/LD
DB5/SCLK
DB6/SDATA
tdl
tdz
S2
tds tdh
S1
S0
D7
Figure 21. Write Timing
Rev. 2.00
27
D2
D1
D0
XRD9824
Output Bus Format
ADC Output —> DO13(MSB):DO0(LSB)
MSB
LSB
DB7
DO13
DO5
DB6
DO12
DO4
DB5
DO11
DO3
DB4
DO10
DO2
DB3
DO9
DO1
DB2
DO8
DO0
DB1
DO7
X
DB0
DO6
X
Table 9. 8 MSB + 6 LSB Output Bus Format
Note :
These are the control register settings upon initial power-up. The previous register settings are retained
following a logic power-down initiated by the power down bit except the signal configuration. When
de-selecting the power down bit (D7 = 0, Normal), the signal configuration (D5 and D0) has to be
reprogrammed.
Rev. 2.00
28
XRD9824
Control Registers
Function
(Register
S2/S1/S0)
D7
D6
D5
D4
D3
D2
D1
D0
Power-up
State
(Note 1)
Red Gain
(000)
G5
(MSB)
G4
G3
G2
G1
G0
(LSB)
X
X
000000XX
Red Offset
(001)
O7
(MSB)
O6
O5
O4
O3
O2
O1
O0
(LSB)
01000000
Grn Gain
(010)
G5
(MSB)
G4
G3
G2
G1
G0
(LSB)
X
X
000000XX
O7
(MSB)
O6
O5
O4
O3
O2
O1
O0
(LSB)
01000000
G5
(MSB)
G4
G3
G2
G1
G0
(LSB)
X
X
000000XX
O7
(MSB)
O6
O5
O4
O3
O2
O1
O0
(LSB)
01000000
POWER
DOWN
DIGITAL
RESET
VRT
INPUT DC
REFERENCE
(VDCREF)
DC/AC
SIGNAL
POLARITY
SIGNAL
CONFIGURATION
0: NORMAL
0: NO RESET
0: INTERNAL
0: DC
1:RESET
(REGISTERS
ARE RESET TO
POWER-UP
STATES)
1: EXTERNAL
0: NonInverted
(CIS)
1: Inverted
(CCD/CIS)
00: Single-Channel
RED input/gain/offset
1:
POWER
DOWN
0: INTERNAL
(VDCREF=AGND)
1: EXTERNAL
(V DCREF=VDCEXT )
Grn Offset
(011)
Blu Gain
(100)
Blu Offset
(101)
Mode
(110)
1: AC
00000000
01: Single-Channel
RED input
RED/GRN/BLU
gain/offset cycle
pixel-by-pixel
10: Triple-Channel
RED/GRN/BLU
input/gain/offset cycle
pixel-by-pixel
11: Triple-Channel
RED/GRN/BLU
input/gain/offset cycle
line-by-line
Mode
&Test
(111)
TEST5
OUTPUT
DISABLE
OFFSET
DAC
RANGE
INTERNAL CIS
REFERENCE
CIRCUIT
TEST4
TEST3
0:NORMAL
0:OUTPUTS
ENABLED
0:-200mV to
+600mV
0:NORMAL
0: TEST4
DISABLED
0: TEST3
DISABLED
1:NOT USED
1:OUTPUTS
DISABLED
1:-400mV to
+400mV
1:REFERENCE
CIRCUIT
ENABLED
Rev. 2.00
29
1: OUTPUT 1: OUTPUT
OF BUFFER OF PGA
TIED TO
TIED TO
BLU
VDCEXT
TEST2
TEST1
0: TEST2 0:NORMAL
DISABLED
1: INPUT
OF ADC
TIED TO
GRN
1: TEST1
ENABLED
00000000
XRD9824
Rev. 2.00
30
XRD9824
20 LEAD SHRINK SMALL OUTLINE PACKAGE
(5.3 mm SSOP)
Rev. 2.00
D
20
11
E
H
1
10
C
A2
A
Seating
Plane
e
B
α
A1
L
SYMBOL
A
A1
A2
B
C
D
E
e
H
L
α
INCHES
MIN
MAX
0.067
0.079
0.002
0.006
0.065
0.073
0.009
0.015
0.004
0.010
0.272
0.296
0.197
0.221
0.0256 BSC
0.292
0.323
0.022
0.037
0°
8°
MILLIMETERS
MIN
MAX
1.70
2.00
0.05
0.15
1.65
1.85
0.22
0.38
0.09
0.25
6.90
7.50
5.00
5.60
0.65 BSC
7.40
8.20
0.55
0.95
0°
8°
Note: The control dimension is the inch column
Rev. 2.00
31
XRD9824
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to
improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits
described herein, conveys no license under any patent or other right, and makes no representation that the circuits
are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may
vary depending upon a user’s specific application. While the information in this publication has been carefully
checked; no responsibility, however, is assumed for in accuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the failure
or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly
affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation
receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the
user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the
circumstances.
Copyright 2000 EXAR Corporation
Datasheet May 2000
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Rev. 2.00
32
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