XRP7724ILBTR-F

Not Recommended for New Designs (Suggested Alternate: XRP7714) XRP7724 Quad Channel Digital PWM/PFM Programmable Power Management System February 2019 Rev. 1.0.2 GENERAL DESCRIPTION APPLICATIONS • • • • • • • The XRP7724 is a quad channel Digital Pulse Width Modulated (DPWM) Step down (buck) controller. A wide 4.75V to 5.5V and 5.5V to 25V input voltage dual range allows for single supply operation from standard power rails. With integrated FET gate drivers, two LDOs for standby power and a 105kHz to 1.23MHz independent channel to channel programmable constant operating frequency, the XRP7724 reduces overall component count and solution footprint and optimizes conversion efficiencies. A selectable digital Pulse Frequency Mode (DPFM) capable of better than 80% efficiency at light current load and low operating current allow for portable and Energy Star compliant applications. Each XRP7724 output channel is individually programmable as low as 0.6V with a resolution as fine as 2.5mV, and configurable for precise soft start and soft stop sequencing, including delay and ramp control. Servers Base Stations Switches/Routers Broadcast Equipment Industrial Control Systems Automatic Test Equipment Video Surveillance Systems FEATURES • Quad Channel Step-down Controller − Digital PWM 105kHz-1.23MHz Operations − Individual Channel Frequency Selection − Patented digital PFM with Ultrasonic mode − Patented Over Sampling Feedback − Integrated MOSFET Drivers − Programmable 5 coefficient PID control • 4.75V to 25V Input Voltage − 4.75V-5.5V and 5.5V-25V Input Ranges − 0.6V to 5.5V Output voltage The XRP7724 operations are fully controlled via a SMBus-compliant I2C interface allowing for advanced local and/or remote reconfiguration, full performance monitoring and reporting as well as fault handling. • SMBus Compliant - I2C Interface − Full Power Monitoring and Reporting • 3 x 15V Capable PSIO + 2 x GPIOs • Full Start/Stop Sequencing Support Built-in independent output over voltage, over temperature, over-current and under voltage lockout protections insure safe operation under abnormal operating conditions. • Built-in Thermal, Over-Current, UVLO and Output Over-Voltage Protections • On Board 5V and 3.3V Standby LDOs • On Board Non-volatile Memory The XRP7724 is offered in a RoHS compliant, “green”/halogen free 44-pin TQFN package. • Supported by PowerArchitect™ Design Tool Version 5 (PA5) 1/31 Rev. 1.0.2 Not Recommended for New Designs (Suggested Alternate: XRP7714) XRP7724 Quad Channel Digital PWM/PFM Programmable Power Management System February 2019 Rev. 1.0.2 TYPICAL APPLICATION DIAGRAM Fig. 1: XRP7724 Application Diagram 2/31 Rev. 1.0.2 Not Recommended for New Designs (Suggested Alternate: XRP7714) XRP7724 Quad Channel Digital PWM/PFM Programmable Power Management System ABSOLUTE MAXIMUM RATINGS OPERATING RATINGS These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. Input Voltage Range VCC ............................... 5.5V to 25V Input Voltage Range VCC = LDO5 ................ 4.75V to 5.5V VOUT1, 2, 3, 4 ...................................................... 5.5V Junction Temperature Range ....................-40°C to 125°C JEDEC Thermal Resistance θJA ..........................30.2°C/W VCCD, LDO5, LDO3_3, GLx, VOUTx ............. -0.3V to 7.0V ENABLE, 5V_EXT ....................................... -0.3V to 7.0V GPIO0/1, SCL, SDA ............................................... 6.0V PSIOs Inputs, BFB .................................................. 18V DVDD, AVDD ........................................................ 2.0V VCC ...................................................................... 28V LX# ............................................................. -1V to 28V BSTx, GHx .................................................... VLXx + 6V Storage Temperature .............................. -65°C to 150°C Power Dissipation ................................ Internally Limited Lead Temperature (Soldering, 10 sec) ................... 300°C ESD Rating (HBM - Human Body Model) .................... 2kV ELECTRICAL SPECIFICATIONS Specifications with standard type are for an Operating Junction Temperature of TJ = 25°C only; limits applying over the full Operating Junction Temperature range are denoted by a “•”. Minimum and Maximum limits are guaranteed through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise indicated, VCC = 5.5V to 25V, 5V EXT open. Note that in cases where there is a discrepancy in values shown in this section and other sections of the datasheet, the values in the Electrical Specification section shall be deemed correct and supersede the other values. QUIESCENT CURRENT Parameter Min. VCC Supply Current in SHUTDOWN ENABLE Turn On Threshold ENABLE Pin Leakage Current Typ. Max. Units 10 20 µA 0.95 V 10 µA EN=5V µA EN=0V 0.82 -10 Conditions EN = 0V, VCC = 12V VCC = 12V Enable Rising LDO3_3 disabled, all channels disabled VCC Supply Current in STANDBY 440 600 µA GPIOs programmed as inputs VCC=12V,EN = 5V VCC Supply Current 2ch PFM 3.1 mA 2 channels on set at 5V, VOUT forced to 5.1V, no load, non-switching, Ultra-sonic off, VCC=12 V, No I2C activity. VCC Supply Current 4ch PFM 4.0 mA 4 channels on set at 5V, VOUT forced to 5.1V, no load, non-switching, Ultra-sonic off, VCC=12V, No I2C activity. VCC Supply Current ON 18 mA All channels enabled, Fsw=600kHz, gate drivers unloaded, No I2C activity. 3/31 Rev. 1.0.2 Not Recommended for New Designs (Suggested Alternate: XRP7714) XRP7724 Quad Channel Digital PWM/PFM Programmable Power Management System INPUT VOLTAGE RANGE AND UNDERVOLTAGE LOCKOUT Parameter VCC Range Min. Typ. Max. Units 5.5 25 V 4.75 5.5 V Conditions • • With VCC connected to LDO5 VOLTAGE FEEDBACK ACCURACY AND OUTPUT VOLTAGE SET POINT RESOLUTION Parameter VOUT Regulation Accuracy Low Output Range 0.6V to 1.6V PWM Operation VOUT Regulation Accuracy Mid Output Range 0.6V to 3.2V PWM Operation VOUT Regulation Accuracy High Output Range 0.6V to 5.5V PWM Operation VOUT Regulation Range Min. Typ. -5 -20 -7.5 -22.5 -15 -45 -20 -50 -30 -90 -40 -100 0.6 Max. Units 5 20 7.5 22.5 15 45 20 50 30 90 40 100 5.5 mV mV mV mV mV mV mV mV mV mV mV mV V Conditions • • • • • • • 0.6 ≤ VOUT ≤ 1.6V 0.6 ≤ VOUT ≤ 1.6V VCC = LDO5 0.6 ≤ VOUT ≤ 3.2V 0.6 ≤ VOUT ≤ 3.2V VCC = LDO5 0.6 ≤ VOUT ≤ 5.5V 0.6 ≤ VOUT ≤ 4.2V, VIN = 5V VCC = LDO5 Without external divider network 12.5 25 50 mV Low Range Mid Range High Range VOUT Fine Set Point Resolution1 2.5 5 10 mV Low Range Mid Range High Range VOUT Input Resistance 120 90 75 kΩ Low Range Mid Range High Range VOUT Input Resistance in PFM Operation 10 1 0.67 MΩ Low Range Mid Range High Range VOUT Native Set Point Resolution Power Good and OVP Set Point Range (from set point) -155 -310 -620 157.5 315 630 mV Low Range Mid Range High Range Power Good and OVP Set Point Accuracy -5 -10 -20 5 10 20 mV Low Range Mid Range High Range 16 V 0.5 V BFB Set Point Range 9 1 BFB Set Point Resolution BFB Accuracy -0.5 V Note 1: Fine Set Point Resolution not available in PFM 4/31 Rev. 1.0.2 Not Recommended for New Designs (Suggested Alternate: XRP7714) XRP7724 Quad Channel Digital PWM/PFM Programmable Power Management System CURRENT AND AUX ADC (MONITORING ADCS) Parameter Current Sense Accuracy Min. Typ. Max. Units -3.75 -10 -5 -12.5 ±1.25 3.75 10 5 +12.5 mV mV mV mV LSB ±2.5 Current Sense ADC INL +/-0.4 Conditions • Low Range (≤120mV) Note 2 -60mV applied • High Range (≤280mV) -150mV DNL 0.27 Current Limit Set Point Resolution and Current Sense ADC Resolution 1.25 mV Low Range (≤120mV) 2.5 mV High Range (≤280mV) Current Sense ADC Range -120 20 mV Low Range (≤120mV) -280 40 mV High Range (≤280mV) mV Low Range Mid Range High Range 15 30 60 VOUT ADC Resolution VOUT ADC Accuracy -1 1 LSB VCC ADC Range 4.6 25 V Note 3 UVLO WARN SET 4.4 4.72 V UVLO WARN set point 4.6V, VCC = LDO5 UVLO WARN CLEAR 4.4 4.72 V UVLO WARN set point 4.6V, VCC = LDO5 UVLO FAULT SET (Note 4) 4.2 4.55 V UVLO FAULT set point 4.4V, VCC = LDO5 200 VCC ADC Resolution VCC ADC Accuracy 1 -1 Die Temp ADC Resolution Die Temp ADC Range mV 5 Vin 1uF) to PAD is recommended for each VCCD pin with the pin(s) connected to LDO5 with shortest possible length of etch. VCCD1-2 VCCD3-4 23,34 AGND 2 GL_RTN1GL_RTN4 39,33, 28,22 GL1-GL4 38,32, 27,21 Output pin of the low side gate driver. Connect directly to the gate of an external Nchannel MOSFET. GH1-GH4 36,30, 25,19 Output pin of the high side gate driver. Connect directly to the gate of an external Nchannel MOSFET. Analog ground pin. This is the small signal ground connection. Ground connection for the low side gate driver. This should be routed as a signal trace with GL. Connect to the source of the low side MOSFET. 9/31 Rev. 1.0.2 Not Recommended for New Designs (Suggested Alternate: XRP7714) XRP7724 Quad Channel Digital PWM/PFM Programmable Power Management System Name Pin Number Description LX1-LX4 37,31, 26,20 Lower supply rail for the GH high-side gate driver. Connect this pin to the switching node at the junction between the two external power MOSFETs and the inductor. These pins are also used to measure voltage drop across bottom MOSFETs in order to provide output current information to the control engine. BST1-BST4 35,29, 24,18 High side driver supply pin(s). Connect BST to the external capacitor as shown in the Typical Application Circuit on page 2. The high side driver is connected between the BST pin and LX pin and delivers the BST pin voltage to the high side FET gate each cycle. GPI0-GPIO1 9,10 These pins can be configured as inputs or outputs to implement custom flags, power good signals, enable/disable controls and synchronization to an external clock. PSIO0-PSIO2 13,14,15 Open drain, these pins can be used to control external power MOSFETs to switch loads on and off, shedding the load for fine grained power management. They can also be configures as standard logic outputs or inputs just as any of the GPIOs can be configured, but as open drains require an external pull-up when configured as outputs. SDA, SCL 11,12 VOUT1-VOUT4 5,6,7,8 Connect to the output of the corresponding power stage. The output is sampled at least once every switching cycle LDO5 44 Output of a 5V LDO. This is a micro power LDO that can remain active while the rest of the IC is in shutdown. This LDO is also used to power the internal Analog Blocks. LDO3_3 1 Output of the 3.3V standby LDO. This is a micro power LDO that can remain active while the rest of the IC is in shutdown. ENABLE 40 If ENABLE is pulled high or allowed to float high, the chip is powered up (logic is reset, registers configuration loaded, etc.). The pin must be held low for the XRP7724 to be placed into shutdown. BFB 42 Input from the 15V output created by the external boost supply. When this pin goes below a pre-defined threshold, a pulse is created on the low side drive to charge this output back to the original level. If not used, this pin should be connected to GND. DGND 17 Digital ground pin. This is the logic ground connection, and should be connected to the ground plane close to the PAD. CPLL 3 V5EXT 43 External 5V that can be provided. If one of the output channels is configured for 5V, then this voltage can be fed back to this pin for reduced operating current of the chip and improved efficiency. AVDD 4 Output of the internal 1.8V LDO. A decoupling capacitor should be placed between AVDD and AGND close to the chip. PAD 45 SMBus/I2C serial interface communication pins. Connect to a 2.2nF capacitor to GND. This is the die attach paddle, which is exposed on the bottom of the part. externally to the ground plane. Connect ORDERING INFORMATION(1) Part Number XRP7724ILB-F XRP7724ILBTR-F Junction Temperature Range Lead-Free Package Packing Method I2C Default Address -40°C ≤ TJ ≤ +125°C Yes(2) 44-pin TQFN Tray Tape & Reel 0x28 (7Bit) XRP7724EVB-DEMO-2 XRP7724 Evaluation Board XR77XXEVB-XCM-V62 Configuration Module XRP7724EVB-DEMO-2-KITA Includes XRP7724EVB-DEMO-2 Evaluation Board, XRP77XXEVB-XCM-V62 Configuration Module and PowerArchitect™ Software NOTES: 1. Refer to www.exar.com/XRP7724 for most up-to-date Ordering Information. 2. Visit www.exar.com for additional information on Environmental Rating. 10/31 Rev. 1.0.2 Not Recommended for New Designs (Suggested Alternate: XRP7714) XRP7724 Quad Channel Digital PWM/PFM Programmable Power Management System TYPICAL PERFORMANCE CHARACTERISTICS All data taken at VCC = 12V, TJ = TA = 25°C, unless otherwise specified - Schematic and BOM from XRP7724EVB. See XRP7724EVB-DEMO-1 Manual. Fig. 5: PFM to PWM Transition Fig. 6 PWM to PFM Transition Fig. 7 0-6A Transient 300kHz PWM only Fig. 8 10-6A Transient 300kHz with OVS ±5.5% Fig. 9 Sequential Start-up Fig. 10 Sequential Shut Down 11/31 Rev. 1.0.2 Not Recommended for New Designs (Suggested Alternate: XRP7714) XRP7724 Quad Channel Digital PWM/PFM Programmable Power Management System Example Fig. 11: Simultaneous Start-up Fig. 12 Simultaneous Shut Down Fig. 13: PFM Zero Current Accuracy Fig. 14: LDO5 Brown Out Recovery, No Load 1.00 0.95 0.90 Vin=25V Rising 0.85 Vin=25V Falling 0.80 0.75 Vin=4.75 V Rising 0.70 Vin=4.75 V Falling 0.65 0.60 -40°C 25°C 85°C 125°C Fig. 15: Enable Threshold Over Temp 12/31 Rev. 1.0.2 Not Recommended for New Designs (Suggested Alternate: XRP7714) XRP7724 Quad Channel Digital PWM/PFM Programmable Power Management System FEATURES AND BENEFITS System Integration Capabilities • Single supply operation Programmable Power Benefits • I2C interface allows: • Fully Configurable − Communication with a System Controller or other Power Management devices for optimized system function − Output set point − Feedback compensation − Frequency set point − Access to modify or read internal registers that control or monitor: − Under voltage lock out − Input voltage measurement − Output Current − Gate drive dead time − Input and Output Voltage − Soft-Start/Soft-Stop Time • Reduced Development Time − ‘Power Good’ − Configurable and re-configurable for different Vout, Iout, Cout, and Inductor values − Part Temperature − Enable/Disable Outputs − No need to change external passives for a new output specification. − Over Current − Over Voltage • Higher integration and Reliability − Temperature Faults − Many external circuits used in the past can be eliminated significantly improving reliability. − Adjusting fault limits and disabling/enabling faults − Packet Error Checking (PEC) on I2C communication PowerArchitect™ Design and Configuration Software (PA5) • 5 GPIO pins with a wide range of configurability − Wizard quickly generates a base design − Fault reporting (including UVLO Warn/Fault, OCP Warn/Fault, OVP, Temperature, Soft-Start in progress, Power Good, System Reset) − Calculates all configuration registers − Projects can be saved and/or recalled − GPIOs can be configured easily and intuitively − Allows a Logic Level interface with other non-digital IC’s or as logic inputs to other devices − “Dashboard” Interface can be used for real-time monitoring and debug • Frequency and Synchronization Capability System Benefits • Reliability is enhanced via communication with the system controller which can obtain real time data on an output voltage, input voltage and current. − Selectable switching frequency between 105kHz and 1.2MHz − Main oscillator clock and DPWM clock can be synchronized to external sources • System processors can communicate with the XRP7724 directly to obtain data or make adjustments to react to circuit conditions − ‘Master’, ‘Slave’ and ‘Stand-alone’ Configurations are possible • Internal MOSFET Drivers − Internal FET drivers (4Ω/2Ω) per channel • A system process or could also be configured to log and analyze operating history, perform diagnostics and if required, take the supply off-line after making other system adjustments. − Built-In Automatic Dead-time adjustment − 30ns Rise and Fall times • 4 Independent SMPS channels and 2 LDOs in a 7x7mm TQFN 13/31 Rev. 1.0.2 Not Recommended for New Designs (Suggested Alternate: XRP7714) XRP7724 Quad Channel Digital PWM/PFM Programmable Power Management System FUNCTIONAL OVERVIEW external circuitry. The 3.3V LDO is solely for customer use and is not used by the chip. There is also a 1.8V linear which is for internal use only and should not be used externally. The XRP7724 is a quad-output digital pulse width modulation (DPWM) controller with integrated gate drivers for use with synchronous buck switching regulators. Each output voltage can be programmed from 0.6V to 5.5V without the need of an external voltage divider. The wide range of the programmable DPWM switching frequency (from 105 kHz to 1.2 MHz) enables the user to optimize for efficiency or component sizes. Since the digital regulation loop requires no external passive components, loop performance is not compromised due to external component variation or operating condition. A key feature of the XRP7724 is its powerful power management capabilities. All four outputs are independently programmable and gives the user not only full control of the delay, ramp, and sequence during power up and power down. One can also control of how the outputs interact and power down in the event of a fault. This includes active ramp down of the output voltages to remove an output voltage as quickly as possible. Another nice feature is that the outputs can be defined and controlled as groups. The XRP7724 provides a number of critical safety features, such as Over-Current Protection (OCP), Over-Voltage Protection (OVP), Over Temperature Protection (OTP) plus input Under Voltage Lockout (UVLO). In addition, a number of key health monitoring features such as warning level flags for the safety functions, Power Goods (PGOOD), etc., plus full monitoring of system voltages and currents. The above are all programmable and/or readable from the SMBus and many are steerable to the GPIOs for hardware monitoring. The XRP7724 has two main types of programmable memory. The first types are runtime registers that contain configuration, control and monitoring information for the chip. The second type is rewritable Non-Volatile Flash Memory (NVFM) that is used for permanent storage of the configuration data along with various chip internal functions. During power up the run time registers are loaded from the NVFM allowing for standalone operation. The XRP7724 brings an extremely high level of functionality and performance to a programmable power system. Ever decreasing product budgets require the designer to quickly make good cost/performance tradeoffs to be truly successful. By incorporating 4 switching channels, two user LDOs, a charge pump boost controller, along with internal gate drivers, all in a single package, the XRP7724 allows for extremely cost effective power system designs. Another key cost factor to put into the cost tradeoffs, which is often overlooked, is the unanticipated Engineering Change Order (ECO). The programmable versatility of the XRP7724, along with the lack of hard wired, on board configuration components, allows for minor and major changes to be made, in circuit, on the board by simple reprogramming. For hardware communication, the XRP7724 has two logic level General Purpose Input-Output (GPIO) pins and three, 15V, open drain, Power System Input-Output (PSIO) pins. Two pins are dedicated to the SMBus data (SDA) and clock (SCL). Additional pins include Chip Enable (Enable), Aux Boost Feedback (BFB) and External PLL Capacitor (CPLL). In addition to providing four switching outputs, the XRP7724 also provides control for an Aux boost supply, and two stand-by linear regulators that produce 5V and 3.3V for a total of 7 customer usable supplies in a single device. The 5V LDO is used for internal power and is also available for customer use to power 14/31 Rev. 1.0.2 Not Recommended for New Designs (Suggested Alternate: XRP7714) XRP7724 Quad Channel Digital PWM/PFM Programmable Power Management System THEORY OF OPERATION CHIP ARCHITECTURE REGULATION LOOPS Vin (VCC) Vref DAC VFB (VOUTx) Scalar ÷1,2,4 AFE Error Amp AFE ADC Window Comp. Fine Adjust Vin Feed Forward Error Register PID Vdrive (VCCD)x DPWM Gate Driver GHx GLx LXx Current ADC OVS PFM/ Ultrasonic PWMPFM Sel Fig 16 XRP7724 Regulation Loops Figure 16 shows a functional block diagram of the regulation loops for an output channel. There are four separate parallel control loops; Pulse Width Modulation (PWM), Pulse Frequency Modulation (PFM), Ultrasonic, and Over Sampling (OVS). Each of these loops is fed by the Analog Front End (AFE) as shown at the left of the diagram. The AFE consist of an input voltage scalar, a programmable Voltage Reference (Vref) DAC, Error Amplifier, and a window comparator. (Please note that the block diagram shown is simplified for ease of understanding. Some of the function blocks are common and shared by each channel by means of a multiplexer.) (low range) the scalar has a gain of 1. For output voltages from 1.6V to 3.2V (mid range) the scalar gain is 1/2 and for voltages greater than 3.2V (high range) the gain is 1/4. This results in the low range having a reference voltage resolution of 12.5mV, mid range of 25mV and the high range having a resolution of 50mV. The error amp has a gain of 4 and compares the output voltage of the scalar to Vref to create an error voltage on its output. This is converted to a digital error term by the AFE ADC which is stored in the error register. The error register has a fine adjust function that can be used to improve the output voltage set point resolution by a factor of 5 resulting in a low range resolution of 2.5mV, mid range resolution of 5mV and a high range resolution of 10mV. The output of the error resister is then used by the Proportional Integral Derivative (PID) controller to manage the loop dynamics. PWM Loop The PWM loop operates in Voltage Control Mode (VCM) with optional Vin feed forward based on the voltage at the VCC pin. The reference voltage (Vref) for the error amp is created by a 0.15V to 1.6V DAC that has a 12.5mV resolution. In order to get a full 0.6V to 5.5V output voltage range an input scalar is used to reduce feedback voltages for higher output voltages to bring them within the 0.15V to 1.6V control range. So for output voltages up to 1.6V The XRP7724 PID is a 17-bit five coefficient control engine that calculates the correct duty cycle under the various operating conditions and feeds it to the Digital Pulse Width Modulator (DPWM). Besides the normal coefficients the PID also uses the Vin voltage to provide a feed forward function. 15/31 Rev. 1.0.2 Not Recommended for New Designs (Suggested Alternate: XRP7714) XRP7724 Quad Channel Digital PWM/PFM Programmable Power Management System The XRP7724 DPWM includes a special delay timing loop that gives a timing resolution that is 16 times the master oscillator frequency (103MHz) for a timing resolution of 607ps for both the driver pulse width and dead time delays. The DWPM creates and outputs the Gate High (GH) and Gate Low (GL) signals to the driver. The maximum and minimum on times and dead time delays are programmable by configuration resisters. current falls below a programmed threshold level for a programmed number of cycles. When PFM mode is entered, the PWM loop is disabled and instead, the scaled output voltage is compared to Vref with a window comparator. The window comparator has three thresholds; normal (Vref), high (Vref + %high) and low (Vref - %low). The %high and %low values are programmable and track Vref. In PFM mode, the normal comparator is used to regulate the output voltage. If the output voltage falls below the Vref level, the comparator is activated and triggers the DPWM to start a switching cycle. When the high side FET is turned on, the inductor current ramps up which charges up the output capacitors and increasing their voltage. After the completion of the high side and low side on-times, the lower FET is turned off to inhibit any inductor reverse current flow. The load current then discharges the output capacitors until the output voltage falls below Vref and the normal comparator is activated this then triggers the DPWM to start the next switching cycle. The time from the end of the switching cycle to the next trigger is referred to as the dead zone. This PFM methodology ensures output voltage ripple does not increase from PWM to PFM. To provide current information, the output inductor current is measured by a differential amplifier that reads the voltage drop across the RDS of lower FET during its on time. There are two selectable ranges, a low range with a gain of 8 for a +20mV to -120 mV range and a high range with a gain of 4 for +40mV to -280mV range. The optimum range to use will depend on the maximum output current and the RDS of the lower FET. The measured voltage is then converted to a digital value by the current ADC block. The resulting current value is stored in a readable register and also used to determine when PWM to PFM transitions should occur. PFM mode loop The XRP7724 has a PFM loop that can be enabled to improve efficiency at light loads. By reducing switching frequency and operating in the discontinuous conduction mode (DCM), both switching and I2R losses are minimized. When PFM mode is initially entered the switching duty cycle is the same that it was in PWM mode. The cause the inductor ripple current to be the same level that it was in PWM mode. During operation the PFM duty cycle is calculated based on the ratio of the output voltage to VCC. Figure 17 shows a functional diagram of the PFM logic. # Cycles Reg Default = 20 If the output voltage ever goes outside the high/low windows, PFM mode is exited and the PWM loop is reactivated. A CHx Fsw PFM Current Threshold Reg A Clk COUNTER Clear A