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ES29LV160D
16Mbit(2M x 8/1M x 16) CMOS 3.0 Volt-only, Boot Sector Flash Memory
GENERAL FEATURES
• Single power supply operation - 2.7V -3.6V for read, program and erase operations
• Minimum 100,000 program/erase cycles per sector • 20 Year data retention at 125oC
SOFTWARE FEATURES
• Sector Structure - 16Kbyte x 1, 8Kbyte x 2, 32Kbyte x 1 boot sectors - 64Kbyte x 31 sectors • Top or Bottom boot block - ES29LV160DT for Top boot block device - ES29LV160DB for Bottom boot block device • Package Options - 48-pin TSOP - 48-ball FBGA ( 6 x 8 mm ) - Pb-free packages - All Pb-free products are RoHS-Compliant • Low Vcc write inhibit • Manufactured on 0.18um process technology • Compatible with JEDEC standards - Pinout and software compatible with single-power supply flash standard • • • • • • Erase Suspend / Erase Resume Data# poll and toggle for Program/erase status CFI ( Common Flash Interface) supported Unlock Bypass program Autoselect mode Auto-sleep mode after tACC + 30ns
HARDWARE FEATURES
• Hardware reset input pin ( RESET#) - Provides a hardware reset to device - Any internal device operation is terminated and the device returns to read mode by the reset • Ready/Busy# output pin ( RY/BY#) - Provides a program or erase operational status about whether it is finished for read or still being progressed • Sector protection / unprotection ( RESET# , A9 ) - Hardware method of locking a sector to prevent any program or erase operation within that sector - Two methods are provided : - In-system method by RESET# pin - A9 high-voltage method for PROM programmers • Temporary Sector Unprotection ( RESET# ) - Allows temporary unprotection of previously protected sectors to change data in-system
DEVICE PERFORMANCE
• Read access time - 90ns/120n for normal Vcc range ( 2.7V - 3.6V ) - 70ns for regulated Vcc range ( 3.0V - 3.6V ) • Program and erase time - Program time : 6us/byte, 8us/word ( typical ) - Sector erase time : 0.7sec/sector ( typical ) • Power consumption (typical values) - 200nA in standby or automatic sleep mode - 9mA active read current at 5 MHz - 15mA active write current during program or erase
ES29LV160D
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GENERAL PRODUCT DESCRIPTION
The ES29LV160 is a 16 megabit, 3.0 volt-only flash memory device, organized as 2M x 8 bits (Byte mode) or 1M x 16 bits (Word mode) which is configurable by BYTE#. Four boot sectors and thirty one main sectors are provided : 16Kbytes x 1, 8Kbytes x 2, 32Kbytes x 1 and 64Kbytes x 31. The device is manufactured with ESI’s proprietary, high performance and highly reliable 0.18um CMOS flash technology. The device can be programmed or erased in-system with standard 3.0 Volt Vcc supply ( 2.7V-3.6V) and can also be programmed in standard EPROM programmers. The device offers minimum endurance of 100,000 program/erase cycles and more than 10 years of data retention. The ES29LV160 offers access time as fast as 70ns or 90ns, allowing operation of high-speed microprocessors without wait states. Three separate control pins are provided to eliminate bus contention : chip enable (CE#), write enable (WE#) and output enable (OE#). All program and erase operation are automatically and internally performed and controlled by embedded program/erase algorithms built in the device. The device automatically generates and times the necessary high-voltage pulses to be applied to the cells, performs the verification, and counts the number of sequences. Some status bits (DQ7, DQ6 and DQ5) read by data# polling or toggling between consecutive read cycles provide to the users the internal status of program/erase operation: whether it is successfully done or still being progressed.
The ES29LV160 is completely compatible with the JEDEC standard command set of single power supply Flash. Commands are written to the internal command register using standard write timings of microprocessor and data can be read out from the cell array in the device with the same way as used in other EPROM or flash devices.
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PRODUCT SELECTOR GUIDE
Family Part Number Voltage Range Speed Option Max Access Time (ns) CE# Access (ns) OE# Access (ns) 3.0 ~ 3.6V 70R 70 70 35 90 90 90 40 ES29LV160 2.7 ~ 3.6V 120 120 120 50
FUNCTION BLOCK DIAGRAM
RY/BY# Vcc Vss Vcc Detector Timer/ Counter DQ0-DQ15(A-1)
Analog Bias Generator WE# RESET# Command Register Write State Machine
Input/Output Buffers
Sector Switches
Data Latch/ Sense Amps
Y-Decoder A Address Latch
Y-Decoder
CE# OE# BYTE#
X-Decoder
Cell Array
Chip Enable Output Enable Logic
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PIN DESCRIPTION
Pin
A0-A19 DQ0-DQ14 DQ15/A-1 CE# OE# WE# RESET# BYTE# RY/BY# Vcc Vss NC 20 Addresses 15 Data Inputs/Outputs DQ15 (Data Input/Output, Word Mode) A-1 (LSB Address Input, Byte Mode) Chip Enable Output Enable Write Enable Hardware Reset Pin, Active Low Selects 8-bit or 16-bit mode Ready/Busy Output (N/A SO 044) 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) Device Ground Pin Not Connected Internally
Description
LOGIC SYMBOL
20 A0 ~ A19 DQ0 ~ DQ15 (A-1)
16 or 8
CE# OE# WE# RESET# BYTE# RY/BY# (N/A SO 044)
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CONNECTION DIAGRAM
A15 A14 A13 A12 A11 A10 A9 A8 A19 NC WE# RESET# NC NC RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48-Pin Standard TSOP
ES29LV160
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
A16 BYTE# Vss DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 Vcc DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# Vss CE# A0
48-Ball FBGA (6 x 8 mm)
(Top View, Balls Facing Down)
A B C D E F G H
6
A13
A12
A14
A15
A16
BYTE#
DQ15/ A-1
Vss
5
A9
A8
A10
A11
DQ7
DQ14
DQ13
DQ6
4
WE#
RESET#
NC
A19
DQ5
DQ12
Vcc
DQ4
3
RY/ BY#
NC
A18
NC
DQ2
DQ10
DQ11
DQ3
2
A7
A17
A6
A5
DQ0
DQ8
DQ9
DQ1
1
A3
A4
A2
A1
A0
CE#
OE#
Vss
ES29LV160D
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DEVICE BUS OPERATIONS
Several device operational modes are provided in the ES29LV160 device. Commands are used to initiate the device operations. They are latched and stored into internal registers with the address and data information needed to execute the device operation. The available device operational modes are listed in Table 1 with the required inputs, controls, and the resulting outputs. Each operational mode is described in further detail in the following subsections.
on the device address inputs produce valid data on the device data outputs. The device stays at the read mode until another operation is activated by writing commands into the internal command register. Refer to the AC read cycle timing diagrams for further details ( Fig. 16 ).
Word/Byte Mode Configuration ( BYTE# )
The device data output can be configured by BYTE# into one of two modes : word and byte modes. If the BYTE# pin is set at logic ‘1’, the device is configured in word mode, DQ0 - DQ15 are active and controlled by CE# and OE#. If the BYTE# pin is set at logic ‘0’, the device is configured in byte mode, and only data I/O pins DQ0 - DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8 - DQ14 are tristated, and the DQ15 pin is used as an input for the LSB (A-1) address.
Read
The internal state of the device is set for the read mode and the device is ready for reading array data upon device power-up, or after a hardware reset. To read the stored data from the cell array of the device, CE# and OE# pins should be driven to VIL while WE# pin remains at VIH. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. Word or byte mode of output data is determined by the BYTE# pin. No additional command is needed in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses
Standby Mode
When the device is not selected or activated in a system, it needs to stay at the standby mode, in which current consumption is greatly reduced with outputs in the high impedance state.
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The device enters the CMOS standby mode when CE# and RESET# pins are both held at Vcc+0.3V. (Note that this is a more restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within Vcc+0.3V, the device will be still in the standby mode, but the standby current will be greater than the CMOS standby current (0.2uA typically). When the device is in the standby mode, only standard access time (tCE) is required for read access, before it is ready for read data. And even if the device is deselected by CE# pin during erase or programming operation, the device draws active current until the operation is completely done. While the device stays in the standby mode, the output is placed in the high impedance state, independent of the OE# input. The device can enter the deep power-down mode where current consumption is greatly reduced down to less than 0.2uA typically by the following three ways:
- CMOS standby ( CE#, RESET# = Vcc + 0.3V ) - During the device reset ( RESET# = Vss + 0.3V ) - In Autosleep Mode ( after tACC + 30ns )
set-up cycle and the last cycle with the program data and addresses. In this mode, two unlock cycles are saved ( or bypassed ).
Sector Addresses
The entire memory space of cell array is divided into a many of small sectors: 16Kbytes x 1, 8Kbytes x 2, 32Kbytes x 1 and 64Kbytes x 31 main sectors. In erase operation, a single sector, multiple sectors, or the entire device (chip erase) can be selected for erase. The address space that each sector occupies is shown in detail in the Table 3-4.
Autoselect Mode
Flash memories are intended for use in applications where the local CPU alters memory contents. In such applications, manufacturer and device identification (ID) codes must be accessible while the device resides in the target system ( the so called “in-system program”). On the other hand, signature codes have been typically accessed by raising A9 pin to a high voltage in PROM programmers. However, multiplexing high voltage onto address lines is not the generally desired system design practice. Therefore, in the ES29LV160 device an autoselect command is provided to allow the system to access the signature codes without any high voltage. The conventional A9 high-voltage method used in the PROM programers for signature codes are still supported in this device. If the system writes the autoselect command sequence, the device enters the Autoselect mode. The system can then read some useful codes such as manufacturer and device ID from the internal registers on DQ7 - DQ0. Standard read cycle timings apply in this mode. In the Autoselect mode, the following three informations can be accessed through either autoselect command method or A9 high-voltage autoselect method. Refer to the Table 2. - Manufacturer ID - Device ID - Sector protection verify
Refer to the CMOS DC characteristics Table11 for further current specification.
Autosleep Mode
The device automatically enters a deep power-down mode called the autosleep mode when addresses remain stable for tACC+30ns. In this mode, current consumption is greatly reduced ( less than 0.2uA typical ), regardless of CE#, WE# and OE# control signals.
Writing Commands
To write a command or command sequences to initiate some operations such as program or erase, the system must drive WE# and CE# to VIL, and OE# to VIH. For program operations, the BYTE# pin determines whether the device accepts program data in bytes or words. Refer to “BYTE# timings for Write Operations” in the Fig. 19 for more information.
Hardware Device Reset ( RESET# )
The RESET# pin provides a hardware method of resetting the device to read array data. When the RESET# pin is driven low for at least a period of tRP ,
Unlock Bypass Mode
To reduce more the programming time, an unlockbypass mode is provided. Once the device enters this mode, only two write cycles are required to initiate the programming operation instead of four cycles in the normal program command sequences which are composed of two unlock cycles, program
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the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once after the device is ready to accept another command sequence, to ensure data integrity.
Sector protection can be implemented via two methods. - In-system protection - A9 High-voltage protection To check whether the sector protection was successfully executed or not, another operation called “protect verification” needs to be performed after the protection operation on a sector. All protection and protect verifications provided in the device are summarized in detail at the Table 1.
CMOS Standby during Device Reset
Current is reduced for the duration of the RESET# pulse. When RESET# is held at Vss + 0.3V, the device draws the greatly reduced CMOS standby current ( ICC4 ). If RESET# is held at VIL but not within Vss+0.3V, the standby current will be greater.
In-System Protection
“In-system protection”, the primary method, requires VID (11.5V~12.5V) on the RESET# with A6=0, A1=1, and A0=0. This method can be implemented either in-system or via programming equipment. This method uses standard microprocessor bus cycle timing. Refer to Fig. 26 for timing diagram and Fig. 2 for the protection algorithm.
RY/BY# and Terminating Operations
If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the internal reset operation is completed, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is completed. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is “1”), the reset operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data after the RESET# pin returns to VIH, which requires a time of tRH.
A9 High-Voltage Protection
“High-voltage protection”, the alternate method intended only for programming equipment, must force VID (11.5~12.5V) on address pin A9 and control pin OE# with A6=0, A1=1 and A0=0. Refer to Fig. 28 for timing diagram and Fig. 4 for the protection algorithm.
RESET# tied to the System Reset
The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the bootup firmware from the Flash memory.Refer to the AC Characteristics tables for RESET# parameters and to Fig. 17 for the timing diagram.
SECTOR UNPROTECTION
The previously protected sectors must be unprotected before modifying any data in the sectors. The sector unprotection algorithm unprotects all sectors in parallel. All unprotected sectors must first be protected prior to the first sector unprotection write cycle to avoid any over-erase due to the intrinsic erase characteristics of the protection cell. After the unprotection operation, all previously protected sectors will need to be individually re-protected. Standard microprocessor bus cycle timings are used in the unprotection and unprotect verification operations. Three unprotect methods are provided in the ES29LV160 device. All unprotection and unprotect verification cycles are summarized in detail at the Table 1. - In-system unprotection - A9 High-voltage unprotection - Temporary sector unprotection
SECTOR PROTECTION
The ES29LV160 features hardware sector protection. In the device, sector protection is performed on the sector previously defined in the Table 3-4. Once after a sector is protected, any program or erase operation is not allowed in the protected sector. The previously protected sectors must be unprotected by one of the unprotect methods provided here before changing data in those sectors.
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In-System Unprotection
“In-system unprotection”, the primary method, requires VID (11.5V~12.5V) on the RESET# with A6=1, A1=1, and A0=0. This method can be implemented either in-system or via programming equipment. This method uses standard microprocessor bus cycle timing. Refer to Fig. 26 for timing diagram and Fig. 3 for the unprotection algorithm.
The command register and all internal program/ erase circuits are disabled, and the device resets to the read mode. Subsequent writes are ignored until Vcc is greater than VLKO. The system must provide proper signals to the control pins to prevent unintentional writes when Vcc is greater than VLKO.
Write Pulse “Glitch” Protection
Noise pulses of less than 5ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
A9 High-Voltage Unprotection
“High-voltage unprotection”, the alternate method intended only for programming equipment, must force VID (11.5~12.5V) on address pin A9 and control pin OE# with A6=1, A1=1 and A0=0. Refer to Fig. 29 for timing diagram and Fig. 5 for the unprotection algorithm.
Logical inhibit
Write cycles are inhibited by holding any one of OE#=VIL, CE#=VIH or WE#=VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one.
Temporary Sector Unprotect
This feature allows temporary unprotection of previously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RESET# pin to VID (11.5V-12.5V). During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once VID is removed from the RESET# pin, all the previously protected sectors are protected again. Fig. 1 shows the algorithm, and Fig. 25 shows the timing diagrams for this feature.
Power-up Write Inhibit
If WE#=CE#=VIL and OE#=VIH during power up, the device does not accept any commands on the rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up.
START
HARDWARE DATA PROTECTION
The ES29LV160 device provides some protection measures against accidental erasure or programming caused by spurious system level signals that may exist during power transition. During power-up, all internal registers and latches in the device are cleared and the device automatically resets to the read mode. In addition, with its internal state machine built-in the device, any alteration of the memory contents or any initiation of new operationcan only occur after successful completion of specific command sequences. And several features are incorporated to prevent inadvertent write cycles resulting from Vcc power-up and power-down transition or system noise.
RESET# = VID (Note 1)
Perform Erase or Program Operations
RESET# = VIH
Temporary Sector Unprotect Completed (Note 2)
Notes:
1. All protected sectors are unprotected . 2. All previously protected sectors are protected once again.
Low Vcc Write inhibit
When Vcc is less than VLKO, the device does not accept any write cycles. This protects data during Vcc power-up and power-down.
Figure 1. Temporary Sector Unprotect Operation
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Table 1. ES29LV160 Device Bus Operations
DQ0 ~ DQ7 DQ8~DQ15 BYTE# = VIH
DOUT (Note 3) High-Z High-Z Output Disable Reset L X Sector Protect (Note 2) Sector Unprotect (Note 2) Temporary Sector Unprotect L H X H H X L H L VID X X SA,A6=L, A1=H,A0=L SA,A6=H, A1=H,A0=L High-Z High-Z (Note 3) High-Z High-Z X X
Operation
CE#
OE#
WE#
RESET#
Addresses (Note 1)
BYTE# = VIL
DQ8~DQ14 = High-Z, DQ15 = A-1
Read Write Standby
L L Vcc+ 0.3V
L H X
H L
H H Vcc+ 0.3V
AIN AIN X
DOUT (Note 3) High-Z
X
In-system
L
H
L
VID
(Note 3)
X
X
X
X
X
VID
AIN SA,A9=VID, A6=L, A1=H,A0=L
(Note 3)
(Note 3)
High-Z
Sector protect A9 High-Voltage Method Sector unprotect
L
VID
L
H
(Note 3) L VID L H SA,A9=VID, A6=H, A1=H,A0=L
(Note 3)
High-Z
Legend: L=Logic Low=VIL, H=Logic High=VIH, VID=11.5-12.5V, X=Don’t Care, SA=Sector Address, AIN=Address In, DIN=Data In,
DOUT=Data Out
Notes:
1. Addresses are A19:A0 in word mode (BYTE#=VIH) , A19:A-1 in byte mode (BYTE#=VIL). 2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector Protection and Unprotection” section. 3. DIN or DOUT as required by command sequence, data polling, or sector protection algorithm.
Table 2. Autoselect Codes (A9 High-Voltage Method)
A19 to A12
X X
Description
CE# OE# WE#
A11 to A10
X X
A9
A8 to A7
X X
A6
A5 to A2
X X
DQ8~DQ15 A1 A0 BYTE# BYTE# = VIH = VIL
X 22h X X
DQ7~DQ0
ManufactureID:ESI Device ID: ES29LV160 Sector Protection Verification
L L
L L
H H
VID VID VID
L L
L L
L H
4Ah C4h(T),49h(B) 01h(protected) 00h(unprotected)
L
L
H
SA
X
X
L
X
H
L
X
X
Legend: T= Top Boot Block, B = Bottom Boot Block, L=Logic Low=VIL, H=Logic High=VIH, SA=Sector Address, X = Don’t care
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Table 3. Top Boot Sector Addresses (ES29LV160DT)
Sector
SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34
Sector address A19~A12
00000XXX 00001XXX 00010XXX 00011XXX 00100XXX 00101XXX 00110XXX 00111XXX 01000XXX 01001XXX 01010XXX 01011XXX 01100XXX 01101XXX 01110XXX 01111XXX 10000XXX 10001XXX 10010XXX 10011XXX 10100XXX 10101XXX 10110XXX 10111XXX 11000XXX 11001XXX 11010XXX 11011XXX 11100XXX 11101XXX 11110XXX 111110XX 11111100 11111101 1111111X
Sector Size (Kbytes/Kwords)
64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 32/16 8/4 8/4 16/8
(X8) Address Range
000000h~00FFFFh 010000h~01FFFFh 020000h~02FFFFh 030000h~03FFFFh 040000h~04FFFFh 050000h~05FFFFh 060000h~06FFFFh 070000h~07FFFFh 080000h~08FFFFh 090000h~09FFFFh 0A0000h~0AFFFFh 0B0000h~0BFFFFh 0C0000h~0CFFFFh 0D0000h~0DFFFFh 0E0000h~0EFFFFh 0F0000h~0FFFFFh 100000h~10FFFFh 110000h~11FFFFh 120000h~12FFFFh 130000h~13FFFFh 140000h~14FFFFh 150000h~15FFFFh 160000h~16FFFFh 170000h~17FFFFh 180000h~18FFFFh 190000h~19FFFFh 1A0000h~1AFFFFh 1B0000h~1BFFFFh 1C0000h~1CFFFFh 1D0000h~1DFFFFh 1E0000h~1EFFFFh 1F0000h~1F7FFFh 1F8000h~1F9FFFh 1FA000h~1FBFFFh 1FC000h~1FFFFFh
(X16) Address Range
00000h~07FFFh 08000h~0FFFFh 10000h~17FFFh 18000h~1FFFFh 20000h~27FFFh 28000h~2FFFFh 30000h~37FFFh 38000h~3FFFFh 40000h~47FFFh 48000h~4FFFFh 50000h~57FFFh 58000h~5FFFFh 60000h~67FFFh 68000h~6FFFFh 70000h~77FFFh 78000h~7FFFFh 80000h~87FFFh 88000h~8FFFFh 90000h~97FFFh 98000h~9FFFFh A0000h~A7FFFh A8000h~AFFFFh B0000h~B7FFFh B8000h~BFFFFh C0000h~C7FFFh C8000h~CFFFFh D0000h~D7FFFh D8000h~DFFFFh E0000h~E7FFFh E8000h~EFFFFh F0000h~F7FFFh F8000h~FBFFFh FC000h~FCFFFh
Remark
Main Sector
Boot Sector FD000h~FDFFFh FE000h~FFFFFh
Note:
The addresses range is A19:A-1 in byte mode (BYTE#=VIL) or A19:A0 in word mode (BYTE#=VIH).
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Table 4. Bottom Boot Sector Addresses (ES29LV160DB)
Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 Sector address A19~A12 0000000X 00000010 00000011 000001XX 00001XXX 00010XXX 00011XXX 00100XXX 00101XXX 00110XXX 00111XXX 01000XXX 01001XXX 01010XXX 01011XXX 01100XXX 01101XXX 01110XXX 01111XXX 10000XXX 10001XXX 10010XXX 10011XXX 10100XXX 10101XXX 10110XXX 10111XXX 11000XXX 11001XXX 11010XXX 11011XXX 11100XXX 11101XXX 11110XXX 11111XXX Sector Size (Kbytes/Kwords) 16/8 8/4 8/4 32/16 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 (X8) Address Range 000000h~003FFFh 004000h~005FFFh 006000h~007FFFh 008000h~00FFFFh 010000h~01FFFFh 020000h~02FFFFh 030000h~03FFFFh 040000h~04FFFFh 050000h~05FFFFh 060000h~06FFFFh 070000h~07FFFFh 080000h~08FFFFh 090000h~09FFFFh 0A0000h~0AFFFFh 0B0000h~0BFFFFh 0C0000h~0CFFFFh 0D0000h~0DFFFFh 0E0000h~0EFFFFh 0F0000h~0FFFFFh 100000h~10FFFFh 110000h~11FFFFh 120000h~12FFFFh 130000h~13FFFFh 140000h~14FFFFh 150000h~15FFFFh 160000h~16FFFFh 170000h~17FFFFh 180000h~18FFFFh 190000h~19FFFFh 1A0000h~1AFFFFh 1B0000h~1BFFFFh 1C0000h~1CFFFFh 1D0000h~1DFFFFh 1E0000h~1EFFFFh 1F0000h~1FFFFFh (X16) Address Range 00000h~01FFFh 02000h~02FFFh Boot Sector 03000h~03FFFh 04000h~07FFFh 08000h~0FFFFh 10000h~17FFFh 18000h~1FFFFh 20000h~27FFFh 28000h~2FFFFh 30000h~37FFFh 38000h~3FFFFh 40000h~47FFFh 48000h~4FFFFh 50000h~57FFFh 58000h~5FFFFh 60000h~67FFFh 68000h~6FFFFh 70000h~77FFFh 78000h~7FFFFh 80000h~87FFFh 88000h~8FFFFh 90000h~97FFFh 98000h~9FFFFh A0000h~A7FFFh A8000h~AFFFFh B0000h~B7FFFh B8000h~BFFFFh C0000h~C7FFFh C8000h~CFFFFh D0000h~D7FFFh D8000h~DFFFFh E0000h~E7FFFh E8000h~EFFFFh F0000h~F7FFFh F8000h~FFFFFh Main Sector Remark
Note:
The addresses range is A19:A-1 in byte mode (BYTE#=VIL) or A19:A0 in word mode (BYTE#=VIH).
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In-System Protection / Unprotection Method
START COUNT = 1 RESET# = VID Wait 1us Protect all sectors: The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address
START COUNT = 1 RESET# = VID Wait 1us
Temporary Sector Unprotect Mode
No
First Write Cycle = 60h? Yes Set up sector address Sector Protect: Write 60h to sector address with A6 = 0, A1 = 1, A0 = 0 Wait 150us Verify Sector Protect: Write 40h to sector address with A6 = 0, A1 = 1, A0 = 0 Read from sector address with A6 = 0, A1 = 1, A0 = 0
First Write Cycle = 60h? Yes No All sectors protected ? Yes Set up first sector address Sector Unprotect: Write 60h to sector address with A6 = 1, A1 = 1,
No
Temporary Sector Unprotect Mode
Increment COUNT
Reset COUNT = 1
Wait 15ms Verify Sector Unprotect: Write 40h to sector address with A6 = 1, A1 = 1, A0 = 0 Read from sector address with A6 = 1, A1 = 1, A0 = 0 No No
Increment COUNT
Set up next sector address
No No COUNT=25? Yes Device failed Data = 01h? Yes Protect another sector? No Remove VID from RESET# Write reset command Sector Protect complete Yes
COUNT =1000? Yes Device failed
Data = 00h? Yes Last sector verified? Yes Remove VID from RESET# Write reset command Sector Unprotect complete No
Figure 2. In-System Sector Protect Algorithm
Figure 3. In-System Sector Unprotect Algorithm
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A9 High-Voltage Method
Start
Start Note: All sectors must be previously protected.
COUNT = 1 COUNT = 1 SET A9=OE#=VID SET A9=OE#=VID
Set Sector Address A CE#, A6, A0=VIL RESET#, A1=VIH
CE#, A0=VIL , RESET#, A6, A1=VIH
SET WE# = VIL SET WE# = VIL Wait 15ms Wait 150 us SET WE# = VIH Increase COUNT SET WE# = VIH Increase COUNT CE#,OE#,A6,A0=VIL RESET#, A1 = VIH CE#,OE#, A0=VIL RESET#, A6, A1=VIH
Set Sector AddressA Read Data No No No COUNT= 25? Data = 01h? No COUNT=1000? Yes Yes Yes Device failed Protect Another Sector ? Yes Device failed The Last Sector Address ? No Remove VID from A9 and Write Reset Command Yes Remove VID from A9 and Write Reset Command No Yes Data = 00h? Increase Sector Address Read Data
Sector Protection Complete Sector Unprotection Complete
Figure 4. Sector Protection Algorithm (A9 High-Voltage Method)
Figure 5. Sector Un-Protection Algorithm (A9 High-Voltage Method)
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Common Flash Memory Interface (CFI)
CFI is supported in the ES29LV160 device. The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility.
This device enters the CFI Query mode when the system writes the CFI query command, 98h, to address 55h in word mode (or address AAh in byte mode), any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 5-8. To terminate reading CFI data, the system must write the reset command.The CFI query command can be written to the system when the device is in the autoselect mode or the erase-suspend-read mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Tables 5-8. When the reset command is written, the device returns respectively to the read mode or erase-suspend-read mode.
Table 5. CFI Query Identification String
Addresses (Word Mode)
10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah
Addresses (Byte Mode)
20h 22h 24h 26h 28h 2Ah 2Ch 2Eh 30h 32h 34h
Data
0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h
Description
Query Unique ASCII string “QRY”
Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command Set(00h = none exists) Address for Alternate OEM Extended Table (00h = none exists)
Table 6. System Interface String
Addresses (Word Mode)
1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h
Addresses (Byte Mode)
36h 38h 3Ah 3Ch 3Eh 40h 42h 44h 46h 48h 4Ah 4Ch
Data
0027h 0036h 0000h 0000h 0004h 0000h 000Ah 0000h 0005h 0000h 0004h 0000h Vcc Min. (write/erase) D7-D4: volt, D3-D0: 100 millivolt Vcc Max. (write/erase) D7-D4: volt, D3-D0: 100 millivolt
Description
Vpp Min. voltage (00h = no Vpp pin present) Vpp Max. voltage (00h = no Vpp pin present) Typical timeout per single byte/word write 2N us Typical timeout for Min. size buffer write 2N us (00h = not supported) Typical timeout per individual block erase 2N ms Typical timeout for full chip erase 2N ms (00h = not supported) Max. timeout for byte/word write 2N times typical Max. timeout for buffer write 2N times typical Max. timeout per individual block erase 2N times typical Max. timeout for full chip erase 2N times typical (00h = not supported)
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Table 7. Device Geometry Definition
Addresses (Word Mode)
27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch
Addresses (Byte Mode)
4Eh 50h 52h 54h 56h 58h 5Ah 5Ch 5Eh 60h 62h 64h 66h 68h 6Ah 6Ch 6Eh 70h 72h 74h 76h 78h
Data
0015h 0002h 0000h 0000h 0000h 0004h 0000h 0000h 0040h 0000h 0001h 0000h 0020h 0000h 0000h 0000h 0080h 0000h 001Eh 0000h 0000h 0001h Device Size = 2N byte
Description
Flash Device Interface description 02 = x8, x16 Asynchronous Max. number of bytes multi-byte write = 2N (00h = not supported) Number of Erase Block Regions within device Erase Block Region 1 Information Number of identical size erase block = 0000h+1 = 1 Erase Block Region 1 Information Block size in Region 1 = 0040h * 256 byte = 16 Kbyte Erase Block Region 2 Information Number of identical size erase block = 0001h+1 =2 Erase Block Region 2 Information Block size in Region 2 = 0020h * 256 byte = 8 Kbyte Erase Block Region 3 Information Number of identical size erase block = 0000h+1 =1 Erase Block Region 3 Information Block size in Region 3 = 0080h * 256 byte = 32 Kbyte Erase Block Region 4 Information Number of identical size erase block = 001Eh+1 =31 Erase Block Region 4 Information Block size in Region 4 = 0100h * 256 byte = 64 Kbyte
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Table 8. Primary Vendor-Specific Extended Query
Addresses (Word Mode)
40h 41h 42h 43h 44h 45h
Addresses (Byte Mode)
80h 82h 84h 86h 88h 8Ah
Data
0050h 0052h 0049h 0031h 0030h 0000h
Description
Query-unique ASCII string “PRI” Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock (Bits 1-0) 0 = Required, 1 = Not required Silicon Revision Number (Bits 7-2) Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write Sector Protect 0 = Not Supported, X = Number of sectors in per group Sector Temporary Unprotect 00 = Not Supported, 01 = Supported Sector Protect/Unprotect scheme 04 = In-System Method and A9 High-Voltage Method Simultaneous Operation 00 = Not Supported Burst Mode Type 00 = Not Supported, 01 = Supported Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
46h 47h 48h 49h 4Ah 4Bh 4Ch
8Ch 8Eh 90h 92h 94h 96h 98h
0002h 0001h 0001h 0004h 0000h 0000h 0000h
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COMMAND DEFINITIONS
Writing specific address and data commands or sequences into the command register initiates device operations. Table 9 defines the valid register command sequences. Note that writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. A reset command is required to return the device to normal operation. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the AC Characteristics section for timing diagrams.
the Device Bus Operations section for more information.The Read-Only Operations table provides the read parameters, and Fig. 16 shows the timing diagram
RESET COMMAND
Writing the reset command resets the device to the read or erase-suspend-read mode. Address bits are don’t cares for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to which the system was writing to the read mode. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to which the system was writing to the read mode. If the program command sequence is written to a sector that is in the Erase Suspend mode, writing the reset command returns the device to the erase-suspend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If the device entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns the device to the erase-suspendread mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the device to the read mode (or erase-suspend-read mode if the device was in Erase-Suspend). 18
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READING ARRAY DATA
The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the erase-suspend-read mode, after which the system can read data from any non-erase-suspended sector. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See the Erase Suspend/Erase Resume Commands section for more information. The system must issue the reset command to return the device to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase operation, or if the device is in the autoselect mode. See the next section, Reset Command, for more information. See also Requirements for Reading Array Data in
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Command Definitions
Table 9. ES29LV160 Command Definitions
Command Sequence (Note 1) Read (Note 6) Reset (Note 7) Manufacturer ID Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Cycles Bus Cycles (Notes 2~5) First Addr RA XXX 555 AAA 555 AAA 555 AAA 555 AAA 555 AAA 555 AAA XXX XXX 555 AAA 555 AAA XXX XXX 55 AA Data RD F0 AA 2AA 555 2AA 555 2AA 555 2AA 555 2AA 555 2AA 555 PA XXX 2AA 555 2AA 555 55 555 AAA 555 AAA 555 AAA 555 AAA 555 AAA 555 AAA 90 X00 X01 X02 X01 X02 (SA)X02 (SA)X04 PA 4A Second Addr Data Third Addr Data Fourth Addr Data Fifth Addr Data Sixth Addr Data
1 1 4
Autoselect (Note 8)
Device ID (Top)
4
AA
55
90
C4
Device ID (Bottom) Sector Protect Verify (Note 9)
4
AA
55
90
49
4
AA
55
90
00/01
Program
4
AA
55
A0
PD
Unlock Bypass Unlock Bypass Program (Note 10) Unlock Bypass Reset (Note 11) Chip Erase
3 2 2
AA A0 90 AA
55 PD 00 55
20
Word Byte Word Byte
6
555 AAA 555 AAA
80
555 AAA 555 AAA
AA
2AA 555 2AA 555
55
555 AAA SA
10
Sector Erase Erase Suspend (Note 12) Erase Resume (Note 13) CFI Query (Note 14)
6 1 1
AA B0 30 98
55
80
AA
55
30
Word Byte
1
Legend:
X = Don’t care RA = Address of the memory location to be read. RD = Data read from location RA during read operation PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later.
PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first. SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A19-A12 uniquely select any sector.
Notes:
1. See Table 1 for description of bus operations. 2. All values are in hexadecimal. 3. Except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. 4. Data bits DQ15-DQ8 are don’t care in command sequences, except for RD and PD 5. Unless otherwise noted, address bits A19-A11 are don’t cares. 6. No unlock or command cycles required when device is in read mode. 7. The Reset command is required to return to the read mode (or to the erase-suspend-read mode if previously in Erase Suspend) when a device is in the autoselect mode, or if DQ5 goes high (while the device is providing status information). 8. The fourth cycle of the autoselect command sequence is a read cycle. Data bits DQ15-DQ8 are don’t care. See the Autoselect Command Sequence section for more information. 9. The data is 00h for an unprotected sector and 01h for a protected sector. 10. The Unlock Bypass command is required prior to the UnlockBypass Program command. 11. The Unlock Bypass Reset command is required to return to the read mode when the device is in the unlock bypass mode. 12. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation. 13. The Erase Resume command is valid only during the Erase Suspend mode. 14. Command is valid when device is ready to read array data or when device is in autoselect mode.
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AUTOSELECT COMMAND
The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected, including information about factorylocked or customer lockable version.
Identifier Code
Manufacturer ID Device ID
BYTE / WORD PROGRAM
The system may program the device by word or byte, depending on the state of the BYTE# pin. Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Table 9 shows the address and data requirements for the byte program command sequence. Note that the autoselect and CFI modes are unavailable while a programming operation is in progress.
Address
00h 01h
Data
4Ah C4h(T), 49h(B) 00 / 01
Sector Protect Verify
(SA)02h
Table 9 shows the address and data requirements. This method is an alternative to “A9 high-voltage method” shown in Table 2, which is intended for PROM programmers and requires VID on address pin A9. The autoselect command sequence may be written to an address within sector that is either in the read mode or erase-suspend-read mode. The auto-select command may not be written while the device is actively programming or erasing. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the autoselect command. The device then enters the autoselect mode. The system may read at any address any number of times without initiating another autoselect command sequence. Once after the device enters the auto-select mode, the manufacture ID code ( 4Ah ) can be accessed by one of two ways. Just one read cycle ( with A6, A1 and A0 = 0 ) can be used. Or four consecutive read cycles ( with A6 = 1 and A1, A0 = 0 ) for continuation codes (7Fh) and then another last cycle for the code (4Ah) (with A6, A1 and A0 = 0) can be used for reading the manufacturer code.
- 4Ah (one-cycle read) - 7Fh 7Fh 7Fh 7Fh 4Ah (Five-cycle read)
START
Write Program Command Sequence
Embedded Program algorithm in progress
Data Poll from System
No Verify Data? Yes No Increment Address Last Address? Yes Programming Completed
The system must write the reset command to return to the read mode (or erase-suspend-read mode if the device was previously in Erase Suspend).
Note: See Table 9 for program command sequence
Figure 6. Program Operation
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Program Status Bits : DQ7, DQ6 or RY/BY#
When the Embedded Program algorithm is complete, the device then returns to the read mode and addresses are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. Refer to the Write Operation Status section Table 10 for information on these status bits.
During the unlock-bypass mode, only the unlockbypass program and unlock-bypass reset commands are valid. To exit the unlock-bypass mode, the system must issue the two-cycle unlock-bypass reset command sequence. The first cycle must contain the data 90h. The second cycle need to only contain the data 00h. The device then returns to the read mode.
- Unlock Bypass Enter Command - Unlock Bypass Reset Command - Unlock Bypass Program Command
Any Commands Ignored during Programming Operation
Any commands written to the device during the Embedded Program algorithm are ignored. Note that a hardware reset can immediately terminates the program operation. The program command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity.
CHIP ERASE COMMAND
To erase the entire memory, a chip erase command is used. This command is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The chip erase command erases the entire memory including all other sectors except the protected sectors, but the internal erase operation is performed on a single sector base.
Programming from “0” back to “1”
Programming is allowed in any sequence and across sector boundaries. But a bit cannot be programmed from “0” back to a ”1”. Attempting to do so may cause the device to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was successful. However, a succeeding read will show that the data is still “0”. Only erase operations can convert a “0” to a “1”
Embedded Erase Algorithm
The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Table 9 shows the address and data requirements for the chip erase command sequence. Note that the autoselect, and CFI modes are unavailable while an erase operation is in progress
Unlock Bypass
In the ES29LV160 device, an unlock bypass program mode is provided for faster programming operation. In this mode, two cycles of program command sequences can be saved. To enter this mode, an unlock bypass enter command should be first written to the system. The unlock bypass enter command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device then enters the unlock-bypass program mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program set-up command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. Table 9 shows the requirements for the command sequence.
Erase Status Bits : DQ7, DQ6, DQ2, or RY/ BY#
When the Embedded Erase algorithm is complete, the device returns to the read mode and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to the Write Operation Status section Table 10 for information on these status bits.
Commands Ignored during Erase Operation
Any command written during the chip erase operation are ignored. However, note that a hardware 21
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reset immediately terminates the erase operation.If that occurs, the chip erase command sequence should be reinitiated once the device has returned to reading array data. to ensure data integrity. Fig. 7 illustrates the algorithm for the erase operation. Refer to the Erase and Program Operations tables in the AC Characteristics section for parameters, and Fig. 21 section for timing diagrams.
to the read mode. The system must rewrite the command sequence and any additional addresses and commands.
Status Bits : DQ7,DQ6,DQ2, or RY/BY#
When the Sector Erase Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. Note that while the Embedded Erase operation is in progress, the system can read data from the nonerasing sector. The system can determine the status of the erase operation by reading DQ7,DQ6,DQ2, or RY/BY# in the erasing sector. Refer to the Write Operation Status section Table 10 for information on these status bits.
SECTOR ERASE COMMAND
By using a sector erase command, a single sector or multiple sectors can be erased. The sector erase command is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. Table 9 shows the address and data requirements for the sector erase command sequence. Note that the autoselect, and CFI modes are unavailable while an erase operation is in progress.
Valid Command during Sector Erase
Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command
Embedded Sector Erase Algorithm
The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings these operations.
START
Write Erase Command Sequence (Notes 1,2)
Sector Erase Time-out Window and DQ3
After the command sequence is written, a sector erase time-out of 50us occurs. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 us, otherwise the last address and command may not be accepted, and erasure may begin. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. The system can monitor DQ3 to determine if the sector erase timer has timed out (See the section on DQ3:Sector Erase Timer.). The time-out begins from the rising edge of the final WE# pulse in the command sequence. Any command other than Sector Erase or Erase Suspend during the time-out period resets the device
Embedded Erase algorithm in progress No
Data Poll to Erasing Bank from System
No Data = FFh? Yes Erasure Completed
Notes:
1. See Table 9 for erase command sequence 2. See the section on DQ3 for information on the sector erase timer
Figure 7. Erase Operation
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sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. Fig. 7 illustrates the algorithm for the erase operation. Refer to the Erase and Program Operations tables in the AC Characteristics section for parameters, and Fig. 21 section for timing diagrams.
After an erase-suspended program operation is complete, the device returns to the erase-suspendread mode. The system can determine the status for the program operation using the DQ7 or DQ6 status bits, just as in the standard Byte Program operation. Refer to the Write Operation Status section for more information.
ERASE SUSPEND/ERASE RESUME
An erase operation is a long-time operation so that two useful commands are provided in the ES29LV160 device Erase Suspend and Erase Resume Commands. Through the two commands, erase operation can be suspended for a while and the suspended operation can be resumed later when it is required. While the erase is suspended, read or program operations can be performed by the system.
Autoselect during Erase-Suspend- Read Mode
In the erase-suspend-read mode, the system can also issue the autoselected command sequence. Refer to the Autoselect Mode and Autoselect Command Sequence section for details (Table 9).
Erase Resume Command
To resume the sector erase operation, the system must write the Erase Resume command. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the chip has resumed erasing.
Erase Suspend Command, (B0h)
The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sector erase operation, including the 50us time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. When the Erase Suspend command is written during the sector erase operation, the device requires a maximum of 20us to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the timeout period and suspends the erase operation.
Read and Program during Erase-SuspendRead Mode
After the erase operation has been suspended, the device enters the erase-suspend-read mode. The system can read data from or program data to any sector not selected for erasure. (The device “erase suspends” all sectors selected for erasure.) Reading at any address within erase-suspended sectors produces status information on DQ7-DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erasesuspended. Refer to the Write Operation Status section for information on these status bits (Table 10).
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COMMAND DIAGRAM
PA/PD Done Program
20 Unlock Bypass 90
A0 80
AA
90 55 55 Autoselect
98 AA F0 CFI F0 Done 98 Chip Erase Done Read
10
SA/30
SA/30 50us
00
Sector Erase
Resume 30
B0 Suspend
Erasesuspend Read
Figure 8. Command Diagram
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WRITE OPERATION STATUS
In the ES29LV160 device, several bits are provided to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6, DQ7 and RY/BY#. Table 10 and the following subsections describe the function of these bits. DQ7 and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress. The device also provides a hardware-based output signal, RY/ BY#, to determine whether an Embedded Program or Erase operation is in progress or has been completed.
Erase algorithm is complete, or if the device enters the Erase Suspend mode, Data# polling produces a “1” on DQ7. The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7.
Erase on the Protected Sectors
After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 1.8us, then the device returns to the read mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at an address within a protected sector, the status may not be valid.
DQ7 (DATA# POLLING)
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm is in progress or completed, or whether a device is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command sequence.
Data# Polling Algorithm
Just prior to the completion of an Embedded Program or Ease operation, DQ7 may change asynchronously with DQ0-DQ6 while Output Enable(OE#) is asserted low. That is, this device may change from providing status information to valid data on DQ7. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the program or erase operation and DQ7 has valid data, the data outputs on DQ0-DQ7 will appear on successive read cycles. Table 10 shows the outputs for Data# Polling on DQ7. Fig. 9 shows the Data# Polling algorithm. Fig. 22 in the AC Characteristics section shows the Data# Polling timing diagram.
During Programming
During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately 250ns, then the device returns to the read mode.
During Erase
During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7. When the Embedded
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START Read DQ7-DQ0 Addr = VA
DQ7 = Data ? No No DQ5 = 1 ? Yes Read DQ7-DQ0 Addr = VA
Yes
Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence ( prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. The system may use either OE# or CE# to control the read cycles. When the operation is complete, DQ6 stops toggling. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7(see the subsection on DQ7:Data# Polling). DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. Table 10 shows the outputs for Toggle Bit I on DQ6. Fig. 10 shows the toggle bit algorithm. Fig. 23 in the “AC Characteristics” section shows the toggle bit timing diagrams. Fig. 24 shows the differences between DQ2 and DQ6 in graphical form. See also the subsection on DQ2 : (Toggle Bit II).
Yes DQ7 = Data ? No FAIL PASS
Notes:
1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address in any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5
Figure 9. Data# Polling Algorithm
Toggling on the Protected Sectors
RY/BY# ( READY/BUSY# )
The RY/BY# is a dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an opendrain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to Vcc. If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is in the read mode, the standby mode, or in the erase-suspend-read mode. Table 10 shows the outputs for RY/BY#.
After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 1.8us, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. If a program address falls within a protected sector, DQ6 toggles for approximately 250ns after the program command sequence is written, then returns to reading array data.
DQ2 ( TOGGLE BIT II )
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence DQ2
DQ6 ( TOGGLE BIT I )
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the
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toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erasesuspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 10 to compare outputs for DQ2 and DQ6. Fig. 10 shows the toggle bit algorithm in flowchart form, and the section “DQ2: Toggle Bit II” explains the algorithm. See also the DQ6: Toggle Bit I subsection. Fig. 23 shows the toggle bit timing diagram. Fig. 24 shows how differently DQ2 operates compared with DQ6.
START
Read DQ7-DQ0
Read DQ7-DQ0
Toggle Bit = Toggle ? Yes No DQ5 = 1 ? Yes Read DQ7-DQ0 Twice
No
Reading Toggle Bits DQ6/DQ2
Refer to Fig. 10 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7-DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7-DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, this system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Fig. 10).
Toggle Bit = Toggle ? Yes Program/Erase Operation Not Complete, Write Reset Command
No
Program/Erase Operation Complete
Note:
The system should recheck the toggle bit even if DQ5 = “1” because the toggle bit may stop toggling as DQ5 changes to “1”. See the subsections on DQ6 and DQ2 for more information.
Figure 10. Toggle Bit Algorithm
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DQ5 ( EXCEEDED TIMING LIMITS )
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a “1”, indicating that the program or erase cycle was not successfully completed. The device may output a “1” on DQ5 if the system tries to program a “1” to a location that was previously programmed to “0” Only an erase operation can change a “0” back to a “1”. Under this condition, the device halts the operation, and when the timing limit has been exceeded, DQ5 produces a ”1”. Under both these conditions, the system must write the reset command to return to the read mode.
DQ3 ( SECTOR ERASE TIMER )
After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has begun. (The sector erase time does not apply to the chip erase command.)
If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out period is complete, DQ3 switches from a “0” to a”1”. If the time between additional sector erase commands from the system can be assumed to be less than 50us, the system need not monitor DQ3. See also the Sector Erase Command Sequence section. After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is “1”, the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until the erasure operation is complete. If DQ3 is “0”, the device will accept additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. In Table 10, DQ3 status operation is well defined and summarized with other status bits, DQ7, DQ6, DQ5, and DQ2.
Table 10. Write Operation Status
Status
Standard Mode Embedded Program Algorithm Embedded Erase Algorithm Erase Suspended Sector Non-Erase Suspended Sector
DQ7 (Note 2)
DQ7# 0 1 Data DQ7#
DQ6
Toggle Toggle No toggle Data Toggle
DQ5 (Note 1)
0 0 0 Data 0
DQ3
N/A 1 N/A Data N/A
DQ2 (Note 2)
No toggle Toggle Toggle Data N/A
RY/ BY#
0 0 1 1 0
Erase Suspend Mode
Erase-SuspendRead
Erase-Suspend-Program
Notes :
1. DQ5 switches to “1” when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to the section on DQ5 for more information. 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
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ABSOLUTE MAXIMUM RATINGS
Storage Temperature Plastic Packages ..............................................-65oC to +150oC
20ns +0.8V Vss-0.5V
20ns
Ambient Temperature with Power Applied ...........................................-65oC to +125oC
Vss-2.0V 20ns
Voltage with Respect to Ground
Vcc (Note 1) ..........................................................-0.5V to +4.0V A9, OE# and RESET# (Note 2) ........................-0.5V to +12.5V All other pins (Note 1) ...................................-0.5V to Vcc + 0.5V
Negative Overshoot
Output Short Circuit Current (Note 3) ................. 200 mA Notes:
1. Minimum DC voltage on input or I/O pins is -0.5V. During voltage transitions, input or I/O pins may overshoot Vss to -2.0V for periods of up to 20ns. Maximum DC voltage on input or I/O pins is Vcc+0.5V. See Fig. 11. During voltage transition, input or I/O pins may overshoot to Vcc+2.0V for periods up to 20ns. See Fig. 11. 2. Minimum DC input voltage on pins A9, OE# and RESET# is -0.5V . During voltage transitions, A9, OE# and RESET# may overshoot Vss to -2.0V for periods of up to 20ns. See Fig. 11. Maximum DC input voltage on pin A9 is +12.5V which may overshoot to +14.0V for periods up to 20ns. 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this datasheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.
20ns Vcc+2.0V
20ns
Vcc+0.5V 2.0V 20ns
Positive Overshoot
Figure 11. Maximum Overshoot Waveform
OPERATING RANGES
Industrial (I) Devices Ambient Temperature (TA).................................-40oC to +85oC Commercial Devices Ambient Temperature (TA)....................................0oC to +70oC Vcc Supply Voltages Vcc for all devices ............................................2.7V to 3.6V Vcc for regulated voltage range ........................3.0V to 3.6V Operating ranges define those limits between which the functionality of the device is guaranteed.
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DC CHARACTERISTICS
Table 11. CMOS Compatible
Parameter Symbol
ILI ILIT ILR ILO
Parameter Description
Input Load Current
Test Conditions
VIN=Vss to Vcc Vcc=Vcc max Vcc=Vcc max; A9=12.5V Vcc=Vcc max; RESET#=12.5V Vout=Vss to Vcc, Vcc=Vcc max 5MHz
Min
Typ
Max
+ 1.0
Unit
uA
A9 Input Load Current RESET# Input Load Current Output Leakage Current
35 35 + 1.0 9 2 9 2 15 0.2 0.2 0.2 16 4
uA uA uA
ICCI
Vcc Active Read Current (Notes 1,2)
CE#=VIL OE#=VIH, Byte mode CE#=VIL, OE#=VIH, Word mode
1MHz 5MHz 1MHz
mA 16 4 30 10 10 10 mA uA uA uA
ICC2 ICC3 ICC4 ICC5 VIL VIH VID VOL VOH1
Vcc Active Write Current (Note 2,3) Vcc Standby Current (Note 2) Vcc Reset Current (Note 2) Automatic Sleep Mode (Notes2,4) Input Low Voltage Input High Voltage Voltage for Autoselect and Temporary Sector Unprotect Output Low Voltage
CE#=VIL, OE#=VIH, WE#=VIL CE#, RESET#= Vcc+0.3V RESET#=Vss + 0.3V VIH = Vcc + 0.3V VIL = Vss + 0.3V -0.5 0.7xVcc Vcc = 3.0V + 10% IOL = 4.0 mA, Vcc = Vcc min IOH = -2.0mA, Vcc = Vcc min 0.85 Vcc 11.5
0.8 Vcc+0.3 12.5 0.45
V V V V
Output High Voltage VOH2 VLKO Low Vcc Lock-Out Voltage (Note 5) IOH = -100 uA, Vcc = Vcc min Vcc - 0.4 2.3 2.5
V V
Notes:
1. The Icc current listed is typically less than 2 mA/MHz, with OE# at VIH , Typical condition : 25oC, Vcc = 3V 2. Maximum ICC specifications are tested with Vcc = Vcc max. 3. Icc active while Embedded Erase or Embedded Program is in progress. 4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30ns. Typical sleep mode current is 200 nA. 5. Not 100% tested.
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DC CHARACTERISTICS
Zero-Power Flash
25
Icc1 (Active Read current)
Supply Current in mA 20
Icc5 (Automatic Sleep Mode)
15
10
5
0
500
1000
1500
2000 Time in ns
2500
3000
3500
4000
Note: Addresses are switching at 1 MHz
Figure 12. Icc1 Current vs. Time (Showing Active and Automatic Sleep Currents)
12 3.6V 10
2.7V 8 Supply Current in mA
6
4
2
0 1 2 3 Frequency in MHz 4 5
Note: T = 25oC
Figure 13. Typical Icc1 vs. Frequency
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3.3V
Table 12. Test Specifications
2.7kΩ
Device Under Test Test Condition
Output Load
70R
90
1TTL gate
120
CL
6.2kΩ
Output Load Capacitance, CL (including jig capacitance) Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels
30 pF
30 pF
100 pF
5 ns 0.0 - 3.0 V 1.5 V 1.5 V
Figure 14. Test Setup
Note: Diodes are IN3064 or equivalent
Output timing measurement reference levels
Key To Switching Waveforms
WAVEFORM INPUTS
Steady Changing from H to L Changing from L to H Don’t Care, Any Change Permitted Does Not Apply Changing, State Unknown Center Line is High Impedance State (High Z)
OUTPUTS
3.0V Input 0.0V 1.5V Measurement Level 1.5V Output
Figure 15. Input Waveforms and Measurement Levels
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AC CHARACTERISTICS
Table 13. Read-Only Operations
Parameter JEDEC Std.
tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX tRC tACC tCE tOE tDF tDF tOH tOEH
Speed Options Description
Read Cycle Time(Note 1) Address to Output Delay Chip Enable to Output Delay Output Enable to Output Delay Chip Enable to Output High Z (Note 1) Output Enable to Output High Z (Note 1) Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First Output Enable Hold Time (Note 1) Read Toggle and Data# Polling CE#,OE#=VIL OE#=VIL
Unit
Test Setup
Min Max Max Max Max Max Min Min Min
70R
70 70 70 35
90
90 90 90 40 16 16 0 0 10
120
120 120 120 50 ns ns ns ns ns ns ns ns ns
Note : 1. Not 100% tested
tRC Address Address Stable tACC CE# tRH tRH tOE OE# tOEH WE# tCE tOH OUTPUTS High-Z High-Z Output Valid tDF
RESET#
RY/BY#
0V
Figure 16. Read Operation Timings
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AC CHARACTERISTICS
Table 14. Hardware Reset ( RESET #)
Parameter JEDEC Std.
tReady tReady tRP tRH tRPD tRB
Description
RESET# Pin Low (During Embedded Algorithms) to Read Mode (See Note) RESET# Pin Low (Not During Embedded Algorithms) to Read Mode (See Note) RESET# Pulse Width RESET High Time Before Read (See Note) RESET# Low to Standby Mode RY/BY# Recovery Time Max Max Min Min Min Min
All Speed Options
20 500 500 50 20 0
Unit
us ns ns ns us ns
Note : Not 100% tested
RY/BY#
0V
CE#,OE# tRH RESET# tRP tREADY
(A) Not During Embedded Algorithm
tREADY RY/BY# tRB
CE#,OE#
RESET# tRP
(B) During Embedded Algorithm
Figure 17. Reset Timings
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AC CHARACTERISTICS
Table 15. Word/Byte Configuration (BYTE#)
Parameter JEDEC Std.
tELFL/tELFH tFLQZ tFHQV
Description
CE# to BYTE# Switching Low or High BYTE# Switching Low to Output HIGH Z BYTE# Switching High to Output Active Max Max Min
70R
90
5 30
120
Unit
ns ns
70
90
120
ns
CE#
OE#
BYTE# tELFL
BYTE# Switching Switching from word to byte mode
DQ0-DQ14
Data Output (DQ0-DQ14) DQ15 Output
Data Output (DQ0-DQ7) Address Input
DQ15/A-1
tELFH
tFLQZ
BYTE#
BYTE# Switching Switching from byte to word mode
DQ0-DQ14
Data Output (DQ0-DQ7) Address Input
Data Output (DQ0-DQ14) DQ15 Output
DQ15/A-1
tFHQV
Figure 18. BYTE# Timing for Read Operations
CE#
The falling edge of the last WE# signal
WE#
BYTE#
tSET (tAS)
tHOLD (tAH)
Note : Refer to the Erase/Program Operations table for tAS and tAH specifications.
Figure 19. BYTE# Timing for Write Operations
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AC CHARACTERISTICS
Table 16. Erase and Program Operations
Parameter JEDEC
tAVAV tAVWL
Std.
tWC tAS tASO Write Cycle Time (Note 1) Address Setup Time
Description
Min Min Min Min Min Min Min Min Min Min Min Min Min Min Typ Typ Typ Min Min Max
70R
70
90
90 0 15
120
120
Unit
ns ns ns
Address Setup Time to OE# low during toggle bit polling Address Hold Time Address Hold Time From CE# or OE# high during toggle bit polling Data Setup Time Data Hold Time Output Enable High during toggle bit polling Read Recovery Time Before Write (OE# High to WE# Low) CE# Setup Time CE# Hold Time Write Pulse Width Write Pulse Width High Latency Between Read and Write Operations Byte
tWLAX
tAH tAHT
45
45 0
50
ns ns
tDVWH tWHDX
tDS tDH tOEPH
35
45 0 20 0 0 0
50
ns ns ns ns ns ns
tGHWL tELWL tWHEH tWLWH tWHDL
tGHWL tCS tCH tWP tWPH tSR/W
35
35 30 0 6 8 0.7 50 0 90
50
ns ns ns
tWHWH1 tWHWH2
tWHWH1 tWHWH2 tVCS tRB tBUSY
Programming Operation (Note 2) Sector Erase Operation (Note 2) Vcc Setup Time (Note 1) Write Recovery Time from RY/BY#
Word
us sec us ns ns
Program/Erase Valid to RY/BY# Delay
Notes:
1. Not 100% tested. 2. See the “Erase And Programming Performance” section for more information.
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AC CHARACTERISTICS
Program Command Sequence (last two cycles)
Read Status Data(last two cycles)
tWC Address 555h
tAS PA tAH PA PA
CE# tCH OE# tCS tWP WE# tWPH tDS tDH A0h PD tBUSY RY/BY# tVCS Status Dout tRB tWHWH1
DATA
Vcc
NOTES :
1. PA = program address, PD = program data, Dout is the true data at the program address. 2. Illustration shows device in word mode.
Figure 20. Program Operation Timings
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AC CHARACTERISTICS
Erase Command Sequence (last two cycles)
Read Status Data
tWC Address 2AAh
tAS SA
555h for chip erase
tAH VA VA
CE# tCH OE# tCS tWP WE# tWPH tDS tDH
10h for chip erase
tWHWH2
DATA
55h
30h tBUSY
In Progress
Complete
tRB
RY/BY#
tVCS
Vcc
NOTES :
1. SA = sector address(for Sector Erase), VA = valid address for reading status data(see “Write Operation Status”). 2. These waveforms are for the word mode.
Figure 21. Chip/Sector Erase Operation Timings
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AC CHARACTERISTICS
tRC Address VA tACC tCE CE# tCH OE# tOEH tDF tOE VA VA
WE# DQ7 DQ0-DQ6 tBUSY RY/BY#
tOH
HIGH-Z
Complement Complement True Valid Data
HIGH-Z
Status Data Status Data True Valid Data
NOTE : VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle
Figure 22. Data# Polling Timings (During Embedded Algorithms)
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AC CHARACTERISTICS
tAHT Address tASO CE# tOEH WE# tOEPH OE# tDH DQ6/DQ2 RY/BY#
Valid Data Valid Status
tAS
tAHT
tCEPH
tOE
Valid Status Valid Status Valid Data
(first read)
(second read)
(stops toggling)
NOTE : VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read
cycle, and array data read cycle.
Figure 23. Toggle Bit Timings (During Embedded Algorithms)
Enter Embedded Erasing
Enter Suspend
Enter Erase Suspend Program Erase Suspend Program
Erase Resume
WE#
Erase Erase Suspend Read Erase Suspend Read Erase Erase Complete
DQ6 DQ2
NOTE : DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle DQ2 and DQ6.
Figure 24. DQ2 vs. DQ6
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AC CHARACTERISTICS
Table 17. Temporary Sector Unprotect
Parameter JEDEC Std.
tVIDR tRSP tRRB
Description
VID Rise and Fall Time (See Note) RESET# Setup Time for Temporary Sector Unprotect RESET# Hold Time from RY/BY# High for Temporary Sector Unprotect Min Min Min
All Speed Options
500 4 4
Unit
ns us us
Note: Not 100% tested.
VID
RESET#
Vss,VIL, or VIH
tVIDR
Program or Erase Command Sequence
tVIDR
CE#
WE# tRSP RY/BY# tRRB
Figure 25. Temporary Sector Unprotect Timing Diagram
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AC CHARACTERISTICS
VID VIH RESET#
SA,A6, A1,A0 DQ 60h
1us
Valid* Sector Protect or Unprotect
Valid*
Valid*
Verify
60h
Sector Protect : 150us, Sector Unprotect: 15ms
40h
Status
CE#
WE# OE#
* For sector protect, A6=0,A1=1,A0=0 For sector unprotect, A6=1,A1=1,A0=0
Figure 26. Sector Protect & Unprotect Timing Diagram
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AC CHARACTERISTICS
Table 18. Alternate CE# Controlled Erase and Program Operations
Parameter JEDEC
tAVAV tAVWL tELAX tDVEH tEHDX tGHEL tWLEL tEHWH tELEH tELEL tWHWH1 tWHWH2
Std.
tWC tAS tAH tDS tDH tGHEL tWS tWH tCP tCPH tWHWH1 tWHWH2
Description
Write Cycle Time( Note 1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Read Recovery Time Before Write (OE# High to WE# Low) WE# Setup Time WE# Hold Time CE# Pulse Width CE# Pulse Width High Byte Programming Operation (Note 2) Sector Erase Operation (Note 2) Word Min Min Min Min Min Min Min Min Min Min Typ Typ Typ
70R
70
90
90 0
120
120
Unit
ns ns
45 35
45 45 0 0 0 0
50 50
ns ns ns ns ns ns
35
35 30 6 8 0.7
50
ns ns
us sec
Notes :
1. Not 100% tested 2. See the “Erase And Programming Performance” section for more information.
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AC CHARACTERISTICS
555 for program 2AA for erase
PD for program SA for sector erase 555 for chip erase
Data Polling
Address tWC WE# tGHEL OE# tCP CE# tWS tDS DATA tRH RESET# RY/BY#
A0 for program 55 for erase PD for program 30 for sector erase 10 for chip erase
PA tAS tWH tAH
tWHWH1 or 2 tCPH tDH
DQ7# DOUT
tBUSY
NOTES :
1. Figure indicates last two bus cycles of a program or erase operation. 2. PA = program address, SA = sector address, PD = program data 3. DQ7# is the complement of the data written to the device. Dout is the data written to the device. 4. Waveforms are for the word mode.
Figure 27. Alternate CE# Controlled Write(Erase/Program) Operation Timings
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Table 19. AC CHARACTERISTICS
Parameter
tOE tVIDR tWPP1 tWPP2 tOESP tCSP tST
Description
Output Enable to Output Delay Voltage Transition Time Write Pulse Width for Protection Operation Write Pulse Width for Unprotection Operation OE# Setup Time to WE# Active CE# Setup Time to WE# Active Voltage Setup Time Max Min Min Min Min Min Min
Value
35/40/50 500 150 15 4 4 4
Unit
ns ns us ms us us us
A A A A tVIDR VID A tST VID OE# tOESP tWPP1
SAx
SAy
tVIDR
WE# tCSP CE# DQ RESET# Vcc
tST
tOE
0x01
Figure 28. Sector Protection timings (A9 High-Voltage Method)
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AC CHARACTERISTICS
A A A A tVIDR VID A tST VID OE# tOESP tWPP2 tST tCSP CE# DQ RESET# Vcc tOE tVIDR
SA0
SA1
WE#
0x00
NOTE : It is recommended to verify for all sectors.
Figure 29. Sector Unprotection timings (A9 High-Voltage Method)
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Table 20. ERASE AND PROGRAMMING PERFORMANCE
Parameter
Sector Erase Time Chip Erase Time Byte Program Time Word Program Time Byte Mode Chip Program Time (Note 3) Word Mode
Typ (Note 1)
0.7 25 6 8 12.6 8.4
Max (Note 2)
15
Unit
sec sec
Comments
Excludes 00h programming prior to erasure (Note 4)
150 210 37.8 25.2
us us sec Exclude system level overhead (Note 5)
Notes:
1. Typical program and erase times assume the following conditions: 25oC, 3.0V Vcc, 10,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90oC, Vcc = 2.7V, 100,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two-or-four-bus-cycle sequence for the program command. See Table 9 for further information on command definitions. 6. The device has a minimum erase and program cycle endurance of 100,000 cycles.
Table 21. LATCHUP CHARACTERISTICS
Description
Input voltage with respect to Vss on all pins except I/O pins (including A9, OE#, and RESET#) Input voltage with respect to Vss on all I/O pins Vcc Current - 1.0V - 1.0V - 100 mA
Min
12.5 V
Max
Vcc + 1.0 V +100 mA
Note: Includes all pins except Vcc. Test conditions: Vcc = 3.0 V, one pin at a time
Table 22. TSOP, SO, AND BGA PACKAGE CAPACITANCE
Parameter Symbol
CIN
Parameter Description
Input Capacitance VIN = 0
Test Setup
TSOP FBGA TSOP
Typ
6 4.2 8.5 5.4 7.5 3.9
Max
7.5 5.0 12 6.5 9 4.7
Unit
pF pF pF pF pF pF
COUT
Output Capacitance
VOUT = 0
FBGA TSOP
CIN2
Control Pin Capacitance
VIN = 0
FBGA
Notes:
1. Sampled, not 100% tested. 2. Test conditions TA = 25oC, f=1.0MHz.
Table 23. DATA RETENTION
Parameter Description
Minimum Pattern Data Retention Time 125oC 20 Years
Test conditions
150o C
Min
10
Unit
Years
ES29LV160D
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Rev. 1C Jan 5 , 2006
E S II ES
Excel Semiconductor inc.
PHYSICAL DIMENSIONS 48-Pin Standard TSOP (measured in millimeters)
0.10 C
2
1 -AE5
A2
SEE DETAIL B
N
-B-
e
N --2
9
N+1 --2
D1 D
5 4
A1 -CSEATING PLANE
0.08MM (0.0031”) M C A-B S
B A B
b
67
WITH PLATING c1 BASE METAL
SEE DETAIL A
7
(c)
b1 R c GAUGE PLANE
SECTION B-B
PARALLEL TO SEATING PLANE
θ°
L
0.25MM (0.0098”) BSC
e/2
-X-
DETAIL A DETAIL B
Package JEDEC Symbol A A1 A2 b1 b c1 c D D1 E e L 0.50 MIN 0.05 0.95 0.17 0.17 0.10 0.10 19.80 18.30 11.90 TS 48 MO-142 (B) DD NOM 1.00 0.20 0.22 20.00 18.40 12.00 0.50 BASIC 0.60 0.70 MAX 1.20 0.15 1.05 0.23 0.27 0.16 0.21 20.20 18.50 12.10
X = A OR B
NOTES:
1. Controlling dimensions are in millimeters(mm). (Dimensioning and tolerancing conforms to ANSI Y14.5M-1982) 2. Pin 1 identifier for standard pin out (Die up). 3. Pin 1 identifier for reverse pin out (Die down): Ink or Laser mark 4. To be determined at the seating plane. The seating plane is defined as the plane of contact that is made when the package leads are allowed to rest freely on a flat horizontal surface. 5. Dimension D1 and E do not include mold protrusion. Allowable mold protrusion is 0.15mm (0.0059”) per side. 6. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.0031”) total in excess of b dimension at max. material condition. Minimum space between protrusion and an adjacent lead to be 0.07mm (0.0028”). 7. These dimensions apply to the flat section of the lead between 0.10mm (0.0039”) and 0.25mm (0.0098”) from the lead tip. 8. Lead coplanarity shall be within 0.10mm (0.004”) as measured from the seating plane. 9. Dimension “e” is measured at the centerline of the leads.
θ
R N
0°
0.08 -
3°
5°
0.20
48
ES29LV160D
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Rev. 1C Jan 5 , 2006
E S II ES
Excel Semiconductor inc.
PHYSICAL DIMENSIONS 48-Ball FBGA (6 x 8 mm)
0.20 (4x)
D
A
D1
H 6
GF
E
D
C
B
A
7
5
e
E
SE
4
E1
3 2 1
6 A1 CORNER INDEX MARK 11 B
b
0.15 M Z A B 0.08 M Z
SD
7 PIN 1 ID.
10
// 0.25 Z A2 A
0.08 Z
A1
Z
PACKAGE JEDEC SYMBOL A A1 A2 D E D1 E1 MD ME N b e SD / SE 0.30 0.21 0.7 MIN
xFBD 048 N/A 6.00 mm x8.00 mm PACKAGE NOM MAX 1.10 0.25 0.76 8.00 BSC 6.00 BSC 5.60 BSC 4.00 BSC 8 6 48 0.35 0.40 0.80 BSC 0.40 BSC 0.29 0.82 NOTE OVERALL THICK NESS BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE BALL FOOTPRINT BALL FOOTPRINT ROW MATRIX SIZED DIRECTION ROW MATRIX SIZED DIRECTION TOTAL BALL COUNT BALL DIAMETER BALL PITCH SOLDER BALL PLACEMENT
NOTES: 1. Dimensioning and tolerancing per ASME Y14.5M-1994 2. All dimensions are in millimeters. 3. Ball position designation per JESD 95-1, SPP-010. 4. e represents the solder ball grid pitch. 5. Symbol “MD” is the ball row matrix size in the “D” direction. Symbol “ME” is the ball column matrix size in the “E” direction. N is the maximum number of solder balls for matrix size MD X ME. 6. Dimension “b” is measured at the maximum ball diameter in a plane parallel to datum Z. 7. SD and SE are measured with respect to datums A and B and define the position of the center solder ball in the outer row. When there is an odd number of solder balls in the outer row parallel to the D or E dimension, respectively, SD or SE = 0.000 when there is an even number of solder balls in the outer row, SD or SE = e/2 8. “X” in the package variations denotes part is outer qualification. 9. “+” in the package drawing indicate the theoretical center of depopulated balls. 10. For package thickness A is the controlling dimension. 11. A1 corner to be indentified by chamfer, ink mark, metallized markings indention or other means.
ES29LV160D
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Excel Semiconductor inc.
ORDERNG INFORMATION
Standard Products
ESI standard products are available in several package and operating ranges. The order number (Valid Combination) is formed by a combination of the following:
ES
29
LV
160 X
X - XX
X
XXX
TEMPERATURE RANGE
Blank : Commercial (0oC to + 70oC) I : Industrial (- 40oC to + 85oC)
Pb-free
C G : : Pb product Pb-free product
PACKAGE TYPE
T : Standard TSOP (48-pin), W : FBGA(48-ball)
VOLTAGE RANGE
Blank : 2.7 ~ 3.6V R : 3.0 ~ 3.6V
SPEED OPTION
70 : 70ns 80 : 80ns 90 : 90ns 12 : 120ns
SECTOR ARCHITECTURE
Blank : Uniform sector T : Top sector B : Bottom sector
TECHNOLOGY
D : 0.18um E : 0.15um F : 0.13um
DENSITY & ORGANIZATION
400 : 4M ( x8 / x16) 160 : 16M ( x8 / x16) 640 : 64M ( x8 / x16) 800 : 8M ( x8 / x16) 320 : 32M ( x8 / x16)
POWER SUPPLY AND INTERFACE
F : 5.0V LV : 3.0V DL : 3.0V, Dual Bank DS : 1.8V, Dual Bank BDS : 1.8V, Burst mode, Dual Bank
COMPONENT GROUP
29 : Flash Memory
EXCEL SEMICONDUCTOR
ES29LV160D
50
Rev. 1C Jan 5 , 2006
E S II ES
Excel Semiconductor inc.
Product Selection Guide
Industrial Device
Part No.
ES29LV160DT-70RTGI ES29LV160DT-70RTCI ES29LV160DB-70RTGI ES29LV160DB-70RTCI ES29LV160DT-90TGI ES29LV160DT-90TCI ES29LV160DB-90TGI ES29LV160DB-90TCI ES29LV160DT-12TGI ES29LV160DT-12TCI ES29LV160DB-12TGI ES29LV160DB-12TCI
Speed Vcc
70ns 70ns 70ns 70ns 90ns 90ns 90ns 90ns 120ns 120ns 120ns 120ns 3.0 - 3.6V 3.0 - 3.6V 3.0 - 3.6V 3.0 - 3.6V 2.7 - 3.6V 2.7 - 3.6V 2.7 - 3.6V 2.7 - 3.6V 2.7 - 3.6V 2.7 - 3.6V 2.7 - 3.6V 2.7 - 3.6V
Boot Sector Package
Top Top Bottom Bottom Top Top Bottom Bottom Top Top Bottom Bottom 48-pin TSOP 48-pin TSOP 48-pin TSOP 48-pin TSOP 48-pin TSOP 48-pin TSOP 48-pin TSOP 48-pin TSOP 48-pin TSOP 48-pin TSOP 48-pin TSOP 48-pin TSOP
Pb
Pb-free Pb-free Pb-free Pb-free Pb-free Pb-free -
Ball Pitch/Size
Body Size
ES29LV160DT-70RWGI ES29LV160DT-70RWCI ES29LV160DB-70RWGI ES29LV160DB-70RWCI ES29LV160DT-90WGI ES29LV160DT-90WCI ES29LV160DB-90WGI ES29LV160DB-90WCI ES29LV160DT-12WGI ES29LV160DT-12WCI ES29LV160DB-12WGI ES29LV160DB-12WCI
70ns 70ns 70ns 70ns 90ns 90ns 90ns 90ns 120ns 120ns 120ns 120ns
3.0 - 3.6V 3.0 - 3.6V 3.0 - 3.6V 3.0 - 3.6V 2.7 - 3.6V 2.7 - 3.6V 2.7 - 3.6V 2.7 - 3.6V 2.7 - 3.6V 2.7 - 3.6V 2.7 - 3.6V 2.7 - 3.6V
Top Top Bottom Bottom Top Top Bottom Bottom Top Top Bottom Bottom
48-Ball FBGA 48-Ball FBGA 48-Ball FBGA 48-Ball FBGA 48-Ball FBGA 48-Ball FBGA 48-Ball FBGA 48-Ball FBGA 48-Ball FBGA 48-Ball FBGA 48-Ball FBGA 48-Ball FBGA
Pb-free Pb-free Pb-free Pb-free Pb-free Pb-free -
0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.3mm
6mm x 8mm 6mm x 8mm 6mm x 8mm 6mm x 8mm 6mm x 8mm 6mm x 8mm 6mm x 8mm 6mm x 8mm 6mm x 8mm 6mm x 8mm 6mm x 8mm 6mm x 8mm
ES29LV160D
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Rev. 1C Jan 5 , 2006
E S II ES
Excel Semiconductor inc.
Product Selection Guide
Commercial Device
Part No.
ES29LV160DT-70RTG ES29LV160DT-70RTC ES29LV160DB-70RTG ES29LV160DB-70RTC ES29LV160DT-90TG ES29LV160DT-90TC ES29LV160DB-90TG ES29LV160DB-90TC ES29LV160DT-12TG ES29LV160DT-12TC ES29LV160DB-12TG ES29LV160DB-12TC
Speed Vcc
70ns 70ns 70ns 70ns 90ns 90ns 90ns 90ns 120ns 120ns 120ns 120ns 3.0 - 3.6V 3.0 - 3.6V 3.0 - 3.6V 3.0 - 3.6V 2.7 - 3.6V 2.7 - 3.6V 2.7 - 3.6V 2.7 - 3.6V 2.7 - 3.6V 2.7 - 3.6V 2.7 - 3.6V 2.7 - 3.6V
Boot Sector Package
Top Top Bottom Bottom Top Top Bottom Bottom Top Top Bottom Bottom 48-pin TSOP 48-pin TSOP 48-pin TSOP 48-pin TSOP 48-pin TSOP 48-pin TSOP 48-pin TSOP 48-pin TSOP 48-pin TSOP 48-pin TSOP 48-pin TSOP 48-pin TSOP
Pb
Pb-free Pb-free Pb-free Pb-free Pb-free Pb-free -
Ball Pitch/Size
Body Size
ES29LV160DT-70RWG ES29LV160DT-70RWC ES29LV160DB-70RWG ES29LV160DB-70RWC ES29LV160DT-90WG ES29LV160DT-90WC ES29LV160DB-90WG ES29LV160DB-90WC ES29LV160DT-12WG ES29LV160DT-12WC ES29LV160DB-12WG ES29LV160DB-12WC
70ns 70ns 70ns 70ns 90ns 90ns 90ns 90ns 120ns 120ns 120ns 120ns
3.0 - 3.6V 3.0 - 3.6V 3.0 - 3.6V 3.0 - 3.6V 2.7 - 3.6V 2.7 - 3.6V 2.7 - 3.6V 2.7 - 3.6V 2.7 - 3.6V 2.7 - 3.6V 2.7 - 3.6V 2.7 - 3.6V
Top Top Bottom Bottom Top Top Bottom Bottom Top Top Bottom Bottom
48-Ball FBGA 48-Ball FBGA 48-Ball FBGA 48-Ball FBGA 48-Ball FBGA 48-Ball FBGA 48-Ball FBGA 48-Ball FBGA 48-Ball FBGA 48-Ball FBGA 48-Ball FBGA 48-Ball FBGA
Pb-free Pb-free Pb-free Pb-free Pb-free Pb-free -
0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.3mm
6mm x 8mm 6mm x 8mm 6mm x 8mm 6mm x 8mm 6mm x 8mm 6mm x 8mm 6mm x 8mm 6mm x 8mm 6mm x 8mm 6mm x 8mm 6mm x 8mm 6mm x 8mm
ES29LV160D
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Rev. 1C Jan 5 , 2006
E S II ES
Excel Semiconductor inc.
Document Title
16M Flash Memory
Revision History
Revision Number Rev. 0A Data Mar. 15, 2004 Initial Release Version. 1. The bias condtion of RESET# in Table 1 for A9 high-Voltage method is changed from VID to H. Rev. 0B Apr. 23, 2004 2. The bias condition of A9 in Table 1 for A9 high-Voltage method is added. 3. The typical byte and word program time are changed from 5us/ 7us to 6us/8us. 4. The dimension of FBGA is changed from 8 x 9mm to 6 x 8mm Rev. 0C May. 21, 2004 1. 80R product is removed and 70R product is newly added. 1. The preliminary is removed from the datasheet. 2. The 44 pin SO is removed. 3. The Icc3 (max) is changed from 5uA to 10uA. 4. The Icc4 (max) is changed from 5uA to 10uA. Rev. 1A Dec. 1, 2004 5. The Icc5 (max) is changed from 5uA to 10uA. 6. The overall thickness of FBGA , A (max), is changed from 1.20 to 1.10. Therefore, ball height (A1) and body thickness (A2) also is changed accordingly. 7. The ball diameter of FBGA, b(min), b(nom), b(max), is changed from 0.25, 0.30, and 0.35 to 0.30, 0.35, and 0.40 respectively. 1. The arrow from Erase Suspend Read to Read is changed to Rev. 1B Dec. 13, 2004 Sector Erase. 2. VLKO(min), 2.3V is added Items
ES29LV160D
53
Rev. 1C Jan 5 , 2006
E S II ES
Excel Semiconductor inc.
Document Title
16M Flash Memory
Revision History
Revision Number Rev. 1C Data Jan. 5, 2006 Items Add RoHS-Compliant Package Option.
Excel Semiconductor Inc.
1010 Keumkang Hightech Valley, Sangdaewon1-Dong 133-1, Jungwon-Gu, Seongnam-Si, Kyongki-Do, Rep. of Korea. Zip Code : 462-807 Tel : +82-31-777-5060 Fax : +82-31-740-3798 / Homepage : www.excelsemi.com
The attached datasheets are provided by Excel Semiconductor.inc (ESI). ESI reserves the right to change the specifications and products. ESI will answer to your questions about device. If you have any questions, please contact the ESI office.
ES29LV160D
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Rev. 1C Jan 5 , 2006
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