100301QC

100301 Low Power Triple 5-Input OR/NOR Gate August 1989 Revised August 2000 100301 Low Power Triple 5-Input OR/NOR Gate General Description The 100301 is a monolithic triple 5-input OR/NOR gate. All inputs have 50 kΩ pull-down resistors and all outputs are buffered. Features s 23% power reduction of the 100101 s 2000V ESD protection s Pin/function compatible with 100101 s Voltage compensated operating range = −4.2V to −5.7V s Available to industrial grade temperature range (PLCC package only) Ordering Code: Order Number 100301SC 100301PC 100301QC 100301QI Package Number M24B N24E V28A V28A Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Industrial Temperature Range (−40°C to +85°C) Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagrams 24-Pin DIP/SOIC 28-Pin PLCC Pin Descriptions Pin Names Dna, Dnb, Dnc Oa, Ob, Oc Oa, Ob, Oc Data Inputs Data Outputs Complementary Data Outputs Description © 2000 Fairchild Semiconductor Corporation DS010579 www.fairchildsemi.com 100301 Truth Table Inputs D1a, D1b, D1c L L L L L L L L L L L L L L L L H H H H H H H H H H H H H H H H H = HIGH Voltage Level L = LOW Voltage Level Outputs D4a, D4b, D4c L L H H L L H H L L H H L L H H L L H H L L H H L L H H L L H H D5a, D5b, D5c L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H Oa, Ob, Oc L H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H Oa, Ob, Oc H L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L D2a, D2b, D2c L L L L L L L L H H H H H H H H L L L L L L L L H H H H H H H H D3a, D3b, D3c L L L L H H H H L L L L H H H H L L L L H H H H L L L L H H H H www.fairchildsemi.com 2 100301 Absolute Maximum Ratings(Note 1) Storage Temperature (TSTG) Maximum Junction Temperature (TJ) VEE Pin Potential to Ground Pin Input Voltage (DC) Output Current (DC Output HIGH) ESD (Note 2) −65°C to +150°C +150°C −7.0V to +0.5V VEE to +0.5V Recommended Operating Conditions Case Temperature (TC) Commercial Industrial Supply Voltage (VEE) 0°C to +85°C −40°C to +85°C −5.7V to −4.2V −50 mA ≥2000V Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The “recommended Operating Conditions” table will define the conditions for actual device operation. Note 2: ESD testing conforms to MIL-STD-883, Method 3015. Commercial Version DC Electrical Characteristics (Note 3) VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = 0°C to +85°C Symbol VOH VOL VOHC VOLC VIH VIL IIL IIH IEE Parameter Output HIGH Voltage Output LOW Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input LOW Current Input HIGH Current Power Supply Current −29 −17 −1165 −1830 0.50 240 −15 Min −1025 −1830 −1035 −1610 −870 −1475 Typ −955 −1705 Max −870 −1620 Units mV mV mV mV mV mV µA µA mA Conditions VIN = VIH(Max) or VIL(Min) VIN = VIH(Min) or VIL(Max) Guaranteed HIGH Signal for All Inputs Guaranteed LOW Signal for All Inputs VIN = VIL(Min) VIN = VIH(Max) Inputs OPEN Loading with 50Ω to −2.0V Loading with 50Ω to −2.0V Note 3: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions. DIP AC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND Symbol tPLH tPHL tTLH tTHL Parameter Propagation Delay Data to Output Transition Time 20% to 80%, 80% to 20% TC = 0°C Min 0.50 0.40 Max 1.10 1.20 TC = +25°C Min 0.50 0.40 Max 1.15 1.20 TC = +85°C Min 0.50 0.40 Max 1.20 1.20 ns ns Figures 1, 2 (Note 4) Figures 1, 2 Units Conditions Note 4: The propagation delay specified is for single output switching. Delays may vary up to 100 ps with multiple outputs switching. 3 www.fairchildsemi.com 100301 Commercial Version (Continued) SOIC and PLCC AC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND Symbol tPLH tPHL tTLH tTHL tOSHL Parameter Propagation Delay Data to Output Transition Time 20% to 80%, 80% to 20% Maximum Skew Common Edge Output-to-Output Variation Data to Output Path tOSLH Maximum Skew Common Edge Output-to-Output Variation Data to Output Path tOST Maximum Skew Opposite Edge Output-to-Output Variation Data to Output Path tPS Maximum Skew Pin (Signal) Transition Variation Data to Output Path Note 5: The propagation delay specified is for single output switching. Delays may vary up to 100 ps with multiple outputs switching. Note 6: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged device. The specifications apply to any outputs switching in the same direction either HIGH-to-LOW (tOSHL), or LOW-to-HIGH (tOSLH), or in opposite directions both HL and LH (tOST). Parameters tOST and tPS guaranteed by design. T C = 0 °C Min 0.50 0.40 Max 1.00 1.10 TC = +25°C Min 0.50 0.40 Max 1.05 1.10 TC = +85°C Min 0.50 0.40 Max 1.10 1.10 Units Conditions Figures 1, 2 (Note 5) Figures 1, 2 PLCC Only ns ns 240 240 240 ps (Note 6) PLCC Only 330 330 330 ps (Note 6) PLCC Only 330 330 330 ps (Note 6) PLCC Only 230 230 230 ps (Note 6) Industrial Version PLCC DC Electrical Characteristics (Note 7) VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = −40°C to +85°C Symbol VOH VOL VOHC VOLC VIH VIL IIL IIH IEE Parameter Output HIGH Voltage Output LOW Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input LOW Current Input HIGH Current Power Supply Current −29 −1170 −1830 0.50 240 −15 −29 TC = −40°C Min −1085 −1830 −1095 −1565 −870 −1480 −1165 −1830 0.50 240 −15 Max −870 −1575 TC = 0°C to +85°C Min −1025 −1830 −1035 −1610 −870 −1475 Max −870 −1620 mV mV mV mV mV mV µA µA mA VIN = VIH(Max) or VIL(Min) VIN = VIH(Min) or VIL(Max) Loading with 50Ω to −2.0V Loading with 50Ω to −2.0V Units Conditions Guaranteed HIGH Signal for All Inputs Guaranteed LOW Signal for All Inputs VIN = VIL(Min) VIN = VIH(Max) Inputs Open Note 7: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions. PLCC AC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND Symbol tPLH tPHL tTLH tTHL Parameter Propagation Delay Data to Output Transition Time 20% to 80%, 80% to 20% TC = −40°C Min 0.40 0.30 Max 1.00 1.10 TC = +25°C Min 0.50 0.40 Max 1.05 1.10 TC = +85°C Min 0.50 0.40 Max 1.10 1.10 ns ns Figures 1, 2 (Note 8) Figures 1, 2 Units Conditions Note 8: The propagation delay specified is for single output switching. Delays may vary up to 100 ps with multiple outputs switching. www.fairchildsemi.com 4 100301 Test Circuitry Notes: VCC, VCCA = +2V, VEE = −2.5V L1 and L2 = equal length 50Ω impedance lines RT = 50Ω terminator internal to scope Decoupling 0.1 µF from GND to VCC and VEE All unused outputs are loaded with 50Ω to GND CL = Fixture and stray capacitance ≤ 3 pF FIGURE 1. AC Test Circuit Switching Waveforms FIGURE 2. Propagation Delay and Transition Times 5 www.fairchildsemi.com 100301 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide Package Number N24E www.fairchildsemi.com 6 100301 Low Power Triple 5-Input OR/NOR Gate Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Package Number V28A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com www.fairchildsemi.com