100324SC

100324 Low Power Hex TTL-to-ECL Translator July 1988 Revised August 2000 100324 Low Power Hex TTL-to-ECL Translator General Description The 100324 is a hex translator, designed to convert TTL logic levels to 100K ECL logic levels. The inputs are compatible with standard or Schottky TTL. A common Enable (E), when LOW, holds all inverting outputs HIGH and holds all true outputs LOW. The differential outputs allow each circuit to be used as an inverting/non-inverting translator, or as a differential line driver. The output levels are voltage compensated over the full −4.2V to −5.7V range. When the circuit is used in the differential mode, the 100324, due to its high common mode rejection, overcomes voltage gradients between the TTL and ECL ground systems. The VEE and VTTL power may be applied in either order. The 100324 is pin and function compatible with the 100124 with similar AC performance, but features power dissipation roughly half of the 100124 to ease system cooling requirements. Features s Pin/function compatible with 100124 s Meets 100124 AC specifications s 50% power reduction of the 100124 s Differential outputs s 2000V ESD protection s −4.2V to −5.7V operating range s Available to MIL-STD-883 s Available to industrial grade temperature range (PLCC package only) Ordering Code: Order Number 100324SC 100324PC 100324QC 100324QI Package Number M24B N24E V28A V28A Package Description 28-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Industrial Temperature Range (−40°C to +85°C) Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams 24-Pin DIP/SOIC 28-Pin PLCC © 2000 Fairchild Semiconductor Corporation DS009878 www.fairchildsemi.com 100324 Pin Descriptions Pin Names D0 – D5 E Q0–Q5 Q0–Q5 Description Data Inputs Enable Input Data Outputs Complementary Data Outputs Truth Table Inputs Dn X L H H = H IGH Voltage Level L = LOW Voltage Level Outputs E L H H Qn L L H Qn H H L Logic Diagram www.fairchildsemi.com 2 100324 Absolute Maximum Ratings(Note 1) Storage Temperature (TSTG) Maximum Junction Temperature (TJ) VEE Pin Potential to Ground Pin VTTL Pin Potential to Ground Pin Input Voltage (DC) Output Current (DC Output HIGH) ESD (Note 2) −65°C to +150°C +150°C −7.0V to +0.5V −0.5V to +6.0V −0.5V to +6.0V −50 mA ≥2000V Recommended Operating Conditions Case Temperature (TC) Commercial Industrial Supply Voltage (VEE) 0°C to +85°C −40°C to +85°C −5.7V to −4.2V Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 2: ESD testing conforms to MIL-STD-883, Method 3015. Commercial Version DC Electrical Characteristics Symbol VOH VOL VOHC VOLC VIH VIL VCD IIH Parameter Output HIGH Voltage Output LOW Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Input HIGH Current Data Enable Input HIGH Current Breakdown Test, All Inputs IIL Input LOW Current Data Enable IEE ITTL VEE Power Supply Current VTTL Power Supply Current −0.9 −5.4 −70 −45 25 −22 38 mA mA All Inputs VIN = +4.0V All Inputs VIN = GND mA 20 120 1.0 mA VIN = +5.5V, All Other Inputs = GND VIN = +0.4V, All Other Inputs VIN = VIH µA 2.0 0 −1.2 (Note 3) Typ −955 −1705 Max −870 −1620 −1610 5.0 0.8 Units mV mV V V V VIN =VIH (Max) or VIL (Min) VIN = VIH(Min) or VIL (Max) Guaranteed HIGH Signal for All Inputs Guaranteed LOW Signal for All Inputs IIN = −18 mA VIN = +2.4V, All Other Inputs VIN = GND Conditions Loading with 50Ω to −2.0V Loading with 50Ω to −2.0V VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = 0°C to +85°C, VTTL = +4.5V to +5.5V Min −1025 −1830 −1035 Note 3: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions. DIP AC Electric Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND, VTTL = +4.5V to +5.5V TC = +25°C TC = 0°C Symbol Parameter Min Max Min Max tPLH tPHL tTLH tTHL Propagation Delay Data and Enable to Output Transition Time 20% to 80%, 80% to 20% 0.50 0.45 3.00 1.80 0.50 0.45 2.90 1.80 TC = +85°C Min 0.50 0.45 Max 3.00 1.80 Units ns ns Conditions Figures 2, 1 3 www.fairchildsemi.com 100324 Commercial Version (Continued) SOIC and PLCC AC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND, VTTL = +4.5V to +5.5V T C = 0 °C TC = +25°C Symbol Parameter Min Max Min Max tPLH tPHL tTLH tTHL tOSHL Propagation Delay Data and Enable to Output Transition Time 20% to 80%, 80% to 20% Maximum Skew Common Edge Output-to-Output Variation Data to Output Path tOSLH Maximum Skew Common Edge Output-to-Output Variation Data to Output Path tOST Maximum Skew Opposite Edge Output-to-Output Variation Data to Output Path tPS Maximum Skew Pin (Signal) Transition Variation Data to Output Path Note 4: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged device. The specifications apply to any outputs switching in the same direction either HIGH-to-LOW (tOSHL), or LOW-to-HIGH (tOSLH), or in opposite directions both HL and LH (tOST). Parameters tOST and tPS guaranteed by design. TC = +85°C Min 0.50 0.45 Max 2.80 1.70 Units Conditions 0.50 0.45 2.80 1.70 0.50 0.45 2.70 1.70 ns ns Figures 2, 1 PLCC Only 0.95 0.95 0.95 ns (Note 4) PLCC Only 0.70 0.70 0.70 ns (Note 4) PLCC Only 1.60 1.60 1.60 ns (Note 4) PLCC Only 1.20 1.20 1.20 ns (Note 4) www.fairchildsemi.com 4 100324 Industrial Version DC Electrical Characteristics (Note 5) VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = −40°C to +85°C, VTTL = +4.5V to +5.5V TC = −40°C TC = 0°C to +85°C Symbol Parameter Units Min Max Min Max VOH VOL VOHC VOLC VIH VIL VCD IIH Output HIGH Voltage Output LOW Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Input HIGH Current Data Enable Input HIGH Current Breakdown Test, All Inputs IIL Input LOW Current Data Enable IEE ITTL VEE Power Supply Current VTTL Power Supply Current −0.9 −5.4 −70 −22 38 −0.9 −5.4 −70 −22 38 mA mA All Inputs VIN = +4.0V All Inputs VIN = GND mA 20 120 1.0 20 120 1.0 mA VIN = +5.5V, All Other Inputs = GND VIN = +0.4V, All Other Inputs VIN = VIH µA 2.0 0 −1.2 −1085 −1830 −1095 −1565 5.0 0.8 2.0 0 −1.2 −870 −1575 −1025 −1830 −1035 −1610 5.0 0.8 −870 −1620 mV mV V V V or VIL (Min) VIN = VIH(Min) or VIL (Max) Guaranteed HIGH Signal for All Inputs Guaranteed LOW Signal for All Inputs IIN = −18 mA VIN = +2.4V, All Other Inputs VIN = GND Conditions VIN =VIH (Max) Loading with 50Ω to −2.0V Loading with 50Ω to −2.0V Note 5: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions. AC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND, VTTL = +4.5V to +5.5V TC = −40°C TC = +25°C Symbol Parameter Min Max Min Max tPLH tPHL tTLH tTHL Propagation Delay Data and Enable to Output Transition Times 20% to 80%, 80% to 20% 0.50 0.35 2.80 1.80 0.50 0.45 2.70 1.70 TC = +85°C Min 0.50 0.45 Max 2.80 1.70 Units ns ns Conditions Figures 2, 1 Figures 2, 1 5 www.fairchildsemi.com 100324 Test Circuit Note: • • • • • • VCC, VCCA = 0V, VEE = −4.5V, VTTL = +5.0V, VIH = +3.0V L1, L2 and L3 = equal length 50Ω impedance lines RT = 50Ω terminator internal to scope Decoupling 0.1 µF from GND to VCC, VEE and VTTL All unused outputs are loaded with 50Ω to −2V or with equivalent ECL terminator network CL = Fixture and stray capacitance ≤ 3 pF FIGURE 1. AC Test Circuit Switching Waveform FIGURE 2. Propagation Delay and Transition Times www.fairchildsemi.com 6 100324 Physical Dimensions inches (millimeters) unless otherwise noted 28-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide Package Number N24E 7 www.fairchildsemi.com 100324 Low Power Hex TTL-to-ECL Translator Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square) Package Number V28A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 8 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com