100325SC

100325 Low Power Hex ECL-to-TTL Translator July 1988 Revised August 2000 100325 Low Power Hex ECL-to-TTL Translator General Description The 100325 is a hex translator for converting F100K logic levels to TTL logic levels. Differential inputs allow each circuit to be used as an inverting, non-inverting or differential receiver. An internal reference voltage generator provides VBB for single-ended operation, or for use in Schmitt trigger applications. All inputs have 50kΩ pull-down resistors. When the inputs are either unconnected or at the same potential the outputs will go LOW. When used in single-ended operation the apparent input threshold of the true inputs is 20mV to 40mV higher (positive) than the threshold of the complementary inputs. The VEE and VTTL power may be applied in either order. Features s Pin/function compatible with 100125 s Meets 100125 AC specifications s 50% power reduction of the 100125 s Differential inputs with built in offset s Standard FAST outputs s 2000V ESD protection s −4.2V to −5.7V operating range s Available to industrial grade temperature range Ordering Code: Order Number 100325SC 100325PC 100325QI 100325QC Package Number M24B N24E V28A V28A Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Industrial Temperature Range (−40°C to +85°C) Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams 24-Pin DIP/SOIC 28-Pin PLCC Pin Descriptions Pin Names D0 – D5 D0 – D5 Q0–Q5 Description Data Inputs Inverting Data Inputs Data Outputs FAST is a registered trademark of Fairchild Semiconductor Corporation. © 2000 Fairchild Semiconductor Corporation DS009879 www.fairchildsemi.com 100325 Truth Table Inputs Dn L H L H Dn H L L H Outputs Qn L H L L Logic Diagram OPEN VEE L H VBB VBB H = HIGH Voltage Level L = LOW Voltage Level OPEN VEE VBB VBB L H L L L H H L www.fairchildsemi.com 2 100325 Absolute Maximum Ratings(Note 1) Storage Temperature (TSTG) Maximum Junction Temperature (TJ) VEE Pin Potential to Ground Pin VTTL Pin Potential to Ground Pin Input Voltage (DC) Voltage Applied to Output in HIGH State (with VCC = 0V) Current Applied to Output in LOW State (Max) ESD (Note 2) twice the rated IOL (mA) −65°C to +150 °C +150 °C −7.0V to +0.5V −0.5V to +6.0V VEE to +0.5V Recommended Operating Conditions Case Temperature (TC) Commercial Industrial Supply Voltage (VEE) 0°C to +85°C −40°C to +85°C −5.7V to −4.2V −0.5V to VCC ≥2000V Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 2: ESD testing conforms to MIL-STD-883, Method 3015. Commercial Version DC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = GND, VTTL = +4.5V to 5.5V, TC = 0°C to +85°C (Note 3) Symbol VBB VIH VIL VOH VOL VDIFF VCM IIH IIL IOS IEE ITTL Parameter Output Reference Voltage Single-Ended Input HIGH Voltage Single-Ended Input LOW Voltage Output HIGH Voltage Output LOW Voltage Input Voltage Differential Common Mode Voltage Input HIGH Current Input LOW Current Output Short-Circuit Current VEE Power Supply Current VTTL Power Supply Current 0.5 −150 −37 −27 45 −60 −17 65 150 VCC − 2.0 VCC − 0.5 350 Min −1380 −1165 −1830 2.5 0.5 Typ −1320 Max −1260 −870 −1475 Units mV mV mV V V mV V µA µA mA mA mA VIN = VIH (Max), D0–D5 = VBB, D0–D5 = VIL (Min) VIN = VIL (Min), D0–D5 = VBB VOUT = GND (Note 4) D0–D5 = VBB D0–D5 = VBB IVBB = −2.1 mA Guaranteed HIGH Signal for All Inputs (with One Input Tied to VBB) Guaranteed LOW Signal for All Inputs (with One Input Tied to VBB) IOH = −2.0 mA IOL = 20 mA Required for Full Output Swing VIN = VIH (Max) or VIL (Min) Conditions Note 3: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions. Note 4: Test one output at a time. DIP AC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = GND, VTTL = +4.5V to +5.5V TC = 0°C Symbol Parameter Min Max tPLH tPHL tPLH tPHL Propagation Delay Data to Output Propagation Delay Data to Output 0.80 1.60 3.50 4.30 TC = +25°C Min 0.90 1.70 Max 3.70 4.50 TC = +85°C Min 1.00 1.80 Max 4.00 4.80 Units ns ns Conditions CL = 15 pF Figures 1, 2 CL = 50 pF Figures 1, 3 3 www.fairchildsemi.com 100325 Commercial Version (Continued) SOIC and PLCC AC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = GND, VTTL = +4.5V to +5.5V TC = 0°C Symbol Parameter Min Max tPLH tPHL tPLH tPHL tOSHL Propagation Delay Data to Output Propagation Delay Data to Output Maximum Skew Common Edge Output-to-Output Variation Data to Output Path tOSLH Maximum Skew Common Edge Output-to-Output Variation Data to Output Path tOST Maximum Skew Opposite Edge Output-to-Output Variation Data to Output Path tPS Maximum Skew Pin (Signal) Transition Variation Data to Output Path Note 5: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged device. The specifications apply to any outputs switching in the same direction either HIGH-to-LOW (tOSHL), or LOW-to-HIGH (tOSLH), or in opposite directions both HL and LH (tOST). Parameters tOST and tPS guaranteed by design. TC = +25°C Min 0.90 1.70 Max 3.50 4.30 TC = +85°C Min 1.00 1.80 Max 3.80 4.60 Units Conditions CL = 15 pF Figures 1, 2 CL = 50 pF Figures 1, 3 PLCC Only (Note 5) PLCC Only 0.80 1.60 3.30 4.10 ns ns 0.65 0.65 0.65 ns 0.65 0.65 0.65 ns (Note 5) PLCC Only 2.20 2.20 2.20 ns (Note 5) PLCC Only 2.10 2.10 2.10 ns (Note 5) www.fairchildsemi.com 4 100325 Industrial Version PLCC DC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = GND, TC = −40°C to +85°C (Note 6) TC = 0°C to +85°C TC = −40°C Symbol Parameter Min Max Min Max VBB VIH VIL VOH VOL VDIFF VCM IIH IIL IOS IEE ITTL Output Reference Voltage Single-Ended Input HIGH Voltage Single-Ended Input LOW Voltage Output HIGH Voltage Output LOW Voltage Input Voltage Differential Common Mode Voltage Input HIGH Current Input LOW Current Output Short-Circuit Current VEE Power Supply Current VTTL Power Supply Current 0.5 −150 −37 −60 −15 65 150 450 0.5 −150 −37 −60 −17 65 −1395 −1170 −1830 2.5 0.5 150 350 −1255 −870 −1480 −1380 −1165 −1830 2.5 0.5 −1260 −870 −1475 Units mV mV mV V V mV V µA µA mA mA mA VIN = VIH (Max), D0–D5 = VBB, D0–D5 = VIL (Min) VIN = VIL (Min), D0–D5 = VBB VOUT = GND (Note 7) D0–D5 = VBB D0–D5 = VBB IVBB = −2.1 mA Guaranteed HIGH Signal for All Inputs (with One Input Tied to VBB) Guaranteed LOW Signal for All Inputs (with One Input Tied to VBB) IOH = −2.0 mA IOL = 20 mA VIN = VIH (Max) or VIL (Min) Conditions Required for Full Output Swing VCC − 2.0 VCC − 0.5 VCC − 2.0 VCC − 0.5 Note 6: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions. Note 7: Test one output at a time. PLCC AC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = GND, VTTL = +4.5V to +5.5V Symbol tPLH tPHL tPLH tPHL Parameter Propagation Delay Data to Output Propagation Delay Data to Output TC = −40°C Min 0.80 1.60 Max 3.30 4.10 TC = +25°C Min 0.90 1.70 Max 3.50 4.30 TC = +85°C Min 1.00 1.80 Max 3.80 4.60 ns ns CL = 15 pF Figures 1, 2 CL = 50 pF Figures 1, 3 Units Conditions Switching Waveform FIGURE 1. Propagation Delay 5 www.fairchildsemi.com 100325 Test Circuits Note: • • • • • • VCC = 0V, VEE = −4.5V, VTTL = +5V L1 and L2 = equal length 50Ω impedance lines RT = 50Ω terminator internal to scope Decoupling 0.1 µF from GND to VCC, VEE and VTTL All unused outputs are loaded with 500Ω to GND CL = Fixture and stray capacitance = 15 pF FIGURE 2. AC Test Circuit for 15 pF Loading www.fairchildsemi.com 6 100325 Test Circuits (Continued) Note: • • • • • • VCC = 0V, V EE = −4.5V, VTTL = +5V L1 and L2 = equal length 50Ω impedance lines RT = 50Ω terminator internal to scope Decoupling 0.1 µF from GND to VCC, VEE and VTTL All unused outputs are loaded with 500Ω to GND CL = Fixture and stray capacitance = 50 pF FIGURE 3. AC Test Circuit for 50 pF Loading 7 www.fairchildsemi.com 100325 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide Package Number N24E www.fairchildsemi.com 8 100325 Low Power Hex ECL-to-TTL Translator Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Package Number V28A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 9 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com www.fairchildsemi.com