100329A

100329A Low Power Octal ECL/TTL Bidirectional Translator with Register August 1989 Revised August 2000 100329A Low Power Octal ECL/TTL Bidirectional Translator with Register General Description The 100329A is an octal registered bidirectional translator designed to convert TTL logic levels to 100K ECL logic levels and vice versa. The direction of the translation is determined by the DIR input. A LOW on the output enable input (OE) holds the ECL outputs in a cut-off state and the TTL outputs at a high impedance level. The outputs change synchronously with the rising edge of the clock input (CP) even though only one output is enabled at the time. The cut-off state is designed to be more negative than a normal ECL LOW level. This allows the output emitter-followers to turn off when the termination supply is −2.0V, presenting a high impedance to the data bus. This high impedance reduces the termination power and prevents loss of low state noise margin when several loads share the bus. The 100329A is designed with FAST TTL output buffers, featuring optimal DC drive and capable of quickly charging and discharging highly capacitive loads. All inputs have 50 kΩ pull-down resistors. Features s Bidirectional translation s ECL high impedance outputs s Registered outputs s FAST TTL outputs s 3-STATE outputs s Voltage compensated operating range = −4.2V to −5.7V s High drive IOS Ordering Code: Order Number 100329APC Package Number N24E Package Description 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide Logic Symbol Connection Diagram Pin Descriptions Pin Names E0–E7 T0–T7 OE CP DIR Description ECL Data I/O TTL Data I/O Output Enable Input Clock Pulse Input (Active Rising Edge) Direction Control Input All pins function at 100K ECL levels except for T0–T7. FAST is a registered trademark of Fairchild Semiconductor Corporation. © 2000 Fairchild Semiconductor Corporation DS500047 www.fairchildsemi.com 100329A Truth Table OE L L H H H H H H H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High Impedance [N] = LOW-to-HIGH Clock Transition NC = No Change DIR L H L L L H H H CP X X [N] [N] L [N] [N] L ECL Port Input LOW (Cut-Off) L H X L H NC TTL Port Z Input L H NC L H X Notes 1, 3 2, 3 1 1 1, 3 2 2 2, 3 Functional Diagram Detail Note 1: ECL input to TTL output mode. Note 2: TTL input to ECL output mode. Note 3: Retains data present before CP. Note: DIR and OE use ECL logic levels www.fairchildsemi.com 2 100329A Absolute Maximum Ratings(Note 4) Storage Temperature (TSTG) Maximum Junction Temperature (Tj) VEE Pin Potential to Ground Pin VTTL Pin Potential to Ground Pin ECL Input Voltage (DC) ECL Output Current (DC Output HIGH) TTL Input Voltage (Note 6) TTL Input Current (Note 6) Voltage Applied to Output in HIGH State 3-STATE Output Current Applied to TTL Output in LOW State (Max) ESD (Note 5) twice the rated IOL (mA) −65°C to +150°C +150°C −7.0V to +0.5V −0.5V to +6.0V VEE to +0.5V Recommended Operating Conditions Case Temperature (TC) ECL Supply Voltage (VEE) TTL Supply Voltage (VTTL) 0°C to +85°C −5.7V to −4.2V +4.5V to +5.5V −50 mA −0.5V to +6.0V −30 mA to +5.0 mA Note 4: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 5: ESD testing conforms to MIL-STD-883, Method 3015. Note 6: Either voltage limit or current limit is sufficient to protect inputs. −0.5V to +5.5V ≥2000V TTL-to-ECL DC Electrical Characteristics (Note 7) VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = 0°C to +85°C, VTTL = +4.5V to +5.5V Symbol VOH VOL Parameter Output HIGH Voltage Output LOW Voltage Cutoff Voltage −2000 VOHC VOLC VIH VIL IIH IIL VFCD IEE Output HIGH Voltage Corner Point HIGH Output LOW Voltage Corner Point LOW Input HIGH Voltage Input LOW Voltage Input HIGH Current Breakdown Test Input LOW Current Input Clamp Diode Voltage VEE Supply Current −189 −199 −94 −94 mA −700 −1.2 2.0 0 −1950 mV mV Min −1025 −1830 Typ −955 −1705 Max −870 −1620 Units mV mV Conditions VIN = VIH (Max) or VIL (Min) Loading with 50Ω to −2V OE or DIR LOW, VIN = VIH (Max) or VIL (Min) Loading with 50Ω to −2V −1035 −1610 5.0 0.8 70 1.0 VIN = VIH (Min) or VIL (Max) Loading with 50Ω to −2V mV V V µA mA µA V Over VTTL, VEE, TC Range Over VTTL, VEE, TC Range VIN = +2.7V VIN = +5.5V VIN = +0.5V IIN = −18 mA LE LOW, OE and DIR HIGH Inputs OPEN VEE = −4.2V to −4.8V VEE = −4.2V to −5.7V Note 7: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions. 3 www.fairchildsemi.com 100329A ECL-to-TTL DC Electrical Characteristics (Note 8) VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = 0°C to +85°C, CL = 50 pF, VTTL = +4.5V to +5.5V Symbol VOH VOL VIH VIL IIH IIL IOZHT IOZLT IOS ITTL Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current 3-STATE Current Output HIGH 3-STATE Current Output LOW Output Short-Circuit Current VTTL Supply Current −700 −225 −100 74 49 67 0.50 70 −1165 −1830 Min 2.7 2.4 Typ 3.1 2.9 0.3 0.5 −870 −1475 350 Max Units V V V mV mV µA µA µA µA mA mA mA mA Conditions IOH = −3 mA, VTTL = 4.75V IOH = −3 mA, VTTL = 4.50V IOL = 24 mA, VTTL = 4.50V Guaranteed HIGH Signal for All Inputs Guaranteed LOW Signal for All Inputs VIN = VIH (Max) VIN = VIL (Min) VOUT = +2.7V VOUT = +0.5V VOUT = 0.0V, VTTL = +5.5V TTL Outputs LOW TTL Outputs HIGH TTL Outputs in 3-STATE Note 8: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions. DIP TTL-to-ECL AC Electrical Characteristics VEE = −4.2V to −5.7V, VTTL = +4.5V to +5.5V, VCC = VCCA = GND TC = 0°C TC = 25°C Symbol Parameter Min Max Min Max fMAX tPLH tPHL tPZH tPHZ tPHZ tset thold tpw(H) tTLH tTHL OE to En (Cut-off to HIGH) OE to En (HIGH to Cut-off) DIR to En (HIGH to Cut-off) Tn to CP Tn to CP Pulse Width CP Transition Time 20% to 80%, 80% to 20% 1.3 1.5 1.6 1.1 1.7 2.1 0.6 1.6 4.2 4.5 4.3 1.5 1.6 1.6 1.1 1.7 2.1 0.6 1.6 4.4 4.5 4.3 1.7 1.6 1.7 1.1 1.9 2.1 0.6 1.6 4.8 4.6 4.5 ns ns ns ns ns ns ns Figures 1, 2 Figures 1, 2 Figures 1, 2 Figures 1, 2 Figures 1, 2 Figures 1, 2 Figures 1, 2 Max Toggle Frequency CP to En 350 1.7 3.6 350 1.7 3.7 TC = 85°C Min 350 1.9 3.9 Max Units MHz ns Figures 1, 2 Conditions DIP ECL-to-TTL AC Electrical Characteristics VEE = −4.2V to −5.7V, VTTL = +4.5V to +5.5V, VCC = VCCA = GND, CL = 50.pF TC = 0°C TC = 25°C TC = 85°C Symbol Parameter Min Max Min Max Min Max fMAX tPLH tPHL tPZH tPZL tPHZ tPLZ tPHZ tPLZ tset thold tpw(H) OE to Tn (Enable Time) OE to Tn (Disable Time) DIR to Tn (Disable Time) En to CP En to CP Pulse Width CP 3.4 3.8 3.2 3.0 2.7 2.8 1.1 2.1 4.1 8.45 9.2 8.95 7.7 8.2 7.45 3.7 4.0 3.3 3.4 2.8 3.1 1.1 2.1 4.1 8.95 9.2 8.95 8.7 8.7 7.95 4.0 4.3 3.5 4.1 3.1 4.0 1.1 2.6 4.1 9.7 9.95 9.2 9.95 8.95 9.2 ns ns ns ns ns ns Figures 3, 5 Figures 3, 5 Figures 3, 6 Figures 3, 4 Figures 3, 4 Figures 3, 4 Max Toggle Frequency CP to Tn 125 3.1 7.2 125 3.1 7.2 125 3.3 7.7 Units MHz ns Figures 3, 4 Conditions www.fairchildsemi.com 4 100329A Test Circuitry (TTL-to-ECL) Note: RT = 50Ω termination resistive load. When an input or output is being monitored by a scope, RTis supplied by the scope’s 50 Ω input resistance. When an input or output is not being monitored, an external 50Ω resistance must be applied to serve as RT. Note: TTL and ECL force signals are brought to the DUT via 50Ω coax lines. Note: VTTL is decoupled to ground with 0.1 µF, VEE is decoupled to ground with 0.01 µF and VCC is connected to ground. FIGURE 1. TTL-to-ECL AC Test Circuit Switching Waveforms (TTL-to-ECL) FIGURE 2. TTL to ECL Transition—Propagation Delay and Transition Times 5 www.fairchildsemi.com 100329A Test Circuitry (ECL-to-TTL) Note: RT = 50Ω termination resistive load. When an input or output is being monitored by a scope, RTis supplied by the scope’s 50Ω input resistance. When an input or output is not being monitored, an external 50Ω resistance must be applied to serve as R T. Note: The TTL 3-STATE pull-up switch is connected to +7V only for ZL and LZ tests. Note: TTL and ECL force signals are brought to the DUT via 50Ω coax lines. Note: VTTL is decoupled to ground with 0.1 µF, VEE is decoupled to ground with 0.01 µF and VCC is connected to ground. FIGURE 3. ECL-to-TTL AC Test Circuit Switching Waveforms (ECL-to-TTL) Note: DIR is LOW, OE is HIGH FIGURE 4. ECL-to-TTL Transition—Propagation Delay and Transition Times www.fairchildsemi.com 6 100329A Switching Waveforms (Continued) Note: DIR is LOW FIGURE 5. ECL-to-TTL Transition, OE to TTL Output, Enable and Disable Times Note: OE is HIGH FIGURE 6. ECL-to-TTL Transition, DIR to TTL Output, Disable Time 7 www.fairchildsemi.com 100329A Low Power Octal ECL/TTL Bidirectional Translator with Register Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide Package Number N24E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 8 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com