100351

100351 Low Power Hex D-Type Flip-Flop July 1988 Revised August 2000 100351 Low Power Hex D-Type Flip-Flop General Description The 100351 contains six D-type edge-triggered, master/ slave flip-flops with true and complement outputs, a pair of common Clock inputs (CPa and CPb) and common Master Reset (MR) input. Data enters a master when both CPa and CPb are LOW and transfers to the slave when CPa and CPb (or both) go HIGH. The MR input overrides all other inputs and makes the Q outputs LOW. All inputs have 50 kΩ pull-down resistors. Features s 40% power reduction of the 100151 s 2000V ESD protection s Pin/function compatible with 100151 s Voltage compensated operating range: −4.2V to −5.7V s Available to industrial grade temperature range Ordering Code: Order Number 100351SC 100351PC 100351QC 100351QI Package Number M24B N24E V28A V28A Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Industrial Temperature Range (−40°C to +85°C) Devises also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagrams 24-Pin DIP/SOIC Pin Descriptions Pin Names D0–D5 CPa, CPb MR Q0–Q5 Q0–Q5 Data Inputs Common Clock Inputs Asynchronous Master Reset Input Data Outputs Complementary Data Outputs Description 28-Pin PLCC © 2000 Fairchild Semiconductor Corporation DS009885 www.fairchildsemi.com 100351 Truth Tables (Each Flip-flop) Synchronous Operation Inputs Dn L H L H X X X CPa Outputs CPb L MR L L L L L L L Qn(t+1) L H L H Qn(t) Qn(t) Qn(t) Dn X CPa X Asynchronous Operation Inputs CPb X MR H Outputs Qn(t+1) L   L L  H L    L H L H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care t = Time before CP positive transition t+1 = Time after CP positive transition  = LOW-to-HIGH transition Logic Diagram www.fairchildsemi.com 2 100351 Absolute Maximum Ratings(Note 1) Storage Temperature (TSTG) Maximum Junction Temperature (TJ) VEE Pin Potential to Ground Pin Input Voltage (DC) Output Current (DC Output HIGH) ESD (Note 2) −65°C to +150°C +150°C −7.0V to +0.5V VEE to +0.5V Recommended Operating Conditions Case Temperature (TC) Commercial Industrial Supply Voltage (VEE) 0°C to +85°C −40°C to +85°C −5.7V to −4.2V −50 mA ≥2000V Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 2: ESD testing conforms to MIL-STD-883, Method 3015. Commercial Version DC Electrical Characteristics (Note 3) VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = 0°C to +85°C Symbol VOH VOL VOHC VOLC VIH VIL IIL IIH Parameter Output HIGH Voltage Output LOW Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input LOW Current Input HIGH Current MR D0–D5 CPa, CPb IEE Power Supply Current −129 350 240 350 −62 mA Inputs OPEN µA VIN = VIH (Max) −1165 −1830 0.50 Min −1025 −1830 −1035 −1610 −870 −1475 Typ −955 −1705 Max −870 −1620 Units mV mV mV mV µA VIN =VIH (Max) or VIL (Min) VIN = VIH (Min) or VIL (Max) Conditions Loading with 50Ω to −2.0V Loading with 50Ω to −2.0V Guaranteed HIGH Signal for All Inputs Guaranteed LOW Signal for All Inputs VIN = VIL (Min) Note 3: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions. DIP AC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND Symbol fMAX tPLH tPHL tPLH tPHL tTLH tTHL tS Parameter Toggle Frequency Propagation Delay CPa, CPb to Output Propagation Delay MR to Output Transition Time 20% to 80%, 80% to 20% Setup Time D0–D5 MR (Release Time) tH tPW(H) Hold Time D0–D5 Pulse Width HIGH CPa, CPb, MR 0.40 1.60 0.80 2.00 0.40 1.60 0.80 2.00 0.40 1.60 0.80 2.00 ns ns ns Figure 5 Figure 4 Figure 5 Figures 3, 4 TC = 0°C Min 375 0.80 1.10 0.35 2.00 2.30 1.20 Max TC = +25°C Min 375 0.80 1.10 0.35 2.0 2.30 1.20 Max TC = +85°C Min 375 0.90 1.20 0.35 2.10 2.40 1.20 Max MHz ns ns ns Figures 2, 3 Figures 1, 3 Figures 1, 4 Figures 1, 3 Units Conditions 3 www.fairchildsemi.com 100351 Commercial Version (Continued) SOIC and PLCC AC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND Symbol fMAX tPLH tPHL tPLH tPHL tTLH tTHL tS Parameter Toggle Frequency Propagation Delay CPa, CPb to Output Propagation Delay MR to Output Transition Time 20% to 80%, 80% to 20% Setup Time D0–D5 MR (Release Time) tH tPW(H) tOSHL Hold Time D0–D5 Pulse Width HIGH CPa, CPb, MR Maximum Skew Common Edge Output-to-Output Variation Clock to Output Path tOSLH Maximum Skew Common Edge Output-to-Output Variation Clock to Output Path tOST Maximum Skew Opposite Edge Output-to-Output Variation Clock to Output Path tPS Maximum Skew Pin (Signal) Transition Variation Clock to Output Path Note 4: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged device. The specifications apply to any outputs switching in the same direction either HIGH-to-LOW (tOSHL), or LOW-to-HIGH (tOSLH), or in opposite directions both HL and LH (tOST). Parameters tOST and tPS guaranteed by design. TC = 0°C Min 375 0.80 1.10 0.45 1.80 2.10 1.70 Max TC = +25°C Min 375 0.80 1.10 0.45 1.80 2.10 1.60 Max TC = +85°C Min 375 0.90 1.20 0.45 1.90 2.20 1.70 Max Units MHz ns ns ns Conditions Figures 2, 3 Figures 1, 3 Figures 1, 4 Figures 1, 3 0.30 1.50 0.80 2.00 0.30 1.50 0.80 2.00 0.30 1.50 0.80 2.00 ns Figure 5 Figure 4 ns ns Figure 5 Figures 3, 4 PLCC only 220 220 220 ps (Note 4) PLCC only 210 210 210 ps (Note 4) PLCC only 240 240 240 ps (Note 4) PLCC only 230 230 230 ps (Note 4) www.fairchildsemi.com 4 100351 Industrial Version PLCC DC Electrical Characteristics VEE=−4.2V to −5.7V, VCC=VCCA= GND, TC= 0°C to +85°C (Note 5) Symbol VOH VOL VOHC VOLC VIH VIL IIL IIH Parameter Output HIGH Voltage Output LOW Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input LOW Current Input HIGH Current MR D0–D5 CPa, CPb IEE Power Supply Current −129 350 240 350 −62 −129 350 240 350 −62 mA Inputs OPEN µA VIN = VIH (Max) −1170 −1830 0.50 TC = −40°C Min −1085 −1830 −1095 −1565 −870 −1480 −1165 −1830 0.50 Max −870 −1575 TC = 0° to +85°C Min −1025 −1830 −1035 −1610 −870 −1475 Max −870 −1620 Units mV mV mV mV µA Conditions VIN =VIH (Max) or VIL (Min) VIN = VIH (Min) or VIL (Max) for All Inputs Guaranteed LOW Signal for All Inputs VIN = VIL (Min) Loading with 50Ω to −2.0V Loading with 50Ω to −2.0V Guaranteed HIGH Signal Note 5: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions. PLCC AC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND Symbol fMAX tPLH tPHL tPLH tPHL tTLH tTHL tS Parameter Toggle Frequency Propagation Delay CPa, CPb to Output Propagation Delay MR to Output Transition Time 20% to 80%, 80% to 20% Setup Time D0–D5 MR (Release Time) tH tPW(H) Hold Time D0–D5 Pulse Width HIGH CPa, CPb, MR 0.60 2.20 0.60 2.00 0.30 1.50 0.90 2.00 0.30 1.50 0.90 2.00 ns ns ns Figure 5 Figure 4 Figure 5 Figures 3, 4 TC = −40°C Min 375 0.80 1.10 0.45 1.80 2.10 1.70 Max TC = +25°C Min 375 0.80 1.10 0.45 1.80 2.10 1.60 Max TC = +85°C Min 375 0.90 1.20 0.45 1.90 2.20 1.70 Max Units MHz ns ns ns Conditions Figures 2, 3 Figures 1, 3 Figures 1, 4 Figures 1, 3 5 www.fairchildsemi.com 100351 Test Circuitry Notes: VCC, VCCA = +2V, VEE = −2.5V L1 and L2 = equal length 50Ω impedance lines RT = 50Ω terminator internal to scope Decoupling 0.1 µF from GND to VCC and VEE All unused outputs are loaded with 50Ω to GND CL = Fixture and stray capacitance ≤ 3 pF FIGURE 1. AC Test Circuit Notes: VCC, VCCA = +2V, VEE = −2.5V L1 and L2 = equal length 50Ω impedance lines RT = 50Ω terminator internal to scope Decoupling 0.1 µF from GND to VCC and VEE All unused outputs are loaded with 50Ω to GND CL = Jig and stray capacitance ≤ 3 pF FIGURE 2. Toggle Frequency Test Circuit www.fairchildsemi.com 6 100351 Switching Waveforms FIGURE 3. Propagation Delay (Clock) and Transition Times FIGURE 4. Propagation Delay (Reset) Notes: tS is the minimum time before the transition of the clock that information must be present at the data input. tH is the minimum time after the transition of the clock that information must remain unchanged at the data input. FIGURE 5. Setup and Hold Time 7 www.fairchildsemi.com 100351 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide Package Number N24E www.fairchildsemi.com 8 100351 Low Power Hex D-Type Flip-Flop Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Package Number V28A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 9 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com www.fairchildsemi.com