100354QC

100354 Low Power 8-Bit Register with Cut-Off Drivers October 1989 Revised August 2000 100354 Low Power 8-Bit Register with Cut-Off Drivers General Description The 100354 contains eight D-type edge triggered, master/ slave flip-flops with individual inputs (Dn), true outputs (Qn), a clock input (CP), an output enable pin (OEN), and a common clock enable pin (CEN). Data enters the master when CP is LOW and transfers to the slave when CP goes HIGH. When the CEN input goes HIGH it overrides all other inputs, disables the clock, and the Q outputs maintain the last state. A Q output follows its D input when the OEN pin is LOW. A HIGH on OEN holds the outputs in a cut-off state. The cutoff state is designed to be more negative than a normal ECL LOW level. This allows the output emitter-followers to turn off when the termination supply is −2.0V, presenting a high impedance to the data bus. This high impedance reduces termination power and prevents loss of low state noise margin when several loads share the bus. The 100354 outputs are designed to drive a doubly terminated 50Ω transmission line (25Ω load impedance). All inputs have 50 kΩ pull-down resistors. Features s Cut-off drivers s Drives 25Ω load s Low power operation s 2000V ESD protection s Voltage compensated operating range = −4.2V to −5.7V s Available to industrial grade temperature range Ordering Code: Order Number 100354PC 100354QC 100354QI Package Number N24E V28A V28A Package Description 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Industrial Temperature Range (−40°C to +85°C) Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagrams 24-Pin DIP Pin Descriptions Pin Names D0 – D7 CEN CP OEN Q0–Q7 Description Data Inputs Clock Enable Input Clock Input (Active Rising Edge) Output Enable Input Data Outputs 28-Pin PLCC © 2000 Fairchild Semiconductor Corporation DS010610 www.fairchildsemi.com 100354 Truth Table Inputs Dn L H X X X X H = HIGH Voltage Level L = LOW Voltage Level NC = No Change X = Don’t Care Cutoff = Lower-than-LOW State = LOW-to-HIGH Transition Outputs CP CEN L L X X H X   L H X X OEN L L L L L H Qn L H NC NC NC Cutoff  Logic Diagram www.fairchildsemi.com 2 100354 Absolute Maximum Ratings(Note 1) Storage Temperature (TSTG) Maximum Junction Temperature (TJ) VEE Pin Potential to Ground Pin Input Voltage (DC) Output Current (DC Output HIGH) ESD (Note 2) −65°C to +150°C +150°C −7.0V to +0.5V VEE to +0.5V Recommended Operating Conditions Case Temperature (TC) Commercial Industrial Supply Voltage (VEE) 0°C to +85°C −40°C to +85°C −5.7V to −4.2V −100 mA ≥2000V Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 2: ESD testing conforms to MIL-STD-883, Method 3015. Commercial Version DC Electrical Characteristics (Note 3) VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = 0°C to +85°C Symbol VOH VOL VOHC VOLC VOLZ VIH VIL IIL IIH IEE Parameter Output HIGH Voltage Output LOW Voltage Output HIGH Voltage Output LOW Voltage Cutoff LOW Voltage Input HIGH Voltage Input LOW Voltage Input LOW Current Input HIGH Current Power Supply Current −202 −209 −105 −105 mA −1165 −1830 0.50 240 Min −1025 −1830 −1035 −1610 −1950 −870 −1475 Typ −955 −1705 Max −870 −1620 Units mV mV mV mV mV µA µA VIN =VIH (Max) or VIL (Min) VIN = VIH (Min) or VIL (Max) VIN = VIH (Min) or VIL (Max) Guaranteed HIGH Signal for All Inputs Guaranteed LOW Signal for All Inputs VIN = VIL (Min) VIN = VIH (Max) Inputs Open VEE = −4.2V to −4.8V VEE = −4.2V to −5.7V Conditions Loading with 25Ω to −2.0V Loading with 25Ω to −2.0V OEN = HIGH Note 3: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions. 3 www.fairchildsemi.com 100354 Commercial Version (Continued) DIP AC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND Symbol fMAX tPLH tPHL tPZH tPHZ tTLH tTHL tS Parameter Toggle Frequency Propagation Delay CP to Output Propagation Delay OEN to Output Transition Time 20% to 80%, 80% to 20% Setup Time Dn CEN (Disable Time) CEN (Release Time) tH tPW(H) Hold Time Dn Pulse Width HIGH CP 1.10 0.40 1.10 0.10 2.00 1.10 0.40 1.10 0.10 2.00 1.10 0.40 1.10 0.10 2.00 ns ns Figures 1, 6 Figures 1, 4 ns Figures 2, 5 TC = 0°C Min 250 1.40 1.60 1.00 0.45 3.00 4.20 2.70 2.00 Max TC = +25°C Min 250 1.40 1.60 1.00 0.45 3.00 4.20 2.70 2.00 Max TC = +85°C Min 250 1.50 1.60 1.00 0.45 3.10 4.20 2.70 2.00 Max MHz ns ns ns Figures 1, 4 Figures 1, 4 (Note 4) Figures 3, 7 (Note 4) Figures 1, 4 Units Conditions Note 4: The propagation delay specified is for single output switching. Delays may vary up to 300 ps with multiple outputs switching. PLCC AC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND Symbol fMAX tPLH tPHL tPZH tPHZ tTLH tTHL tS Parameter Toggle Frequency Propagation Delay CP to Output Propagation Delay OEN to Output Transition Time 20% to 80%, 80% to 20% Setup Time Dn CEN (Disable Time) CEN (Release Time) tH tPW(H) tOSHL Hold Time Dn Pulse Width HIGH CP Maximum Skew Common Edge Output-to-Output Variation Clock to Output Path tOSLH Maximum Skew Common Edge Output-to-Output Variation Clock to Output Path tOST Maximum Skew Opposite Edge Output-to-Output Variation Clock to Output Path tPS Maximum Skew Pin (Signal) Transition Variation Clock to Output Path Note 5: The propagation delay specified is for single output switching. Delays may vary up to 300 ps with multiple outputs switching. Note 6: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged device. The specifications apply to any outputs switching in the same direction either HIGH-to-LOW (tOSHL), or LOW-to-HIGH (tOSLH), or in opposite directions both HL and LH (tOST). Parameters tOST and tPS guaranteed by design. TC = 0°C Min 250 1.40 1.60 1.00 0.45 2.80 4.00 2.50 1.90 Max TC = +25°C Min 250 1.40 1.60 1.00 0.45 2.80 4.00 2.50 1.90 Max TC = +85°C Min 250 1.50 1.60 1.00 0.45 2.90 4.00 2.50 1.90 Max Units MHz ns ns ns Conditions Figures 1, 4 Figures 1, 4 (Note 5) Figures 3, 7 (Note 5) Figures 1, 4 1.00 0.30 1.00 0.00 2.00 1.00 0.30 1.00 0.00 2.00 1.00 0.30 1.00 0.00 2.00 ns ns Figures 1, 6 Figures 1, 4 ns Figures 2, 5 280 280 280 ps (Note 6) 340 340 340 ps (Note 6) 340 340 340 ps (Note 6) 250 250 250 ps (Note 6) www.fairchildsemi.com 4 100354 Industrial Version PLCC DC Electrical Characteristics (Note 7) VEE=−4.2V to −5.7V, VCC= VCCA= GND, TC=−40°C to +85°C TC = −40°C Symbol Parameter Min Max VOH VOL VOHC VOLC VOLZ VIH VIL IIL IIH IEE Output HIGH Voltage Output LOW Voltage Output HIGH Voltage Output LOW Voltage Cutoff LOW Voltage Input HIGH Voltage Input LOW Voltage Input LOW Current Input HIGH Current Power Supply Current −202 −209 −105 −105 −202 −209 −105 −105 mA −1170 −1830 0.50 240 −1085 −1830 −1095 −1565 −1900 −870 −1480 −1165 −1830 0.50 240 −870 −1575 TC = 0° to +85°C Min −1025 −1830 −1035 −1610 −1950 −870 −1475 Max −870 −1620 Units mV mV mV mV mV µA µA Conditions VIN =VIH (Max) or VIL (Min) VIN = VIH (Min) or VIL (Max) VIN = VIH (Min) or VIL (Max) Guaranteed HIGH Signal for All Inputs Guaranteed LOW Signal for All Inputs VIN = VIL (Min) VIN = VIH (Max) Inputs Open VEE = −4.2V to −4.8V VEE = −4.2V to −5.7V Loading with 50Ω to −2.0V Loading with 50Ω to −2.0V OEN = HIGH Note 7: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions. PLCC AC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND Symbol fMAX tPLH tPHL tPZH tPHZ tTLH tTHL tS Parameter Toggle Frequency Propagation Delay CP to Output Propagation Delay OEN to Output Transition Time 20% to 80%, 80% to 20% Setup Time Dn CEN (Disable Time) CEN (Release Time) tH tPW(H) Hold Time Dn Pulse Width High CP 1.00 0.30 1.00 0.00 2.00 1.00 0.30 1.00 0.00 2.00 1.00 0.30 1.00 0.00 2.00 ns ns Figures 1, 6 Figures 1, 4 ns Figures 2, 5 TC = −40°C Min 250 1.40 1.50 1.00 0.45 2.80 4.10 2.50 1.90 Max TC = +25°C Min 250 1.40 1.60 1.00 0.45 2.80 4.00 2.50 1.90 Max TC = +85°C Min 250 1.50 1.60 1.00 0.45 2.90 4.00 2.50 1.90 Max Units MHz ns ns ns Conditions Figures 1, 4 Figures 1, 4 (Note 8) Figures 3, 5 (Note 8) Figures 1, 4 Note 8: The propagation delay specified is for single output switching. Delays may vary up to 300 ps with multiple outputs switching. 5 www.fairchildsemi.com 100354 Test Circuitry FIGURE 1. Toggle Frequency Test Circuit FIGURE 2. AC Test Circuit FIGURE 3. AC Test Circuit Notes: VCC, VCCA = +2V, VEE = −2.5V L1 and L2 = equal length 50Ω impedance lines RT = 50Ω terminator internal to scope Decoupling 0.1 µF from GND to VCC and VEE All unused outputs are loaded with 25Ω to GND CL = Fixture and stray capacitance ≤ 3 pF www.fairchildsemi.com 6 100354 Switching Waveforms FIGURE 4. Propagation Delay (Clock) and Transition Times FIGURE 5. Setup and Pulse Width Times Notes: tS is the minimum time before the transition of the clock that information must be present at the data input. tH is the minimum time after the transition of the clock that information must remain unchanged at the data input. FIGURE 6. Data Setup and Hold Time Note: The output AC measurement point for cut-off propagation delay testing = the 50% voltage point between active VOL and VOH. FIGURE 7. Cutoff Times 7 www.fairchildsemi.com 100354 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide Package Number N24E www.fairchildsemi.com 8 100354 Low Power 8-Bit Register with Cut-Off Drivers Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Package Number V28A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 9 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com www.fairchildsemi.com