100355QI

100355 Low Power Quad Multiplexer/Latch July 1989 Revised August 2000 100355 Low Power Quad Multiplexer/Latch General Description The 100355 contains four transparent latches, each of which can accept and store data from two sources. When both Enable (En) inputs are LOW, the data that appears at an output is controlled by the Select (Sn) inputs, as shown in the Operating Mode table. In addition to routing data from either D0 or D1, the Select inputs can force the outputs LOW for the case where the latch is transparent (both Enables are LOW) and can steer a HIGH signal from either D0 or D1 to an output. The Select inputs can be tied together for applications requiring only that data be steered from either D0 or D1. A positive-going signal on either Enable input latches the outputs. A HIGH signal on the Master Reset (MR) input overrides all the other inputs and forces the Q outputs LOW. All inputs have 50 kΩ pull-down resistors. Features s Greater than 40% power reduction of the 100155 s 2000V ESD protection s Pin/function compatible with 100155 s Voltage compensated operating range = −4.2V to −5.7V s Available to industrial grade temperature range Ordering Code: Order Number 100355PC 100355QC 100355QI Package Number N24E V28A V28A Package Description 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Industrial Temperature Range (−40°C to +85°C) Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagrams 24-Pin DIP Pin Descriptions Pin Names E1, E2 S0, S1 MR Dna–Dnd Qa–Qd Qa–Qd Description Enable Inputs (Active LOW) Select Inputs Master Reset Data Inputs Data Outputs Complementary Data Outputs 28-Pin PLCC © 2000 Fairchild Semiconductor Corporation DS010147 www.fairchildsemi.com 100355 Operating Mode Table Controls E1 H X L L L L E2 X H L L L L S1 X X L H L H S0 X X L L H H Outputs Qn Latched (Note 1) Latched (Note 1) D0x D0x + D1x L D1x Truth Table Inputs MR H L L L L L L L L L L E1 X L L L L L L L L H X E2 X L L L L L L L L X H S1 X H H L L L H H H X X S0 X H H L L H L L L X X D1x D0x X H L X X X H X L X X X X X H L X X H L X X Outputs Qx H L H L H H L L H Qx L H L H L L H H L H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Note 1: Stores data present before E went HIGH Latched (Note 1) Latched (Note 1) Logic Diagram www.fairchildsemi.com 2 100355 Absolute Maximum Ratings(Note 2) Storage Temperature (TSTG) Maximum Junction Temperature (TJ) VEE Pin Potential to Ground Pin Input Voltage (DC) Output Current (DC Output HIGH) ESD (Note 3) −65°C to +150°C +150°C −7.0V to +0.5V VEE to +0.5V Recommended Operating Conditions Case Temperature (TC) Commercial Industrial Supply Voltage (VEE) 0°C to +85°C −40°C to +85°C −5.7V to −4.2V −50 mA ≥2000V Note 2: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 3: ESD testing conforms to MIL-STD-883, Method 3015. Commercial Version DC Electrical Characteristics (Note 4) VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = 0°C to +85°C Symbol VOH VOL VOHC VOLC VIH VIL IIL IIH Parameter Output HIGH Voltage Output LOW Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input LOW Current Input HIGH Current S0, S1 E1, E2 Dna–Dnd MR IEE Power Supply Current −87 220 350 340 430 −40 mA Inputs Open µA VIN = VIH (Max) −1165 −1830 0.50 Min −1025 −1830 −1035 −1610 −870 −1475 Typ −955 −1705 Max −870 −1620 Units mV mV mV mV mV mV µA VIN = VIH (Max) or VIL (Min) VIN = VIH (Min) or VIL (Max) Guaranteed HIGH Signal for ALL Inputs Guaranteed LOW Signal for ALL Inputs VIN = VIL (Min) Conditions Loading with 50Ω to −2.0V Loading with 50Ω to −2.0V Note 4: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guard banding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions. 3 www.fairchildsemi.com 100355 Commercial Version (Continued) DIP AC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tTLH tTHL tS Parameter Propagation Delay Dna–Dnd to Output (Transparent Mode) Propagation Delay S0, S1 to Output (Transparent Mode) Propagation Delay E1, E2 to Output Propagation Delay MR to Output Transition Time 20% to 80%, 80% to 20% Setup Time Dna–Dnd S0, S1 MR (Release Time) tH Hold Time Dna–Dnd S0, S1 tPW (L) tPW (H) Pulse Width LOW E1, E2 Pulse Width HIGH MR 0.40 0.00 2.00 2.00 0.40 0.00 2.00 2.00 0.40 0.00 2.00 2.00 ns ns Figure 2 Figure 3 ns Figure 4 0.90 1.70 1.50 0.90 1.70 1.50 0.90 1.70 1.50 Figure 3 ns Figure 4 0.80 0.80 0.60 2.00 2.30 1.40 0.80 0.80 0.60 2.00 2.30 1.40 0.80 0.80 0.60 2.10 2.30 1.40 ns ns ns Figures 1, 3 Figures 1, 2 1.00 2.60 1.00 2.60 1.20 2.70 ns Figures 1, 2 0.60 1.90 0.60 1.90 0.70 2.00 ns TC = 0°C Min Max TC = +25°C Min Max TC = +85°C Min Max Units Conditions www.fairchildsemi.com 4 100355 Commercial Version (Continued) PLCC AC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tTLH tTHL tS Parameter Propagation Delay Dna–Dnd to Output (Transparent Mode) Propagation Delay S0, S1 to Output (Transparent Mode) Propagation Delay E1, E2 to Output Propagation Delay MR to Output Transition Time 20% to 80%, 80% to 20% Setup Time Dna–Dnd S0, S1 MR (Release Time) tH Hold Time Dna–Dnd S0, S1 tPW (L) tPW (H) tOSHL Pulse Width LOW E1, E2 Pulse Width HIGH MR Maximum Skew Common Edge Output-to-Output Variation Data to Output Path tOSLH Maximum Skew Common Edge Output-to-Output Variation Data to Output Path tOST Maximum Skew Opposite Edge Output-to-Output Variation Data to Output Path tPS Maximum Skew Pin (Signal) Transition Variation Data to Output Path Note 5: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged device. The specifications apply to any outputs switching in the same direction either HIGH-to-LOW (tOSHL), or LOW-to-HIGH (tOSLH), or in opposite directions both HL and LH (tOST ). Parameters tOST and tPS guaranteed by design. TC = 0°C Min 0.60 Max 1.70 TC = +25°C Min 0.60 Max 1.70 TC = +85°C Min 0.70 Max 1.80 Units Conditions ns Figures 1, 2 1.00 2.40 1.00 2.40 1.20 2.50 ns 0.80 0.80 0.60 1.80 2.10 1.30 0.80 0.80 0.60 1.80 2.10 1.30 0.80 0.80 0.60 1.90 2.10 1.30 ns ns ns Figures 1, 3 Figures 1, 2 0.80 1.60 1.40 0.30 −0.10 2.00 2.00 330 0.80 1.60 1.40 0.30 −0.10 2.00 2.00 330 0.80 1.60 1.40 0.30 −0.10 2.00 2.00 330 ns Figure 4 Figure 3 ns Figure 4 ns ns ps Figure 2 Figure 3 PLCC only (Note 5) PLCC only 370 370 370 ps (Note 5) PLCC only 370 370 370 ps (Note 5) PLCC only 270 270 270 ps (Note 5) 5 www.fairchildsemi.com 100355 Industrial Version PLCC DC Electrical Characteristics (Note 6) VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = −40°C to +85°C TC = −40°C Symbol Parameter Min Max VOH VOL VOHC VOLC VIH VIL IIL IIH Output HIGH Voltage Output LOW Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input LOW Current Input HIGH Current S0, S1 E1, E2 Dna–Dnd MR IEE Power Supply Current −87 300 350 340 430 −40 −87 220 350 340 430 −40 mA Inputs Open µA VIN = VIH (Max) −1170 −1830 0.50 −1085 −1830 −1095 −1565 −870 −1480 −1165 1830 0.50 −870 −1575 TC = 0°C to +85°C Min −1025 −1830 −1035 −1610 −870 1475 Max −870 −1620 Units mV mV mV mV mV mV µA Conditions VIN = VIH (Max) or VIL (Min) VIN = VIH (Min) or VIL (Max) for ALL Inputs Guaranteed LOW Signal for ALL Inputs VIN = VIL (Min) Loading with 50Ω to −2.0V Loading with 50Ω to −2.0V Guaranteed HIGH Signal Note 6: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guard banding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions. PLCC AC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tTLH tTHL tS Parameter Propagation Delay Dna–Dnd to Output (Transparent Mode) Propagation Delay S0, S1 to Output (Transparent Mode) Propagation Delay E1, E2 to Output Propagation Delay MR to Output Transition Time 20% to 80%, 80% to 20% Setup Time Dna–Dnd S0, S1 MR (Release Time) tH Hold Time Dna–Dnd S0, S1 tPW (L) tPW (H) Pulse Width LOW E1, E2 Pulse Width HIGH MR 0.40 0.00 2.00 2.00 0.30 −0.10 2.00 2.00 0.30 −0.10 2.00 2.00 ns ns Figure 2 Figure 3 ns Figure 4 0.90 2.40 1.50 0.80 1.60 1.40 0.80 1.60 1.40 Figure 3 ns Figure 4 0.80 0.80 0.40 1.80 2.10 1.90 0.80 0.80 0.60 1.80 2.10 1.30 0.80 0.80 0.60 1.90 2.10 1.30 ns ns ns Figures 1, 3 Figures 1, 2 1.00 2.40 1.00 2.40 1.20 2.50 ns Figures 1, 2 0.60 1.70 0.60 1.70 0.70 1.80 ns TC = −40°C Min Max TC = +25°C Min Max TC = +85°C Min Max Units Conditions www.fairchildsemi.com 6 100355 Test Circuit Notes: VCC, VCCA = +2V, VEE = −2.5V L1 and L2 = equal length 50Ω impedance lines RT = 50Ω terminator internal to scope Decoupling 0.1 µF from GND to VCC and VEE All unused outputs are loaded with 50Ω to GND CL = Fixture and stray capacitance ≤ 3 pF Pin numbers shown are for flatpak; for DIP see logic symbol FIGURE 1. AC Test Circuit 7 www.fairchildsemi.com 100355 Switching Waveforms FIGURE 2. Enable Timing FIGURE 3. Reset Timing Notes: tS is the minimum time before the transition of the enable that information must be present at the data input. tH is the minimum time after the transition of the enable that information must remain unchanged at the data input. FIGURE 4. Data Setup and Hold Times www.fairchildsemi.com 8 100355 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide Package Number N24E 9 www.fairchildsemi.com 100355 Low Power Quad Multiplexer/Latch Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Package Number V28A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 10 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com