100397

100397 Quad Differential ECL/TTL Translating Transceiver with Latch January 1992 Revised August 2000 100397 Quad Differential ECL/TTL Translating Transceiver with Latch General Description The 100397 is a quad latched transceiver designed to convert TTL logic levels to differential F100K ECL logic levels and vice versa. This device was designed with the capability of driving a differential 25Ω ECL load with cutoff capability, and will sink a 64 mA TTL load. The 100397 is ideal for mixed technology applications utilizing either an ECL or TTL backplane. The direction of translation is set by the direction control pin (DIR). The DIR pin on the 100397 accepts F100K ECL logic levels. An ECL LOW on DIR sets up the ECL pins as inputs and TTL pins as outputs. An ECL HIGH on DIR sets up the TTL pins as inputs and ECL pins as outputs. A LOW on the output enable input pin (OE) holds the ECL output in a cut-off state and the TTL outputs at a high impedance level. A HIGH on the latch enable input (LE) latches the data at both inputs even though only one output is enabled at the time. A LOW on LE makes the latch transparent. The cut-off state is designed to be more negative than a normal ECL LOW level. This allows the output emitterfollowers to turn off when the termination supply is −2.0V, presenting a high impedance to the data bus. This high impedance reduces termination power and prevents loss of low state noise margin when several loads share the bus. The 100397 is designed with FAST TTL output buffers, featuring optimal DC drive and capable of quickly charging and discharging highly capacitive loads. All inputs have 50 KΩ pull-down resistors. Features s Differential ECL input/output structure s 64 mA FAST TTL outputs s 25Ω differential ECL outputs with cut-off s Bi-directional translation s 2000V ESD protection s Latched outputs s 3-STATE outputs s Voltage compensated operating range = −4.2V to −5.7V Ordering Code: Order Number 100397PC 100397QC 100397QI Package Number N24E V28A V28A Package Description 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Industrial Temperature Range (−40°C to +85°C) Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. FAST is a registered trademark of Fairchild Semiconductor Corporation. © 2000 Fairchild Semiconductor Corporation DS010971 www.fairchildsemi.com 100397 Logic Symbol Pin Descriptions Pin Names E0–E3 E0–E3 T0–T3 OE LE ECL Data I/O Complementary ECL Data I/O TTL Data I/O Output Enable Input (ECL Levels) Latch Enable Input (ECL Levels) Direction Control Input (ECL levels) ECL Ground ECL Output Ground ECL Ground-to-Substrate ECL Quiescent Power Supply ECL Dynamic Power Supply TTL Quiescent Ground TTL Dynamic Ground TTL Quiescent Power Supply TTL Dynamic Power Supply Description Connection Diagrams 24-Pin DIP DIR GNDECL GNDECLO GNDS VEE VEED GNDTTL GNDTTLD VTTL VTTLD All pins function at 100K ECL levels except for T0–T3. Truth Table 28-Pin PLCC LE 0 0 0 0 1 1 1 1 DIR 0 0 1 1 0 0 1 1 OE 0 1 0 1 0 1 0 1 ECL Port LOW (Cut-Off) Input LOW (Cut-Off) Output Input Latched LOW (Cut-Off) Latched X (Note 2)(Note 3) H = H IGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High Impedance Note 1: ECL input to TTL output mode. Note 2: TTL input to ECL output mode. Note 3: Retains data present before LE set HIGH. Note 4: Latch is transparent. TTL Port Z Notes Output (Note 1)(Note 4) Z Input Z X Input (Note 2)(Note 4) (Note 1)(Note 3) (Note 1)(Note 3) (Note 2)(Note 3) www.fairchildsemi.com 2 100397 Functional Diagram Note: LE, DIR, and OE use ECL logic levels Detail 3 www.fairchildsemi.com 100397 Absolute Maximum Ratings(Note 5) Storage Temperature (TSTG) Maximum Junction Temperature (TJ) VEE Pin Potential to Ground Pin VTTL Pin Potential to Ground Pin ECL Input Voltage (DC) ECL Output Current (DC Output HIGH) TTL Input Voltage (Note 7) TTL Input Current (Note 7) Voltage Applied to Output in HIGH State 3-STATE Output Current Applied to TTL Output in LOW State (Max) ESD (Note 6) twice the Rated IOL (mA) −65°C to +150°C +150°C −7.0V to +0.5V −0.5V to +6.0V VEE to +0.5V Recommended Operating Conditions Case Temperature (TC) Commercial Industrial ECL Supply Voltage (VEE) TTL Supply Voltage (VTTL) 0°C to +85°C −40°C to +85°C −5.7V to −4.2V +4.5V to +5.5V −50 mA −0.5V to +7.0V −30 mA to +5.0 mA Note 5: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 6: ESD testing conforms to MIL-STD-883, Method 3015. Note 7: Either voltage limit or current limit is sufficient to protect inputs. −0.5V to +5.5V ≥2000V Commercial Version TTL-to-ECL DC Electrical Characteristics (Note 8) VEE = −4.2V to −5.7V, GND = 0V, TC = 0°C to +85°C, VTTL = +4.5V to +5.5V Symbol VOH VOL Parameter Output HIGH Voltage Output LOW Voltage Cutoff Voltage −2000 VOHC VOLC VIH VIL IIH IBVIT IIL VFCD IEE IEEZ Output HIGH Voltage Corner Point High Output LOW Voltage Corner Point Low Input HIGH Voltage Input LOW Voltage Input HIGH Current Input HIGH Current Breakdown (I/O) Input LOW Current Input Clamp Diode Voltage VEE Supply Current VEE Supply Current −1.0 −1.2 −99 −159 −50 −90 2.0 0 −1950 mV Min −1025 −1830 Typ −955 −1705 Max −870 −1620 Units mV mV Conditions VIN = VIH(Max) or VIL(Min) Loading with 50Ω to − 2V OE and LE Low, DIR High VIN = VIH(Max) or VIL(Min), Loading with 50Ω to −2V −1035 −1610 5.0 0.8 5.0 0.5 mV mV V V µA mA mA V VIN = VIH(Min) or VIL(Max) Loading with 50Ω to −2V Over VTTL, VEE, TC Range Over VTTL, VEE, TC Range VIN = +2.7V VIN = 5.5V VIN = +0.5V IIN = −18 mA LE Low, OE and DIR HIGH Inputs Open LE and OE Low, Dir HIGH Inputs Open Note 8: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions. www.fairchildsemi.com 4 100397 Commercial Version (Continued) ECL-to-TTL DC Electrical Characteristics (Note 9) VEE = −4.2V to −5.7V, GND = 0V, TC = 0°C to +85°C, CL = 50 pF, VTTL = +4.5V to +5.5V Symbol VOH VOL VIH VIL VDIFF VCM IIH Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Voltage Differential Common Mode Voltage Input HIGH Current E0–E3, E0–E3 OE, LE, DIR ICEX IZZ IIL IOZHT IOZLT IOS ITTL Output HIGH Leakage Current Bus Drainage Test Input LOW Current 3-STATE Current Output High 3-STATE Current Output Low Output Short-Circuit Current VTTL Supply Current −650 −100 −225 39 27 39 0.50 70 240 35 50 500 µA µA µA µA µA mA mA mA mA VOUT = VTTL VOUT = 5.25V VTTL = 0.0V VIN = VIL(Min) VOUT = +2.7V VOUT = +0.5V VOUT = 0.0V, VTTL = +5.5V TTL Outputs LOW TTL Outputs HIGH TTL Outputs in 3-STATE µA VIN = VIH(Max) −1165 −1830 150 GNDECL − 2.0 GNDECL − 0.5 Min 2.7 2.4 Typ 3.1 2.9 0.3 0.5 −870 −1475 Max Units V V V mV mV mV V Conditions IOH = −3 mA, VTTL = 4.75V IOH = −3 mA, VTTL = 4.50V IOL = 24 mA, VTTL = 4.50V Guaranteed HIGH Signal for All Inputs Guaranteed LOW Signal for All Inputs Required for Full Output Swing Note 9: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions. DIP and PCC TTL-to-ECL AC Electrical Characteristics VEE = −4.2V to −5.7V, VTTL = +4.5V to +5.5V Symbol fMAX tPLH tPHL tPLH tPHL tPZH OE to En, En (Cutoff to HIGH) tPHZ OE to En, En (HIGH to Cutoff) tPHZ tS tH tTLH tTHL DIR to En, En (HIGH to Cutoff) Tn to LE Tn to LE Transition Time 20% to 80%, 80% to 20% 2.5 4.5 2.5 4.5 2.5 4.6 ns Figures 1, 3 Parameter Maximum Clock Frequency Tn to En, En (Transparent) LE to En, En TC = 0°C Min 180 0.9 1.2 2.1 2.3 Max TC = 25°C Min 180 0.8 1.3 2.2 2.4 Max T C = 8 5 °C Min 180 0.7 1.4 2.5 2.5 Max Units MHz ns ns Figures 1, 3 Figures 1, 3 Conditions 2.1 3.8 2.3 4.0 2.5 4.5 ns Figures 1, 3 2.0 0.8 0.6 0.8 3.5 2.1 0.8 0.6 3.7 2.3 0.8 0.6 4.2 ns ns ns Figures 1, 3 Figures 1, 3 Figures 1, 3 Figures 1, 3 2.8 0.8 2.8 0.8 2.8 ns 5 www.fairchildsemi.com 100397 Commercial Version (Continued) DIP and PCC ECL-to-TTL AC Electrical Characteristics VEE = −4.2V to −5.7V, VTTL = +4.5V to +5.5V, CL = 50 pF TC = 0°C Symbol Parameter Min Max fMAX tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPHZ tPLZ tS tH tPW(L) OE to Tn (Enable Time) OE to Tn (Disable Time) DIR to Tn (Disable Time) En, En to LE En, En to LE Pulse Width LE Maximum Clock Frequency En, En to Tn (Transparent) LE to Tn 75 1.7 2.2 3.3 3.2 4.9 3.6 3.4 3.5 3.4 0.6 0.7 2.0 4.9 4.0 5.2 5.6 8.3 8.6 6.9 8.1 6.8 TC = 25°C Min 75 1.7 2.2 3.4 3.3 5.1 3.5 3.5 3.5 3.4 0.6 0.7 2.0 5.1 4.0 5.4 5.7 8.5 8.3 6.7 8.1 6.7 Max TC = 85°C Min 75 1.8 2.3 3.8 3.6 5.6 3.5 3.6 3.5 3.6 0.6 0.7 2.0 5.8 4.1 6.1 6.3 9.2 7.5 6.7 7.6 6.7 Max MHz ns ns ns ns ns ns ns ns Figures 2, 4 Figures 2, 4 Figures 2, 5 Figures 2, 5 Figures 2, 6 Figures 2, 4 Figures 2, 4 Figures 2, 4 Units Conditions Industrial Version TTL-to-ECL DC Electrical Characteristics (Note 10) VEE = −4.2V to −5.7V, GND = 0V, TC = −40°C to +85°C, VTTL = +4.5V to +5.5V Symbol VOH VOL Parameter Output HIGH Voltage Output LOW Voltage Cutoff Voltage −2000 VOHC VOLC VIH VIL IIH IBVIT IIL VFCD IEE IEEZ Output HIGH Voltage Corner Point HIGH Output LOW Voltage Corner Point LOW Input HIGH Voltage Input LOW Voltage Input HIGH Current Input HIGH Current Breakdown (I/O) Input LOW Current Input Clamp Diode Voltage VEE Supply Current VEE Supply Current −1.0 −1.2 −99 −159 −40 −90 2.0 0 −1900 mV Min −1085 −1830 Typ −955 −1705 Max −870 −1575 Units mV mV Conditions VIN = VIH(Max) or VIL(Min) Loading with 50Ω to −2V OE and LE LOW, DIR HIGH VIN= VIH(Max) or VIL(Min), Loading with 50Ω to −2V −1095 −1565 5.0 0.8 5.0 0.5 mV mV V V µA mA mA V VIN = VIH(Min) or VIL(Max) Loading with 50Ω to −2V Over VTTL, VEE, TC Range Over VTTL, VEE, TC Range VIN = +2.7V VIN = 5.5V VIN = +0.5V IIN = −18 mA LE Low, OE and DIR HIGH Inputs Open LE and OE LOW, Dir HIGH Inputs Open Note 10: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions. www.fairchildsemi.com 6 100397 Industrial Version (Continued) ECL-to-TTL DC Electrical Characteristics (Note 11) VEE = −4.2V to −5.7V, GND = 0V, TC = −40°C to +85°C, CL = 50 pF, VTTL = +4.5V to +5.5V Symbol VOH VOL VIH VIL VDIFF VCM IIH Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Voltage Differential Common Mode Voltage Input HIGH Current E0–E3, E0–E3 OE, LE, DIR ICEX IZZ IIL IOZHT IOZLT IOS ITTL Output HIGH Leakage Current Bus Drainage Test Input LOW Current 3-STATE Current Output HIGH 3-STATE Current Output LOW Output Short-Circuit Current VTTL Supply Current −650 −100 −225 39 27 39 0.50 70 300 35 50 500 µA µA µA µA µA mA mA mA mA VOUT = VTTL VOUT = 5.25V VTTL = 0.0V VIN = VIL(Min) VOUT = +2.7V VOUT = +0.5V VOUT = 0.0V, VTTL = +5.5V TTL Outputs LOW TTL Outputs HIGH TTL Outputs in 3-STATE µA −1170 −1830 150 GNDECL − 2.0 GNDECL − 0.5 Min 2.7 2.4 Typ 3.1 2.9 0.3 0.5 −870 −1480 Max Units V V V mV mV mV V VIN = VIH(Max) Conditions IOH = −3 mA, VTTL = 4.75V IOH = −3 mA, VTTL = 4.50V IOL = 24 mA, VTTL = 4.50V Guaranteed HIGH Signal for All Inputs Guaranteed LOW Signal for All Inputs Required for Full Output Swing Note 11: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions. PCC TTL-to-ECL AC Electrical Characteristics VEE = −4.2V to −5.7V, VTTL = +4.5V to +5.5V Symbol fMAX tPLH tPHL tPLH tPHL tPZH OE to En, En (Cutoff to HIGH) tPHZ OE to En, En (HIGH to Cutoff) tPHZ tS tH tTLH tTHL DIR to En, En (HIGH to Cutoff) Tn to LE Tn to LE Transition Time 20% to 80%, 80% to 20% 1.9 3.8 2.5 4.5 2.5 4.6 ns Figures 1, 3 Parameter Maximum Clock Frequency Tn to En, En (Transparent) LE to En, En TC = −40°C Min 180 0.9 1.2 2.4 2.3 Max TC = +25°C Min 180 0.8 1.3 2.2 2.4 Max TC = +85°C Min 180 0.7 1.4 2.5 2.5 Max Units MHz ns ns Figures 1, 3 Figures 1, 3 Conditions 2.5 4.7 2.3 4.0 2.5 4.5 ns Figures 1, 3 1.8 0.8 0.6 0.8 3.5 2.1 0.8 0.6 3.7 2.3 0.8 0.6 4.2 ns ns ns Figures 1, 3 Figures 1, 3 Figures 1, 3 Figures 1, 3 2.8 0.8 2.8 0.8 2.8 ns 7 www.fairchildsemi.com 100397 Industrial Version (Continued) PCC ECL-to-TTL AC Electrical Characteristics VEE = −4.2V to −5.7V, VTTL = +4.5V to +5.5V, CL = 50 pF TC = −40°C Symbol Parameter Min Max fMAX tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPHZ tPLZ tS tH tPW(L) OE to Tn (Enable Time) OE to Tn (Disable Time) DIR to Tn (Disable Time) En, En to LE En, En to LE Pulse Width LE Maximum Clock Frequency En, En to Tn (Transparent) LE to Tn 75 1.7 2.2 3.3 3.1 4.8 3.5 3.2 3.5 3.2 0.6 0.7 2.0 4.9 4.3 5.2 5.6 8.3 9.2 7.3 8.8 7.2 TC = +25°C Min 75 1.7 2.2 3.4 3.3 5.1 3.5 3.5 3.5 3.4 0.6 0.7 2.0 5.1 4.0 5.4 5.7 8.5 8.3 6.7 8.1 6.7 Max TC = +85°C Min 75 1.8 2.3 3.8 3.6 5.6 3.5 3.6 3.5 3.6 0.6 0.7 2.0 5.8 4.1 6.1 6.3 9.2 7.5 6.7 7.6 6.7 Max MHz ns ns ns ns ns ns ns ns Figures 2, 4 Figures 2, 4 Figures 2, 5 Figures 2, 5 Figures 2, 6 Figures 2, 4 Figures 2, 4 Figures 2, 4 Units Conditions www.fairchildsemi.com 8 100397 Test Circuitry (TTL-to-ECL) Notes: Rt = 50Ω termination. When an input or output is being monitored by a scope, Rt is supplied by the scope’s 50Ω resistance. When an input or output is not being monitored, and external 50Ω resistance must be applied to serve as Rt. TTL and ECL force signals are brought to the DUT via 50Ω coax lines. VTTL is decoupled to ground with 0.1 µF to ground, VEE is decoupled to ground with 0.01 µF and GND is connected to ground. For ECL input pins, the equivalent force/sense circuitry is optional. FIGURE 1. TTL-to-ECL AC Test Circuit Switching Waveforms (TTL-to-ECL) FIGURE 2. TTL to ECL Transition—Propagation Delay and Transition Times 9 www.fairchildsemi.com 100397 Test Circuitry (ECL-to-TTL) Notes: Rt = 50Ω termination. When an input or output is being monitored by a scope, Rt is supplied by the scope’s 50Ω resistance. When an input or output is not being monitored, and external 50Ω resistance must be applied to serve as Rt. The TTL 3-STATE pull up switch is connected to +7V only for ZL and LZ tests. TTL and ECL force signals are brought to the DUT via 50Ω coax lines. VTTL is decoupled to ground with 0.1 µF to ground, V EE is decoupled to ground with 0.01 µF and GND is connected to ground. FIGURE 3. ECL-to-TTL AC Test Circuit Note: DIR is LOW, and OE is HIGH FIGURE 4. ECL-to-TTL Transition—Propagation Delay and Transition Times www.fairchildsemi.com 10 100397 Test Circuitry (ECL-to-TTL) (Continued) Note: DIR is LOW, LE is HIGH Note: OE is HIGH, LE is HIGH FIGURE 5. ECL-to-TTL Transition, OE to TTL Output, Enable and Disable Times FIGURE 6. ECL-to-TTL Transition, DIR to TTL Output, Disable Time Applications FIGURE 7. Applications Diagram—MOS/TTL SRAM Interface Using 100397 ECL–TTL Latched Translator 11 www.fairchildsemi.com 100397 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide Package Number N24E www.fairchildsemi.com 12 100397 Quad Differential ECL/TTL Translating Transceiver with Latch Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Package Number V28A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 13 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com www.fairchildsemi.com