29F53

29F52•29F53 8-Bit Registered Transceiver April 1988 Revised August 1999 29F52•29F53 8-Bit Registered Transceiver General Description The 29F52 and 29F53 are 8-bit registered transceivers. Two 8-bit back to back registers store data flowing in both directions between two bidirectional buses. Separate clock, clock enable and 3-STATE output enable signals are provided for each register. The A0–A7 output pins are guaranteed to sink 24 mA while the B0–B7 output pins are designed for 64 mA. The 29F53 is an inverting option of the 29F52. Both transceivers are AMD Am2952/2953 functional equivalents. Features s 8-bit registered transceivers s Separate clock, clock enable and 3-STATE output enable provided for each register s AMD Am2952/2953 functional equivalents s Both inverting and non-inverting options available s 24-Pin slimline package Ordering Code: Order Number 29F52SC 29F52SPC 29F53SPC Package Number M24B N24C N24C Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols 29F52 29F53 IEEE/IEC 29F52 IEEE/IEC 29F53 © 1999 Fairchild Semiconductor Corporation DS009606 www.fairchildsemi.com 29F52•29F53 Connection Diagrams Pin Assignment for DIP and SOIC 29F52 Pin Assignment for DIP 29F53 Unit Loading/Fan Out Pin Names A0–A7 B0–B7 OEA CPA CEA OEB CPB CEB Description A-Register Inputs/ B-Register 3-STATE Outputs B Register Inputs/ A-Register 3-STATE Outputs Output Enable A-Register A-Register Clock A-Register Clock Enable Output Enable B-Register B-Register Clock B-Register Clock Enable U.L. HIGH/LOW 3.5/1.083 150/40 (33.3) 3.5/1.083 600/106.6 (80) 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 Input IIH/IIL Output IOH/IOL 70 µA/0.65 mA −3 mA/24 mA (20 mA) 70 µA/0.65 mA −12 mA/64 mA (48 mA) 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA Output Control OE H L L Internal Q X L H Y-Output 29F52 29F53 Z L H Z H L Function Register Function Table (Applies to A or B Register) Inputs D Disable Outputs Enable Outputs X L H CP X N N CE H L L Internal Q NC L H Function Hold Data Load Data H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = HIGH Impedance N = LOW-to-HIGH Transition NC = No Change www.fairchildsemi.com 2 29F52•29F53 Block Diagrams 29F52 3 www.fairchildsemi.com 29F52•29F53 Block Diagrams (continued) 29F53 www.fairchildsemi.com 4 29F52•29F53 Absolute Maximum Ratings(Note 1) Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output 3-STATE Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA) −0.5V to VCC −0.5V to +5.5V −65°C to +150°C −55°C to +125°C −55°C to +150°C −0.5V to +7.0V −0.5V to +7.0V −30 mA to +5.0 mA Recommended Operating Conditions Free Air Ambient Temperature Supply Voltage 0°C to +70°C +4.5V to +5.5V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol VIH VIL VCD VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 10% VCC 10% VCC 10% VCC 5% VCC 5% VCC VOL IIH IBVI IBVIT IIL IIH + IOZH IIL + IOZL IOS ICEX IZZ ICCH ICCL ICCZ Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Input HIGH Current Breakdown Test (I/O) Input LOW Current Output Leakage Current Output Leakage Current Output Short-Circuit Current Output HIGH Leakage Current Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current 130 −60 −100 10% VCC 10% VCC 2.5 2.4 2.0 2.7 2.7 0.5 0.55 20 100 1.0 −0.6 70 −650 −150 −225 250 500 190 190 190 µA µA mA mA mA Max 0.0V Max Max Max V µA µA mA mA µA µA mA Min Max Max Max Max Max Max Max V Min Min 2.0 0.8 −1.2 Typ Max Units V V V Min VCC Conditions Recognized as a HIGH Signal Recognized as a LOW Signal IIN = −18 mA (Non I/O Pins) IOH = −1 mA (An) IOH = −3 mA (An, Bn) IOH = −15 mA (Bn) IOH = −1 mA (An) IOH = −3 mA (An, Bn) IOL = 24 mA (A n) IOL = 64 mA (B n) VIN = 2.7V (Non-I/O Pins) VIN = 7.0V (Non-I/O Pins) VIN = 5.5V (An, Bn) VIN = 0.5V (Non-I/O Pins) VOUT = 2.7V (An, Bn) VOUT = 0.5V (An, Bn) VOUT = 0V (An) VOUT = 0V (Bn) VOUT = VCC (An, Bn) VOUT = 5.25V (An, B n) VO = HIGH VO = LOW VO = HIGH Z 5 www.fairchildsemi.com 29F52•29F53 AC Electrical Characteristics TA = +25°C Symbol Parameter Min tPLH tPHL tPZH tPZL tPHZ tPLZ Propagation Delay CPA or CPB to An or Bn Output Enable Time OEA or OEB to An or Bn Output Disable Time OEA or OEB to An or Bn 3.0 4.0 2.5 3.5 2.5 2.5 VCC = +5.0V CL = 50 pF Typ 5.5 7.0 5.5 7.0 6.5 5.5 Max 7.5 9.0 7.5 9.5 9.0 7.5 TA = −55°C to +125°C VCC = +5.0V CL = 50 pF Min Max TA = 0°C to +70°C VCC = +5.0V CL = 50 pF Min 2.5 3.5 2.0 3.0 2.0 2.0 Max 8.5 10.0 8.5 10.5 10.0 8.5 ns ns Units ns AC Operating Requirements TA = +25°C Symbol Parameter VCC = +5.0V Min tS(H) tS(L) tH(H) tH(L) tS(H) tS(L) tH(H) tH(L) tW(H) tW(L) Setup Time, HIGH or LOW An or Bn to CPA or CPB Hold Time, HIGH or LOW An or Bn to CPA or CPB Setup Time, HIGH or LOW CEA or CEB to CPA or CPB Hold Time, HIGH or LOW CEA or CEB to CPA or CPB Pulse Width, HIGH or LOW CPA or CPB 4.0 4.0 2.0 2.0 1.0 4.0 2.0 2.0 3.0 3.0 Max TA = −55°C to +125°C VCC = +5.0V Min Max TA = 0°C to +70°C VCC = +5.0V Min 4.5 4.5 2.5 2.5 1.5 4.5 2.5 2.5 3.5 3.5 Max ns ns ns Units ns ns www.fairchildsemi.com 6 29F52•29F53 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B 7 www.fairchildsemi.com 29F52•29F53 8-Bit Registered Transceiver Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide Package Number N24C Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 8 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com