74ABT16652

74ABT16652 16-Bit Transceivers and Registers with 3-STATE Outputs April 1993 Revised January 1999 74ABT16652 16-Bit Transceivers and Registers with 3-STATE Outputs General Description The ABT16652 consists of sixteen bus transceiver circuits with D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Each byte has separate control inputs which can be shorted together for full 16-bit operation. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to HIGH logic level. Output Enable pins (OEAB, OEBA) are provided to control the transceiver function. Features s Independent registers for A and B buses s Multiplexed real-time and stored data s Separate control logic for each byte s A and B output sink capability of 64 mA, source capability of 32 mA s Guaranteed output skew s High impedance glitch free bus loading during entire power up and power down cycle s Nondestructive hot insertion capability Ordering Code: Order Number 74ABT16652CSSC 74ABT16652CMTD Package Number MS56A MTD56 Package Description 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Pin Descriptions Pin Names A0–A16 Descriptions Data Register A Inputs/ 3-STATE Outputs B0–B16 Data Register B Inputs/ 3-STATE Outputs CPABn, CPBAn SABn, SBAn OEABn, OEBAn Clock Pulse Inputs Select Inputs Output Enable Inputs Connection Diagram © 1999 Fairchild Semiconductor Corporation DS011599.prf www.fairchildsemi.com 74ABT16652 Functional Description In the transceiver mode, data present at the HIGH impedance port may be stored in either the A or B register or both. The select (SABn, SBAn) controls can multiplex stored and real-time. The examples in Figure 1 demonstrate the four fundamental bus-management functions that can be performed with the ABT16652. Data on the A or B data bus, or both can be stored in the internal D flip-flop by LOW to HIGH transitions at the appropriate Clock Inputs (CPABn, CPBAn) regardless of the Select or Output Enable Inputs. When SAB and SBA are in the real time transfer mode, it is also possible to store data without using the internal D flip-flops by simultaneously enabling OEABn and OEBAn. In this configuration each Output reinforces its Input. Thus when all other data sources to the two sets of bus lines are in a HIGH impedance state, each set of bus lines will remain at its last state. Note A: Real-Time Transfer Bus B to Bus A Note C: Storage OEAB OEBA CPAB CPBA SAB SBA OEAB OEBA CPAB CPBA SAB 1 1 1 1 1 SBA 1 1 1 X L L H X H L L X X X L Note B: Real-Time Transfer Bus A to Bus B    1 1 1 1 X X X X X X X X Note D: Transfer Storage Data to A or B OEAB OEBA CPAB CPBA SAB 1 1 1 1 1 SBA 1 H H X X L X OEAB OEBA CPAB1 CPBA SAB SBA 1 1 1 1 1 H FIGURE 1. L H or L H or L H H www.fairchildsemi.com 2 74ABT16652 Function Table Inputs OEAB1 OEBA1 L L X H L L L L H H H H H H H X L L L H H L CPAB1 CPBA1 SAB1 SBA1 H or L Inputs/Outputs (Note 1) A0 thru A7 Input Input Input Output Output B0 thru B7 Input Isolation Store A and B Data Not Specified Store A, Hold B Output Input Input Store A in Both Registers Hold A, Store B Store B in Both Registers Real-Time B Data to A Bus Store B Data to A Bus Input Output Output Output Real-Time A Data to B Bus Stored A Data to B Bus Stored A Data to B Bus and Stored B Data to A Bus H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW to HIGH Clock Transition Operating Mode H or L X     X X H or L H or L     X X X X X X X X X X X L H H X X X X X X L H X X H Not Specified Input H or L H or L H or L H or L  Note 1: The data output functions may be enabled or disabled by various signals at OEAB or OEBA inputs. Data input functions are always enabled, i.e., data at the bus pins will be stored on every LOW to HIGH transition on the clock inputs. This also applies to data I/O (A and B: 8–15) and #2 control pins. Logic Diagrams Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 www.fairchildsemi.com 74ABT16652 Absolute Maximum Ratings(Note 2) Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 3) Input Current (Note 3) Voltage Applied to Any Output in the Disable or Power-Off State in the HIGH State Current Applied to Output in LOW State (Max) DC Latchup Source Current twice the rated IOL (mA) −500 mA −0.5V to +5.5V −0.5V to VCC −0.5V to +7.0V −0.5V to +7.0V −30 mA to +5.0 mA −65°C to +150°C −55°C to +125°C −55°C to +150°C Over Voltage Latchup (I/O) 10V Recommended Operating Conditions Free Air Ambient Temperature Supply Voltage Minimum Input Edge Rate (∆V/∆t) Data Input Enable Input Clock Input 50 mV/ns 20 mV/ns 100 mV/ns −40°C to +85°C +4.5V to +5.5V Note 2: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 3: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol VIH VIL VCD VOH VOL VID IIH IBVI IBVIT IIL IIH + IOZH IIL + IOZL IOS ICEX IZZ ICCH ICCL ICCZ ICCT ICCD Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input Leakage Test Input HIGH Current Input HIGH Current Breakdown Test Input HIGH Current Breakdown Test (I/O) Input LOW Current Output Leakage Current −1 −1 10 −10 −275 50 100 1.0 60 1.0 2.5 No Load 0.23 µA µA mA µA µA mA mA mA mA mA/MHz 0V–5.5V µA Max VIN = 0.5V (Non-I/O Pins) (Note 4) VIN = 0.0V (Non-I/O Pins) VOUT = 2.7V (An, Bn); OEABn = GND and OEBAn = 2.0V Output Leakage Current 0V–5.5V VOUT = 0.5V (An, Bn); OEABn = GND and OEBAn = 2.0V Output Short-Circuit Current Output HIGH Leakage Current Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current Additional ICC/Input Dynamic ICC (Note 4) Max Max 0.0V Max Max Max Max Max VOUT = 0V (An, Bn) VOUT = VCC (An, Bn) VOUT = 5.5V (An, Bn); All Others GND All Outputs HIGH All Outputs LOW Outputs 3-STATE; All Others at VCC or GND VI = VCC − 2.1V All Others at VCC or GND Outputs Open OEABn, OEBAn and SEL = GND Non-I/O = GND or VCC One bit toggling, 50% duty cycle Note 4: Guaranteed but not tested. Min Typ Max Units V VCC Conditions Recognized HIGH Signal Recognized LOW Signal 0.8 −1.2 2.5 2.0 0.55 V V V V V Min Min Min 0.0 Max Max Max IIN = −18 mA (Non I/O Pins) IOH = −3 mA, (An, Bn) IOH = −32 mA, (A n, Bn) IOL = 64 mA, (A n, Bn) IID = 1.9 µA, (Non-I/O Pins) All Other Pins Grounded VIN = 2.7V (Non-I/O Pins) (Note 4) VIN = VCC (Non-I/O Pins) VIN = 7.0V (Non-I/O Pins) VIN = 5.5V (An, Bn) 1 1 7 100 µA µA µA www.fairchildsemi.com 4 74ABT16652 DC Electrical Characteristics (SSOP Package) Symbol VOLP VOLV VOHV VIHD VILD Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum HIGH Level Dynamic Output Voltage Minimum HIGH Level Dynamic Input Voltage Maximum LOW Level Dynamic Input Voltage −1.4 2.5 2.0 Min Typ 0.7 −1.0 3.0 1.6 1.2 0.8 Max 1.2 Units V V V V V VCC 5.0 5.0 5.0 5.0 5.0 Conditions CL = 50 pF, RL = 500Ω TA = 25°C (Note 5) TA = 25°C (Note 5) TA = 25° (Note 6) TA = 25°C (Note 7) TA = 25°C (Note 7) Note 5: M ax number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested. Note 6: M ax number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested. Note 7: Max number of data inputs (n) switching. n − 1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD). Guaranteed, but not tested. AC Electrical Characteristics (SSOP Package) TA = +25°C Symbol Parameter Min tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Propagation Delay Clock to Bus Propagation Delay Bus to Bus Propagation Delay SBAn or SABn to An to Bn Enable Time OEBAn or OEABn to An or Bn Disable Time OEBAn or OEABn to An or Bn 1.5 1.5 3.9 3.3 5.9 5.9 1.5 1.5 5.9 5.9 ns 1.5 1.5 2.8 3.0 5.5 5.5 1.5 1.5 5.5 5.5 ns 1.5 1.5 1.5 1.5 1.5 1.5 V CC = +5.0V CL = 50 pF Typ 3.0 3.4 2.6 3.0 2.9 3.2 Max 4.9 4.9 4.5 4.5 5.0 5.0 1.5 1.5 1.5 1.5 1.5 1.5 TA = −40°C to +85°C VCC = 4.5V–5.5V CL = 50 pF Min Max 4.9 4.9 4.5 4.5 5.0 5.0 ns ns ns Units AC Operating Requirements TA = +25°C Symbol Parameter Min fmax tS(H) tS(L) tH(H) tH(L) tW(H) tW(L) Max Clock Frequency Setup Time, HIGH or LOW Bus to Clock Hold Time, HIGH or LOW Bus to Clock Pulse Width, HIGH or LOW 3.0 3.0 ns 1.0 1.0 ns 2.0 V CC = +5.0V CL = 50 pF Typ 200 2.0 Max TA = −40°C to +85°C VCC = 4.5V–5.5V CL = 50 pF Min Max MHz ns Units 5 www.fairchildsemi.com 74ABT16652 Extended AC Electrical Characteristics (SSOP Package) TA = −40°C to +85°C VCC = 4.5V–5.5V Symbol Parameter CL = 50 pF 16 Outputs Switching (Note 8) Min tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Progagation Delay Clock to Bus Progagation Delay Bus to Bus Progagation Delay SBA or SAB to An or Bn Output Enable Time OEBAn or OEABn to An or Bn Output Disable Time OEBA or OEAB to An or Bn Note 8: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.). Note 9: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. This specification pertains to single output switching only. Note 10: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. Note 11: The 3-STATE delay times are dominated by the RC network (500Ω, 250 pF) on the output and has been excluded from the datasheet. TA = −40°C to +85°C VCC = 4.5V–5.5V CL = 250 pF 1 Output Switching (Note 9) Min 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 Max 7.5 7.5 7.0 7.0 7.5 7.5 8.0 8.0 TA = −40°C to +85°C VCC = 4.5V–5.5V CL = 250 pF 16 Outputs Switching (Note 10) Min 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 Max 10.0 10.0 9.5 9.5 10.0 10.0 10.5 10.5 ns ns ns ns Units Max 5.8 5.8 6.5 6.5 6.0 6.0 6.0 6.0 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 6.0 6.0 (Note 11) (Note 11) ns Skew (Note 12) (SSOP Package) TA = −40°C to +85°C VCC = 4.5V–5.5V Symbol Parameter CL = 50 pF 16 Outputs Switching (Note 12) Max tOSHL (Note 14) tOSLH (Note 14) tPS (Note 15) tOST (Note 14) tPV (Note 16) Pin to Pin Skew HL Transitions Pin to Pin Skew LH Transitions Duty Cycle LH–HL Skew Pin to Pin Skew LH/HL Transitions Device to Device Skew LH/HL Transitions 3.5 4.0 ns 2.8 3.0 ns 2.0 2.5 2.0 2.5 ns 2.0 TA = −40°C to +85°C VCC = 4.5V–5.5V CL = 250 pF 16 Outputs Switching (Note 13) Max 2.5 ns Units Note 12: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.). Note 13: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. Note 14: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device. The specification applies to any outputs switching HIGH to LOW (tOSHL), LOW to HIGH (tOSLH), or any combination switching LOW to HIGH and/or HIGH to LOW (tOST). This specification is guaranteed but not tested. Note 15: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested. Note 16: Propagation delay variation for a given set of conditions (i.e., temperature and VCC) from device to device. This specification is guaranteed but not tested. www.fairchildsemi.com 6 74ABT16652 Capacitance Symbol CIN CI/O (Note 17) Parameter Input Capacitance I/O Capacitance Typ 5.0 11.0 Units pF pF Conditions (TA = 25°C) V CC = 0V (non I/O pins) V CC = 5.0V (An, Bn) Note 17: CI/O is measured at frequency, f = 1 MHz, per MIL-STD-883, Method 3012. AC Loading *Includes jig and probe capacitance FIGURE 2. Standard AC Test Load FIGURE 3. Test Input Signal Levels Input Pulse Requirement Amplitude 3.0V Rep. Rate 1 MHz tW 500 ns tr 2.5 ns tf 2.5 ns FIGURE 4. Test input Signal Requirements AC Waveforms FIGURE 5. Propagation Delay Waveforms for Inverting and Non-Inverting Functions FIGURE 7. 3-STATE Output HIGH and LOW Enable and Disable Times FIGURE 6. Propagation Delay, Pulse Width Waveforms FIGURE 8. Setup Time, Hold Time and Recovery Time Waveforms 7 www.fairchildsemi.com 74ABT16652 Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide Package Number MS56A www.fairchildsemi.com 8 74ABT16652 16-Bit Transceivers and Registers with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD56 LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.