74ABT2952

74ABT2952 Octal Registered Transceiver January 1992 Revised November 1999 74ABT2952 Octal Registered Transceiver General Description The ABT2952 is an octal registered transceiver. Two 8-bit back to back registers store data flowing in both directions between two bidirectional buses. Separate clock, clock enable and 3-STATE output enable signals are provided for each register. The output pins are guaranteed to source 32 mA and to sink 64 mA. Features s Separate clock, clock enable and 3-STATE output enable provided for each register s A and B output sink capability of 64 mA source capability of 32 mA s Guaranteed output skew s Guaranteed multiple output switching specifications s Output switching specified for both 50 pF and 250 pF loads s Guaranteed simultaneous switching noise level and dynamic threshold performance s Guaranteed latchup protection s High impedance glitch free bus loading during entire power up and power down cycle s Nondestructive hot insertion capability Ordering Code: Order Number 74ABT2952CSC 74ABT2952CMSA 74ABT2952CMTC Package Number M24B MSA24 MTC24 Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body 24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names A0–A7 Description A-Register Inputs/B-Register 3-STATE Outputs B0–B7 B-Register Inputs/A-Register 3-STATE Outputs OEA CPA CEA OEB CPB CEB Output Enable A-Register A-Register Clock A-Register Clock Enable Output Enable B-Register B-Register Clock B-Register Clock Enable © 1999 Fairchild Semiconductor Corporation DS010969 www.fairchildsemi.com 74ABT2952 Truth Table Output Control Internal OE Q H L L X L H Z L H Disable Outputs Enable Outputs Output Function D X L H Register Function Table (Applies to A or B Register) Inputs CP CE H L L Internal Function Q NC L H Hold Data Load Data   X H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = HIGH Impedance = LOW-to-HIGH Transition NC = No Change  Block Diagram www.fairchildsemi.com 2 74ABT2952 Absolute Maximum Ratings(Note 1) Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Any Output in the Disable or Power-Off State in the HIGH State Current Applied to Output in LOW State (Max) DC Latchup Source Current Over Voltage Latchup (I/O) twice the rated IOL (mA) −500 mA 10V −0.5V to +5.5V −0.5V to VCC −65°C to +150°C −55°C to +125°C −55°C to +150°C −0.5V to +7.0V −0.5V to +7.0V −30 mA to +5.0 mA Recommended Operating Conditions Free Air Ambient Temperature Supply Voltage Minimum Input Edge Rate (∆V/∆t) Data Input Enable Input Clock Input 50 mV/ns 20 mV/ns 100 mV/ns −40°C to +85°C +4.5V to +5.5V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol VIH VIL VCD VOH VOL VID IIH IBVI IBVIT IIL Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input Leakage Test Input HIGH Current Input HIGH Current Breakdown Test Input HIGH Current Breakdown Test (I/O) Input LOW Current 4.75 1 1 7 100 −1 −1 IIH + IOZH Output Leakage Current IIL + IOZL IOS ICEX IZZ ICCH ICCL ICCZ ICCT ICCD Output Leakage Current −100 10 −10 −275 50 100 250 30 50 2.5 No Load 0.18 2.5 2.0 0.55 V V Min 0.0 Min 2.0 0.8 −1.2 Typ Max Units V V V Min VCC Conditions Recognized HIGH Signal Recognized LOW Signal IIN = −18 mA (Non I/O Pins) IOH = −3 mA (An, Bn) IOH = −32 mA (An, Bn) IOL = 64 mA (An, B n) IID = 1.9 µA (Non-I/O Pins) All Other Pins Grounded µA µA µA µA µA µA mA µA µA µA mA µA mA mA/MHz Max Max Max Max VIN = 2.7V (Non-I/O Pins) (Note 3) VIN = VCC (Non-I/O Pins) VIN = 7.0V (Non-I/O Pins) VIN = 5.5V (An, Bn) VIN = 0.5V (Non-I/O Pins) (Note 3) VIN = 0.0V (Non-I/O Pins) OEA or OEB = 2.0V 0V–5.5V VOUT = 0.5V (An, Bn); OEA or OEB = 2.0V Output Short-Circuit Current Output HIGH Leakage Current Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current Additional ICC/Input Dynamic ICC (Note 4) Max Max 0.0V Max Max Max Max Max VOUT = 0V (An, Bn) VOUT = VCC (An, Bn) VOUT = 5.5V (An, Bn); All Others GND All Outputs HIGH All Outputs LOW Outputs 3-STATE; All Others GND VI = VCC − 2.1V; All Others at VCC or GND Outputs Open OEA or OEB = GND, Non-I/O = GND or VCC One Bit toggling, 50% duty cycle (Note 4) Note 3: Guaranteed, but not tested. Note 4: For 8-bit toggling, ICCD < 1.4 mA/MHz. 0V–5.5V VOUT = 2.7V (An, Bn); 3 www.fairchildsemi.com 74ABT2952 DC Electrical Characteristics (SOIC Package) Conditions Symbol Parameter Min Typ Max Units VCC 5.0 5.0 5.0 5.0 5.0 CL = 50 pF, RL = 500Ω VOLP VOLV VOHV VIHD VILD Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum HIGH Level Dynamic Output Voltage Minimum HIGH Level Dynamic Input Voltage Maximum LOW Level Dynamic Input Voltage −1.2 2.5 2.0 0.6 −1.0 3.0 1.7 1.2 0.8 0.8 V V V V V TA = 25°C (Note 5) TA = 25°C (Note 5) TA = 25°C (Note 6) TA = 25°C (Note 7) TA = 25°C (Note 7) Note 5: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output at Low. Guaranteed, but not tested. Note 6: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested. Note 7: M ax number of data inputs (n) switching. n − 1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD ). Guaranteed, but not tested. AC Electrical Characteristics (SOIC and SSOP Package) TA = +25°C Symbol Parameter Min fMAX tPLH tPHL tPZH tPZL tPHZ tPLZ Maximum Clock Frequency Propagation Delay CPA or CPB to An or Bn Output Enable Time OEA or OEB to An or Bn Output Disable Time OEA or OEB to An or Bn 1.5 1.5 3.6 3.2 6.0 6.0 1.5 1.5 6.0 6.0 ns 1.5 1.5 3.2 3.5 5.5 5.5 1.5 1.5 5.5 5.5 ns 200 1.5 1.5 3.4 3.6 5.3 5.3 VCC = +5.0V CL = 50 pF Typ Max TA = −40°C to +85°C VCC = 4.5V to 5.5V CL = 50 pF Min 200 1.5 1.5 5.3 5.3 Max MHz ns Units AC Operating Requirements TA = +25°C Symbol Parameter VCC = +5.0V CL = 50 pF Min tS(H) ts(L) tH(H) tH(L) tS(H) tS(L) tH(H) tH(L) tW(H) tW(L) Setup Time, HIGH or LOW An or Bn to CPA or CPB Hold Time, HIGH or LOW An or Bn to CPA or CPB Setup Time, HIGH or LOW CEA or CEB to CPA or CPB Hold Time, HIGH or LOW CEA or CEB to CPA or CPB Pulse Width, HIGH or LOW CPA or CPB 3.0 3.0 3.0 3.0 ns 1.5 1.5 1.5 1.5 ns 2.5 2.5 2.5 2.5 ns 1.5 1.5 1.5 1.5 ns 2.5 2.5 Max Min 2.5 2.5 TA = −40°C to +85°C VCC = 4.5V to 5.5V CL = 50 pF Max ns Units www.fairchildsemi.com 4 74ABT2952 Extended AC Electrical Characteristics (SOIC Package) TA = −40°C to +85°C VCC = 4.5V to 5.5V Symbol Parameter CL = 50 pF 8 Outputs Switching (Note 8) Min tPLH tPHL tPZH tPZL tPHZ tPZL Propagation Delay CPA or CPB to An or Bn Output Enable Time OEA or OEB to An or Bn Output Disable Time OEA or OEB to An or Bn 1.5 1.5 1.5 1.5 1.5 1.5 Max 6.0 6.0 6.0 6.0 6.0 6.0 Min 2.0 2.0 2.0 2.0 (Note 11) Max 8.0 8.0 8.0 8.0 2.5 2.5 2.5 2.5 TA = −40°C to +85°C VCC = 4.5V to 5.5V CL = 250 pF (Note 9) TA = −40°C to +85°C VCC = 4.5V to 5.5V CL = 250 pF 8 Outputs Switching (Note 10) Min Max 10.5 10.5 11.5 11.5 (Note 11) ns ns Units ns Note 8: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.). Note 9: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. This specification pertains to single output switching only. Note 10: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. Note 11: The 3-STATE delays are dominated by the RC network (500Ω, 250 pF) on the output and has been excluded from the datasheet. Skew (SOIC Package) TA = −40°C to +85°C VCC = 4.5V–5.5V Symbol Parameter CL = 50 pF 8 Outputs Switching (Note 12) Max tOSHL (Note 14) tOSLH (Note 14) tPS (Note 15) tOST (Note 14) tPV (Note 16) Pin to Pin Skew HL Transitions Pin to Pin Skew LH Transitions Duty Cycle LH–HL Skew Pin to Pin Skew LH/HL Transitions Device to Device Skew LH/HL Transitions 1.0 1.0 2.0 2.1 2.5 TA = −40°C to +85°C VCC = 4.5V–5.5V CL = 250 pF 8 Outputs Switching (Note 13) Max 1.5 2.0 4.5 4.5 5.0 ns ns ns ns ns Units Note 12: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.). Note 13: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. Note 14: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device. The specification applies to any outputs switching HIGH-to-LOW (tOSHL), LOW to HIGH (tOSLH), or any combination switching LOW-to-HIGH and/or HIGH-toLOW (tOST ). This specification is guaranteed but not tested. Note 15: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested. Note 16: Propagation delay variation for a given set of conditions (i.e., temperature and VCC) from device to device. This specification is guaranteed but not tested. Capacitance Symbol CIN CI/O (Note 17) Parameter Input Capacitance Output Capacitance Typ 5 11 Units pF pF Conditions TA = 25°C VCC = 0V (Non I/O Pins) VCC = 5.0V (An, Bn) Note 17: CI/O is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012. 5 www.fairchildsemi.com 74ABT2952 AC Loading *Includes jig and probe capacitance FIGURE 1. Standard AC Test Load FIGURE 2. Test Input Signal Levels Amplitude 3.0V Rep. Rate 1 MHz tW 500 ns tr 2.5 ns tf 2.5 ns FIGURE 3. Input Signal Requirements AC Waveforms FIGURE 4. Propagation Delay Waveforms for Inverting and Non-Inverting Functions FIGURE 6. 3-STATE Output HIGH and LOW Enable and Disable Times FIGURE 5. Propagation Delay, Pulse Width Waveforms FIGURE 7. Setup Time, Hold Time and Recovery Time Waveforms www.fairchildsemi.com 6 74ABT2952 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body Package Number M24B 24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide Package Number MSA24 7 www.fairchildsemi.com 74ABT2952 Octal Registered Transceiver Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC24 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 8 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com