74AC191SC

74AC191 Up/Down Counter with Preset and Ripple Clock November 1988 Revised November 1999 74AC191 Up/Down Counter with Preset and Ripple Clock General Description The AC191 is a reversible modulo 16 binary counter. It features synchronous counting and asynchronous presetting. The preset feature allows the AC191 to be used in programmable dividers. The Count Enable input, the Terminal Count output and the Ripple Clock output make possible a variety of methods of implementing multistage counters. In the counting modes, state changes are initiated by the rising edge of the clock. Features s ICC reduced by 50% s High speed—133 MHz typical count frequency s Synchronous counting s Asynchronous parallel load s Cascadable s Outputs source/sink 24 mA Ordering Code: Order Number 74AC191SC 74AC191SJ 74AC191MTC 74AC191PC Package Number M16A M16D MTC16 N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Names CE CP P0–P3 PL U /D Q0–Q3 RC TC Description Count Enable Input Clock Pulse Input Parallel Data Inputs Asynchronous Parallel Load Input Up/Down Count Control Input Flip-Flop Outputs Ripple Clock Output Terminal Count Output FACT is a trademark of Fairchild Semiconductor Corporation. © 1999 Fairchild Semiconductor Corporation DS009940 www.fairchildsemi.com 74AC191 RC Truth Table Inputs PL H H H L CE L H X X TC (Note 1) H X L X CP Outputs RC X X X H H H H = H IGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Transition = Clock Pulse  Note 1: TC is generated internally Functional Description The AC191 is a synchronous up/down counter. The AC191 is organized as a 4-bit binary counter. It contains four edgetriggered flip-flops with internal gating and steering logic to provide individual preset, count-up and count-down operations. Each circuit has an asynchronous parallel load capability permitting the counter to be preset to any desired number. When the Parallel Load (PL ) input is LOW, information present on the Parallel Load inputs (P0–P3) is loaded into the counter and appears on the Q outputs. This operation overrides the counting functions, as indicated in the Mode Select Table. A HIGH signal on the CE input inhibits counting. When CE is LOW, internal state changes are initiated synchronously by the LOW-to-HIGH transition of the clock input. The direction of counting is determined by the U/D input signal, as indicated in the Mode Select Table. CE and U/D can be changed with the clock in either state, provided only that the recommended setup and hold times are observed. Two types of outputs are provided as overflow/underflow indicators. The terminal count (TC) output is normally LOW. It goes HIGH when the circuits reach zero in the count down mode or 15 in the count up mode. The TC output will then remain HIGH until a state change occurs, whether by counting or presetting or until U/D is changed. The TC output should not be used as a clock signal because it is subject to decoding spikes. The TC signal is also used internally to enable the Ripple Clock (RC) output. The RC output is normally HIGH. When CE is LOW and TC is HIGH, RC output will go LOW when the clock next goes LOW and will stay LOW until the clock goes HIGH again. This feature simplifies the design of multistage counters, as indicated in Figure 1 and Figure 2. In Figure 1, each RC output is used as the clock input for the next higher stage. This configuration is particularly advantageous when the clock source has a limited drive capability, since it drives only the first stage. To prevent counting in all stages it is only necessary to inhibit the first stage, since a HIGH signal on CE inhibits the RC output pulse, as indicated in the RC Truth Table. A disadvantage of this configuration, in some applications, is the timing skew between state changes in the first and last stages. This represents the cumulative delay of the clock as it ripples through the preceding stages. A method of causing state changes to occur simultaneously in all stages is shown in Figure 2. All clock inputs are driven in parallel and the RC outputs propagate the carry/borrow signals in ripple fashion. In this configuration the LOW state duration of the clock must be long enough to allow the negative-going edge of the carry/borrow signal to www.fairchildsemi.com 2 ripple through to the last stage before the clock goes HIGH. There is no such restriction on the HIGH state duration of the clock, since the RC output of any device goes HIGH shortly after its CP input goes HIGH. The configuration shown in Figure 3 avoids ripple delays and their associated restrictions. The CE input for a given stage is formed by combining the TC signals from all the preceding stages. Note that in order to inhibit counting an enable signal must be included in each carry gate. The simple inhibit scheme of Figure 1 and Figure 2 doesn't apply, because the TC output of a given stage is not affected by its own CE. Mode Select Table Inputs PL H H L H CE L L X H U/D L H X X Mode   X X CP Count Up Count Down Preset (Asyn.) No Change (Hold) State Diagram 74AC191 Functional Description (continued) FIGURE 1. N-Stage Counter Using Ripple Clock FIGURE 2. Synchronous N-Stage Counter Using Ripple Carry/Borrow FIGURE 3. Synchronous N-Stage Counter with Parallel Gated Carry/Borrow Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 www.fairchildsemi.com 74AC191 Absolute Maximum Ratings(Note 2) Supply Voltage (VCC ) DC Input Diode Current (IIK) VI = −0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) PDIP 140°C ±50 mA −65°C to +150 °C ±50 mA −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V −0.5V to +7.0V Recommended Operating Conditions Supply Voltage (VCC) Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate (∆V/∆t) VIN from 30% to 70% of VCC VCC @ 3.3V 4.5V, 5.5V 125 mV/ns 2.0V to 6.0V 0V to VCC 0V to VCC −40°C to +85°C Note 2: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications. DC Electrical Characteristics Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level Output Voltage VCC (V) 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 VOL Maximum LOW Level Output Voltage 3.0 4.5 5.5 3.0 4.5 5.5 IIN (Note 5) IOLD IOHD ICC (Note 5) Maximum Input Leakage Current Minimum Dynamic Output Current (Note 4) Maximum Quiescent Supply Current 0.002 0.001 0.001 TA = +25°C Typ 1.5 2.25 2.75 1.5 2.25 2.75 2.99 4.49 5.49 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.56 3.86 4.86 0.1 0.1 0.1 0.36 0.36 0.36 TA = −40°C to +85°C Guaranteed Limits 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.46 3.76 4.76 0.1 0.1 0.1 0.44 0.44 0.44 V VIN = VIL or VIH IOL = 12 mA IOL = 24 mA IOL = 24 mA (Note 3) 5.5 5.5 5.5 5.5 4.0 ±0.1 ±1.0 75 −75 40.0 µA mA mA µA VI = VCC, GND VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC or GND V IOUT = 50 µA V VIN = VIL or VIH IOH −12 mA IOH = −24 mA IOH.= −24 mA (Note 3) V IOUT = −50 µA V VOUT = 0.1V or VCC − 0.1V V VOUT = 0.1V or VCC − 0.1V Units Conditions Note 3: All outputs loaded; thresholds on input associated with output under test. Note 4: Maximum test duration 2.0 ms, one output loaded at a time. Note 5: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. www.fairchildsemi.com 4 74AC191 AC Electrical Characteristics VCC Symbol Parameter (V) (Note 6) fMAX Maximum Count Frequency tPLH Propagation Delay CP to Qn tPHL Propagation Delay CP to Qn tPLH Propagation Delay CP to TC tPHL Propagation Delay CP to TC tPLH Propagation Delay CP to RC tPHL Propagation Delay CP to RC tPLH Propagation Delay CE to RC tPHL Propagation Delay CE to RC tPLH Propagation Delay U /D to RC tPHL Propagation Delay U /D to RC tPLH Propagation Delay U /D to TC tPHL Propagation Delay U /D to TC tPLH Propagation Delay Pn to Qn tPHL Propagation Delay Pn to Qn tPLH Propagation Delay PL to Qn tPHL Propagation Delay PL to Qn Note 6: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V CL = 50 pF TA = +25°C Min 70 90 2.0 1.5 2.5 1.5 3.5 2.5 4.0 2.5 2.5 2.0 2.5 1.5 2.5 1.5 2.0 1.5 2.5 1.5 2.5 1.5 2.0 1.5 2.0 1.5 2.5 2.0 2.5 1.5 3.5 2.0 3.0 2.0 Typ 105 133 8.5 6.0 8.5 6.0 10.5 7.5 10.5 7.5 7.5 5.5 7.0 5.0 7.0 5.0 6.5 5.0 6.5 5.0 7.0 5.0 7.0 5.0 6.5 5.0 8.0 5.5 7.5 5.5 9.5 5.5 8.0 6.0 15.0 11.0 14.5 10.5 18.0 12.0 17.5 12.5 12.0 9.5 11.5 8.5 12.0 8.5 11.0 8.0 12.5 9.0 12.0 8.5 11.5 8.5 11.0 8.5 13.5 9.5 13.0 9.5 14.5 9.5 13.5 10.0 Max TA = −40°C to +85°C CL = 50 pF Min 65 85 1.5 1.5 2.0 1.5 2.5 1.5 3.0 2.0 2.0 1.0 2.0 1.0 1.5 1.0 1.5 1.0 2.0 1.0 2.0 1.0 1.5 1.0 1.5 1.0 2.0 1.0 1.5 1.0 2.5 1.0 2.0 1.5 16.0 12.0 16.0 11.5 20.0 14.0 19.0 13.5 13.5 10.5 12.5 9.5 13.5 9.5 12.5 9.0 14.5 10.0 13.5 10.0 13.5 9.5 12.5 9.5 15.5 10.5 14.5 10.5 17.5 10.5 15.5 11.0 Max MHz Units 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5 www.fairchildsemi.com 74AC191 AC Operating Requirements VCC Symbol Parameter (V) (Note 7) tS Setup Time, HIGH or LOW Pn to PL tH Hold Time, HIGH or LOW Pn to PL tS Setup Time, LOW CE to CP tH Hold Time, LOW CE to CP tS Setup Time, HIGH or LOW U/D to CP tH Hold Time, HIGH or LOW U/D to CP tW PL Pulse Width, LOW 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 tW CP Pulse Width, LOW 3.3 5.0 trec Recovery Time PL to CP Note 7: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V TA = +25°C C L = 50 pF Typ 1.0 0.5 −1.5 −0.5 3.0 1.5 −4.0 −2.5 4.0 2.5 −5.0 −3.0 2.0 1.0 2.0 2.0 −0.5 −1.0 3.0 2.0 0.5 1.0 6.0 4.0 −0.5 0 8.0 5.5 0 0.5 3.5 1.0 3.5 3.0 0 0 TA = −40°C to +85°C CL = 50 pF Guaranteed Minimum 3.0 2.5 1.0 1.0 7.0 4.5 −0.5 0 9.0 6.5 0 0.5 4.0 1.0 4.0 4.0 0 0 ns Units ns ns ns ns ns ns ns 3.3 5.0 ns Capacitance Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance Typ 4.5 75.0 Units pF pF V CC = OPEN V CC = 5.0V Conditions www.fairchildsemi.com 6 74AC191 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body Package Number M16A 7 www.fairchildsemi.com 74AC191 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D www.fairchildsemi.com 8 74AC191 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 9 www.fairchildsemi.com 74AC191 Up/Down Counter with Preset and Ripple Clock Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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