74AC257 • 74ACT257 Quad 2-Input Multiplexer with 3-STATE Outputs
November 1988 Revised November 1999
74AC257 • 74ACT257 Quad 2-Input Multiplexer with 3-STATE Outputs
General Description
The AC/ACT257 is a quad 2-input multiplexer with 3STATE outputs. Four bits of data from two sources can be selected using a Common Data Select input. The four outputs present the selected data in true (noninverted) form. The outputs may be switched to a high impedance state by placing a logic HIGH on the common Output Enable (OE) input, allowing the outputs to interface directly with bus-oriented systems.
Features
s ICC and IOZ reduced by 50% s Multiplexer expansion by tying outputs together s Noninverting 3-STATE outputs s Outputs source/sink 24 mA s ACT257 has TTL-compatible inputs
Ordering Code:
Order Number 74AC257SC 74AC257SJ 74AC257MTC 74AC257PC 74ACT257SC 74ACT257SJ 74ACT257MTC 74ACT257PC Package Number M16A M16D MTC16 N16E M16A M16D MTC16 N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names S OE I0a–I0d I1a–I1d Za–Zd Description Common Data Select Input 3-STATE Output Enable Input Data Inputs from Source 0 Data Inputs from Source 1 3-STATE Multiplexer Outputs
FACT is a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation
DS009949
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74AC257 • 74ACT257
Functional Description
The AC/ACT257 is quad 2-input multiplexer with 3-STATE outputs. It selects four bits of data from two sources under control of a Common Data Select input. When the Select input is LOW, the I0x inputs are selected and when Select is HIGH, the I1x inputs are selected. The data on the selected inputs appears at the outputs in true (noninverted) form. The device is the logic implementation of a 4-pole, 2position switch where the position of the switch is determined by the logic levels supplied to the Select input. The logic equations for the outputs are as follows: Za = OE • (11a • S + I0a • S) Zb = OE • (11b • S + I0b • S) Zc = OE • (11c • S + I0c • S) Zd = OE • (11d • S + I0d • S) When the Output Enable (OE) is HIGH, the outputs are forced to a high impedance state. If the outputs are tied together, all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings. Designers should ensure the Output Enable signals to 3-STATE devices whose outputs are tied together are designed so there is no overlap.
Truth Table
Output Enable OE H L L L L
H = H IGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance
Select Input S X H H L L I0 X X X L H
Data Inputs I1 X L H X X
Outputs
Z Z L H L H
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74AC257 • 74ACT257
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V VI = VCC +0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V VO = VCC +0.5V DC Output Voltage (VO) DC Output Source ort Sink Curren (IO) DC VCC or Ground Current Per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) PDIP 140°C ±50 mA −65°C to +150°C ±50 mA −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V −0.5V to +7.0V
Recommended Operating Conditions
Supply Voltage (VCC) AC ACT Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate (∆V/∆t) AC Devices VIN from 30% to 70% of VCC VCC @ 3.3V, 4.5V, 5.5V Minimum Input Edge Rate (∆V/∆t) ACT Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V 125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications.
2.0V to 6.0V 4.5V to 5.5V 0V to VCC 0V to VCC −40°C to +85°C
125 mV/ns
DC Electrical Characteristics for AC
Symbol VIH Parameter Minimum HIGH Level Voltage Input VIL Maximum LOW Level Voltage Input VOH Minimum HIGH Level Voltage Output VCC (V) 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 VOL Maximum LOW Level Voltage Output 3.0 4.5 5.5 3.0 4.5 5.5 IIN (Note 4) IOZ Maximum Input Leakage Current Maximum 3-STATE Leakage Current IOLD IOHD ICC (Note 4) Minimum Dynamic (Note 3) Output Current Maximum Quiescent Supply Current 5.5 5.5 5.5 5.5 4.0 ±0.25 ±2.5 75 −75 40.0 µA mA mA µA 5.5 0.002 0.001 0.001 TA = +25°C Typ 1.5 2.25 2.75 1.5 2.25 2.75 2.99 4.49 5.49 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.56 3.86 4.86 0.1 0.1 0.1 0.36 0.36 0.36 ± 0.1 TA = −40°C to +85°C Guaranteed Limits 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 VIN = VIL or VIH 2.46 3.76 4.76 0.1 0.1 0.1 VIN = VIL or VIH 0.44 0.44 0.44 ± 1.0 µA V IOL = 12 mA IOL = 24 mA IOL = 24 mA (Note 2) VI = VCC, GND VI (OE) = VIL, VIH VI = VCC, GND VO = VCC, GND VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC or GND V IOUT = 50 µA V IOH = −12 mA IOH = −24 mA IOH = −24 mA (Note 2) V IOUT = −50 µA V VOUT = 0.1V or VCC − 0.1V V Units Conditions VOUT = 0.1V or VCC − 0.1V
Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: M aximum test duration 2.0 ms, one output loaded at a time. Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
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74AC257 • 74ACT257
DC Electrical Characteristics for ACT
Symbol VIH VIL VOH Parameter Minimum HIGH Level Input Voltage Maximum LOW Level Input Voltage Minimum HIGH Level Output Voltage VCC (V) 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL Maximum LOW Level Output Voltage 4.5 5.5 4.5 5.5 IIN IOZ ICCT IOLD IOHD ICC Maximum Input Leakage Current Maximum 3-STATE Leakage Current Maximum ICC/Input Dynamic Output Current Minimum (Note 6) Maximum Quiescent Supply Current 5.5 5.5 5.5 5.5 5.5 5.5 4.0 0.6 0.001 0.001 TA = +25°C Typ 1.5 1.5 1.5 1.5 4.49 5.49 2.0 2.0 0.8 0.8 4.4 5.4 3.86 4.86 0.1 0.1 0.36 0.36 ±0.1 ± 0.5 TA = −40°C to +85°C Guaranteed Limits 2.0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.44 0.44 ±1.0 ± 5.0 1.5 75 −75 40.0 µA µA mA mA mA µA V Units V V V Conditions VOUT = 0.1V or VCC − 0.1V VOUT = 0.1V or VCC − 0.1V IOUT = −50 µA VIN = VIL or VIH V IOH = −24 mA IOH = −24 mA (Note 5) IOUT = 50 µA VIN = VIL or VIH V IOL = 24 mA IOL = 24 mA (Note 5) VI = VCC, GND VI = VIL, VIH VO = VCC, GND VI = VCC − 2.1V VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC or GND
Note 5: All outputs loaded; thresholds on input associated with output under test. Note 6: Maximum test duration 2.0 ms, one output loaded at a time.
AC Electrical Characteristics for AC
VCC Symbol Parameter Propagation Delay In to Zn Propagation Delay In to Zn tPLH tPHL Propagation Delay S to Zn Propagation Delay S to Zn tPZH tPZL tPHZ tPLZ Output Enable Time Output Enable Time Output Disable Time Output Disable Time (V) (Note 7) tPLH tPHL 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0
Voltage Range 5.0 is 5.0V ± 0.5V
TA = +25°C CL = 50 pF Min 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 Typ 5.0 4.0 6.0 4.5 7.0 5.0 7.5 5.5 6.5 5.0 5.5 5.0 5.5 5.0 5.5 5.0 Max 8.5 6.0 8.5 6.0 10.5 7.5 10.5 7.5 9.5 7.5 9.0 8.5 10.0 9.0 9.0 8.0
TA = −40°C to +85°C CL = 50 pF Min 1.0 1.0 1.0 1.0 1.5 1.0 1.5 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Max 9.0 7.0 9.0 7.0 11.5 8.5 11.5 8.5 10.5 8.5 10.0 9.5 11.0 10.0 10.0 9.0 ns ns ns ns ns ns ns ns Units
Note 7: Voltage Range 3.3 is 3.0V ± 0.3V
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74AC257 • 74ACT257
AC Electrical Characteristics for ACT
VCC Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Propagation Delay In to Zn Propagation Delay In to Zn Propagation Delay S to Zn Propagation Delay S to Zn Output Enable Time Output Enable Time Output Disable Time Output Disable Time (V) (Note 8) 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 Min 1.5 2.0 2.0 2.5 2.0 2.0 2.5 2.0 TA = +25°C CL = 50 pF Typ 5.0 6.0 7.0 7.0 6.0 6.0 6.5 6.0 Max 7.0 7.5 9.5 10.5 8.0 8.0 9.0 7.5 TA = −40°C to +85°C CL = 50 pF Min 1.0 1.5 1.5 2.0 1.5 1.5 1.5 1.5 Max 7.5 8.5 10.5 11.5 9.0 9.0 10.0 8.5 ns ns ns ns ns ns ns ns Units
Note 8: Voltage Range 5.0 is 5.0V ± 0.5V
Capacitance
Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance Typ 4.5 50.0 Units pF pF VCC = OPEN VCC = 5.0V Conditions
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74AC257 • 74ACT257
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body Package Number M16A
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74AC257 • 74ACT257
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D
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74AC257 • 74ACT257
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16
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74AC257 • 74ACT257 Quad 2-Input Multiplexer with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 9 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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