74ACT125SC

74AC125, 74ACT125 — Quad Buffer with 3-STATE Outputs January 2008 74AC125, 74ACT125 Quad Buffer with 3-STATE Outputs Features ■ ICC reduced by 50% ■ Outputs source/sink 24mA ■ ACT125 has TTL-compatible outputs General Description The AC/ACT125 contains four independent non-inverting buffers with 3-STATE outputs. Ordering Information Order Number 74AC125SC 74AC125SJ 74AC125MTC 74AC125PC 74ACT125SC 74ACT125SJ 74ACT125MTC 74ACT125PC Package Number M14A M14D MTC14 N14A M14A M14D MTC14 N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. Connection Diagram Logic Symbol IEEE/IEC Pin Description Pin Names An, Bn On Description Inputs Outputs Function Table Inputs An L L H Bn L H X Output On L H Z H = HIGH Voltage Level, L = LOW Voltage Level Z = HIGH Impedance, X = Immaterial ©1988 Fairchild Semiconductor Corporation 74AC125, 74ACT125 Rev. 1.4.1 www.fairchildsemi.com 74AC125, 74ACT125 — Quad Buffer with 3-STATE Outputs Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VCC IIK Supply Voltage DC Input Diode Current VI = –0.5V VI = VCC + 0.5 VI IOK DC Input Voltage DC Output Diode Current VO = –0.5V VO = VCC + 0.5V VO IO TSTG TJ DC Output Voltage Parameter Rating –0.5V to +7.0V –20mA +20mA –0.5V to VCC + 0.5V –20mA +20mA –0.5V to VCC + 0.5V ±50mA ±50mA –65°C to +150°C 140°C DC Output Source or Sink Current Storage Temperature Junction Temperature ICC or IGND DC VCC or Ground Current per Output Pin Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol VCC Supply Voltage AC ACT VI VO TA ∆V / ∆t ∆V / ∆t Input Voltage Output Voltage Operating Temperature Parameter Rating 2.0V to 6.0V 4.5V to 5.5V 0V to VCC 0V to VCC –40°C to +85°C 125mV/ns 125mV/ns Minimum Input Edge Rate, AC Devices: VIN from 30% to 70% of VCC, VCC @ 3.3V, 4.5V, 5.5V Minimum Input Edge Rate, ACT Devices: VIN from 0.8V to 2.0V, VCC @ 4.5V, 5.5V ©1988 Fairchild Semiconductor Corporation 74AC125, 74ACT125 Rev. 1.4.1 www.fairchildsemi.com 2 74AC125, 74ACT125 — Quad Buffer with 3-STATE Outputs DC Electrical Characteristics for AC Symbol VIH Parameter Minimum HIGH Level Input Voltage VCC (V) 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 TA = +25°C Conditions VOUT = 0.1V or VCC – 0.1V VOUT = 0.1V or VCC – 0.1V IOUT = –50µA TA = –40°C to +85°C Guaranteed Limits Units V 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.46 3.76 4.76 0.1 0.1 0.1 0.44 0.44 0.44 ±1.0 ±2.5 µA µA V V V Typ. 1.5 2.25 2.75 1.5 2.25 2.75 2.99 4.49 5.49 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.56 3.86 4.86 0.002 0.001 0.001 0.1 0.1 0.1 0.36 0.36 0.36 ±0.1 VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level Output Voltage VIN = VIL or VIH, IOH = –12mA VIN = VIL or VIH, IOH = –24mA VIN = VIL or VIH, IOH = –24mA(1) IOUT = 50µA VOL Maximum LOW Level Output Voltage 3.0 4.5 5.5 3.0 4.5 5.5 VIN = VIL or VIH, IOL = 12mA VIN = VIL or VIH, IOL = 24mA VIN = VIL or VIH, IOL = 24mA(1) VI = VCC, GND VI (OE) = VIL, VIH, VI = VCC, VGND, VO = VCC, GND VOLD = 1.65V Max. VOHD = 3.85V Min. VIN = VCC or GND IIN(3) IOZ Maximum Input Leakage Current Maximum 3-STATE Current Minimum Dynamic Output Current(2) Maximum Quiescent Supply Current 5.5 5.5 ±0.25 IOLD IOHD ICC (3) 5.5 5.5 5.5 75 –75 4.0 40.0 mA mA µA Notes: 1. All outputs loaded; thresholds on input associated with output under test. 2. Maximum test duration 2.0ms, one output loaded at a time. 3. IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. ©1988 Fairchild Semiconductor Corporation 74AC125, 74ACT125 Rev. 1.4.1 www.fairchildsemi.com 3 74AC125, 74ACT125 — Quad Buffer with 3-STATE Outputs DC Electrical Characteristics for ACT Symbol VIH VIL VOH Parameter Minimum HIGH Level Input Voltage Maximum LOW Level Input Voltage Minimum HIGH Level Output Voltage VCC (V) 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 TA = +25°C Conditions VOUT = 0.1V or VCC – 0.1V VOUT = 0.1V or VCC – 0.1V IOUT = –50µA VIN = VIL or VIH, IOH = –24mA VIN = VIL or VIH, IOH = –24mA(4) IOUT = 50µA VIN = VIL or VIH, IOL = 24mA VIN = VIL or VIH, IOL= 24mA(4) VI = VCC, GND VI = VIL, VIH; VO = VCC, GND VI = VCC – 2.1V(6) VOLD = 1.65V Max. VOHD = 3.85V Min. VIN = VCC or GND 4.0 0.6 0.001 0.001 4.86 0.1 0.1 0.36 0.36 ±0.1 ±0.5 TA = –40°C to +85°C Guaranteed Limits Units V V V 2.0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.44 0.44 ±1.0 ±5.0 1.5 75 –75 40.0 µA µA mA mA mA µA V Typ. 1.5 1.5 1.5 1.5 4.49 5.49 2.0 2.0 0.8 0.8 4.4 5.4 3.86 VOL Maximum LOW Level Output Voltage 4.5 5.5 4.5 5.5 IIN IOZ ICCT IOLD IOHD ICC Maximum Input Leakage Current Maximum 3-STATE Current Maximum ICC/Input Minimum Dynamic Output Current(5) Maximum Quiescent Supply Current 5.5 5.5 5.5 5.5 5.5 5.5 Notes: 4. All outputs loaded; thresholds on input associated with output under test. 5. Maximum test duration 2.0ms, one output loaded at a time. 6. May be measured per the JEDEC Alternate Method. ©1988 Fairchild Semiconductor Corporation 74AC125, 74ACT125 Rev. 1.4.1 www.fairchildsemi.com 4 74AC125, 74ACT125 — Quad Buffer with 3-STATE Outputs AC Electrical Characteristics for AC TA = +25°C, CL = 50pF Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ TA = –40°C to +85°C, CL = 50pF Min. 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Parameter Propagation Delay, Data to Output Propagation Delay, Data to Output Output Enable Time Output Enable Time Output Disable Time Output Disable Time VCC (V)(7) 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 Min. 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Typ. 6.5 5.5 6.5 5.0 6.0 5.0 7.5 5.5 7.5 6.5 7.5 6.5 Max. 9.0 7.0 9.0 7.0 10.5 7.0 10.0 8.0 10.0 9.0 10.5 9.0 Max. 10.0 7.5 10.0 7.5 11.0 8.0 11.0 8.5 10.5 9.5 11.5 9.5 Units ns ns ns ns ns ns Note: 7. Voltage range 3.3 is 3.3V ± 0.3V. Voltage range 5.0 is 5.0V ± 0.5V. AC Electrical Characteristics for ACT TA = +25°C, CL = 50pF Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ TA = –40°C to +85°C, CL = 50pF Min. 1.0 1.0 1.0 1.0 1.0 1.0 Parameter Propagation Delay, Data to Output Propagation Delay, Data to Output Output Enable Time Output Enable Time Output Disable Time Output Disable Time VCC (V)(8) 5.0 5.0 5.0 5.0 5.0 5.0 Min. 1.0 1.0 1.0 1.0 1.0 1.0 Typ. 6.5 7.0 6.0 7.0 7.0 7.5 Max. 9.0 9.0 8.5 9.5 9.5 10.0 Max. 10.0 10.0 9.5 10.5 10.5 10.5 Units ns ns ns ns ns ns Note: 8. Voltage Range 5.0 is 5.0V ± 0.5V. Capacitance Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance Conditions VCC = OPEN VCC = 5.0V Typ. 4.5 45.0 Units pF pF ©1988 Fairchild Semiconductor Corporation 74AC125, 74ACT125 Rev. 1.4.1 www.fairchildsemi.com 5 74AC125, 74ACT125 — Quad Buffer with 3-STATE Outputs Physical Dimensions 8.75 8.50 7.62 14 8 B A 0.65 5.60 6.00 4.00 3.80 PIN ONE INDICATOR 1 7 1.70 1.27 1.27 (0.33) 0.51 0.35 0.25 M LAND PATTERN RECOMMENDATION CBA 1.75 MAX 1.50 1.25 0.25 0.10 C 0.10 C SEE DETAIL A 0.25 0.19 NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AB, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD GAGE PLANE FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X145-14M 0.36 E) DRAWING CONFORMS TO ASME Y14.5M-1994 F) DRAWING FILE NAME: M14AREV13 0.50 X 45° 0.25 R0.10 R0.10 8° 0° 0.90 0.50 (1.04) DETAIL A SCALE: 20:1 SEATING PLANE Figure 1. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1988 Fairchild Semiconductor Corporation 74AC125, 74ACT125 Rev. 1.4.1 www.fairchildsemi.com 6 74AC125, 74ACT125 — Quad Buffer with 3-STATE Outputs Physical Dimensions (Continued) Figure 2. 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1988 Fairchild Semiconductor Corporation 74AC125, 74ACT125 Rev. 1.4.1 www.fairchildsemi.com 7 74AC125, 74ACT125 — Quad Buffer with 3-STATE Outputs Physical Dimensions (Continued) 0.43 TYP 0.65 1.65 0.45 6.10 12.00° TOP R0.09 min & BOTTOM A. CONFORMS TO JEDEC REGISTRATION MO-153, VARIATION AB, REF NOTE 6 B. DIMENSIONS ARE IN MILLIMETERS C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS D. DIMENSIONING AND TOLERANCES PER ANSI Y14.5M, 1982 E. LANDPATTERN STANDARD: SOP65P640X110-14M F. DRAWING FILE NAME: MTC14REV6 1.00 R0.09min Figure 3. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1988 Fairchild Semiconductor Corporation 74AC125, 74ACT125 Rev. 1.4.1 www.fairchildsemi.com 8 74AC125, 74ACT125 — Quad Buffer with 3-STATE Outputs Physical Dimensions (Continued) 19.56 18.80 14 8 6.60 6.09 1 7 (1.74) 1.77 1.14 5.33 MAX 0.38 MIN 8.12 7.62 0.35 0.20 3.56 3.30 3.81 3.17 0.58 0.35 2.54 8.82 NOTES: UNLESS OTHERWISE SPECIFIED THIS PACKAGE CONFORMS TO A) JEDEC MS-001 VARIATION BA B) ALL DIMENSIONS ARE IN MILLIMETERS. DIMENSIONS ARE EXCLUSIVE OF BURRS, C) MOLD FLASH, AND TIE BAR EXTRUSIONS. D) DIMENSIONS AND TOLERANCES PER ASME Y14.5-1994 E) DRAWING FILE NAME: MKT-N14AREV7 Figure 4. 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1988 Fairchild Semiconductor Corporation 74AC125, 74ACT125 Rev. 1.4.1 www.fairchildsemi.com 9 74AC125, 74ACT125 — Quad Buffer with 3-STATE Outputs TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks. PDP-SPM™ SyncFET™ ® Power220® ® Power247 The Power Franchise® POWEREDGE® Power-SPM™ PowerTrench® TinyBoost™ Programmable Active Droop™ TinyBuck™ ® QFET TinyLogic® QS™ TINYOPTO™ QT Optoelectronics™ TinyPower™ ® Quiet Series™ TinyPWM™ RapidConfigure™ TinyWire™ Fairchild® SMART START™ Fairchild Semiconductor® µSerDes™ ® SPM FACT Quiet Series™ UHC® STEALTH™ FACT® Ultra FRFET™ SuperFET™ FAST® UniFET™ SuperSOT™-3 FastvCore™ VCX™ ® ®* SuperSOT™-6 FlashWriter SuperSOT™-8 * EZSWITCH™ and FlashWriter® are trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design. This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor. The datasheet is printed for reference information only. Rev. I32 ACEx® Build it Now™ CorePLUS™ CROSSVOLT™ CTL™ Current Transfer Logic™ EcoSPARK® EZSWITCH™ * ™ FPS™ FRFET® Global Power ResourceSM Green FPS™ Green FPS™ e-Series™ GTO™ i-Lo™ IntelliMAX™ ISOPLANAR™ MegaBuck™ MICROCOUPLER™ MicroFET™ MicroPak™ MillerDrive™ Motion-SPM™ OPTOLOGIC® OPTOPLANAR® 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Preliminary First Production No Identification Needed Full Production Obsolete Not In Production ©1988 Fairchild Semiconductor Corporation 74AC125, 74ACT125 Rev. 1.4.1 www.fairchildsemi.com 10