74ACT1284_00

74ACT1284 IEEE 1284 Transceiver June 1996 Revised November 2000 74ACT1284 IEEE 1284 Transceiver General Description The 74ACT1284 contains four non-inverting bidirectional buffers and three non-inverting buffers with open Drain outputs and high drive capability on the B Ports. It is intended to provide a standard signaling method for a bi-direction parallel peripheral in an Extended Capabilities Port mode (ECP). The HD (active HIGH) input pin enables the B Ports to switch from open Drain to a high drive totem pole output, capable of sourcing 14 mA on all seven buffers. The DIR input determines the direction of data flow on the bidirectional buffers. DIR (active HIGH) enables data flow from A Ports to B Ports. DIR (active LOW) enables data flow from B Ports to A Ports. Features s TTL-compatible inputs s A Ports have standard 4 mA totem pole outputs s Typical input hysteresis of 0.5V s B Port high drive source/sink capability of 14 mA s Bidirectional non-inverting buffers s Supports IEEE P1284 Level 1 and Level 2 signaling standards for bidirectional parallel communications between personal computers and printing peripherals s B Port outputs in High Impedance mode during power down s Guaranteed 4000V minimum ESD protection Ordering Code: Order Number 74ACT1284SC 74ACT1284MSA 74ACT1284MTC Package Number M20B MSA20 MTC20 Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Connection Diagram Pin Descriptions Pin Names HD DIR A1 - A4 B1 - B4 A5 - A7 B5 - B7 Description High Drive Enable input (Active HIGH) Direction Control Input Side A Inputs or Outputs Side B Inputs or Outputs Side A Inputs Side B Outputs FACT is a trademark of Fairchild Semiconductor Corporation. © 2000 Fairchild Semiconductor Corporation DS011683 www.fairchildsemi.com 74ACT1284 Truth Table Inputs DIR L L H H Note 1: B5 - B7 Open Drain Outputs Note 2: B1 - B7 Open Drain Outputs HD L H L H Outputs B1- B4 Data to A1 - A4, and A5 - A7 Data to B5 - B7 (Note 1) B1- B4 Data to A1 - A4, and A5 - A7 Data to B5 - B7 A1 - A7 Data to B1 - B7 (Note 2) A1 - A7 Data to B1 - B7 Logic Diagram www.fairchildsemi.com 2 74ACT1284 Absolute Maximum Ratings(Note 3) (Note 4) Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V VI = VCC + 0.5V DC Input Voltage (VI) A Side DC Input Voltage (VI) B Side DC Output Diode Current (IOK) VO = −0.5V VO = VCC + 0.5V DC Output Voltage (VO) A Side DC Output Voltage (VO) B Side DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) Recommended Operating Conditions Supply Voltage (VCC) Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) 4.7V to 5.5V 0V to VCC 0V to VCC −0.5V to +7.0V −20 mA +20 mA −0.5V to VCC + 0.5V −2V to +7V −20 mA +20 mA −0.5V to VCC + 0.5V −2V to +7V ± 50 mA ± 50 mA −65°C to +150°C −40°C to +85°C Note 3: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications. Note 4: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol VIH VIL VOH Parameter Minimum HIGH Level Input Voltage Maximum LOW Level Input Voltage Minimum HIGH Level Output Voltage 4.7 VCC (V) 4.7 5.5 4.7 5.5 TA = +25°C 2.0 2.0 0.8 0.8 4.5 3.7 2.4 VOL Maximum LOW Level Output Voltage 4.7 0.2 0.4 Guaranteed Limits TA = 0°C to +70°C TA = −40°C to +85°C 2.0 2.0 0.8 0.8 4.5 3.7 2.4 0.2 0.4 2.0 2.0 0.8 0.8 4.5 3.7 2.4 0.2 0.4 V V Units Conditions Recognized High Signal Recognized Low Signal IOUT = −50 µA (An) VIN = VIL or VIH (Note 5) IOH = −4 mA (An) IOH = −14 mA (Bn) IOUT = 50 µA (An) VIN = VIL or VIH (Note 5) IOH = 4 mA (An) IOH = 14 mA (Bn) IIN ICCT ICC IOZ IOFF ∆VT RD Maximum Input Leakage Current Maximum ICC/Input Maximum Quiescent Supply Current Maximum Output Leakage Current Maximum B-Side Power Down Leakage Current Input Hysteresis Maximum Output Impedance Minimum Output Impedance 5.5 5.5 5.5 5.5 0.0 5.0 5.0 5.0 400 ±20 100 0.4 22 8 ±0.1 1.5 400 ±20 100 0.4 22 8 ±1.0 1.5 500 ±20 100 0.35 24 6 µA mA µA µA µA V Ω Ω VI = VCC, GND (DIR, A5, A6, A7, HD) VI = VCC − 2.1V VIN = VCC or GND VO = VCC, GND VOUT = 5.25V VT + − VT− Bn (Note 6) Bn (Note 6) V V Note 5: All outputs loaded; thresholds on input associated with output under test. Note 6: This parameter is guaranteed but not tested, characterized only: RD is the measure of the B-Side output impedance with the output in the HIGH state. 3 www.fairchildsemi.com 74ACT1284 AC Electrical Characteristics TA = +25°C Symbol Parameter VCC = 4.7V − 5.5V Min tPHL tPLH tPHL tPLH tpEnable tpDisable tSKEW tPLH tPHL tr , tf tRISE and tFALL B1 - B7 (Note 7) Note 7: Open Drain Note 8: This parameter is guaranteed but not tested, characterized only. Note: Pulse Generator for all pulses; Rate ≤ 1.0 MHz; AO ≤ 50Ω; tf ≤ 2.5 ns, tr ≤ 2.5 ns. TA = 0°C to +70°C VCC = 4.7V − 5.5V Min 2.0 2.0 2.0 2.0 2.0 2.0 Max 20.0 20.0 20.0 20.0 20.0 20.0 TA = −40°C to +85°C VCC = 4.7V − 5.5V Min 2.0 2.0 2.0 2.0 2.0 2.0 Max 24.0 24.0 24.0 24.0 24.0 24.0 ns ns ns ns ns ns Figure 1 Figure 2 Figure 3 Figure 3 Figure 2 Figure 2 Units Figure Number Max 20.0 20.0 20.0 20.0 20.0 20.0 A1- A7 to B1 - B7 A1- A7 to B1 - B7 B1 - B4 to A1 - A4 B1 - B4 to A1 - A4 Output Enable Time HD to B1 - B7 Output Disable Time HD to B1 - B7 Output Slew Rate B1 - B7 2.0 2.0 2.0 2.0 2.0 2.0 0.05 0.40 0.05 0.40 0.05 0.40 V/ns Figures 1, 2 Figure 4 (Note 8) 120 120 120 ns Capacitance Symbol CIN CI/O Parameter Input Capacitance I/O Pin Capacitance Typ 4.0 12.0 Units pF pF VCC = 5.0V Conditions VCC = OPEN (HD, DIR A5 - A7) www.fairchildsemi.com 4 74ACT1284 AC Loading and Waveforms tSLEW measures between 10% to 90% on the tPHL Transition tSLEW measures between 10% to 90% on the tPLH Transition FIGURE 1. Port A to B Propagation Delay Waveforms FIGURE 2. B Output Test Load and Waveforms FIGURE 3. B to A Direction Test Load and Waveforms for Outputs A1 - A4 FIGURE 4. A to B Direction Test Load and Waveforms for Open Drain B1 - B7 5 www.fairchildsemi.com 74ACT1284 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide Package Number MSA20 www.fairchildsemi.com 6 74ACT1284 IEEE 1284 Transceiver Physical Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com www.fairchildsemi.com