74ACT161PC

74AC161 • 74ACT161 Synchronous Presettable Binary Counter November 1988 Revised September 2003 74AC161 • 74ACT161 Synchronous Presettable Binary Counter General Description The AC/ACT161 are high-speed synchronous modulo-16 binary counters. They are synchronously presettable for application in programmable dividers and have two types of Count Enable inputs plus a Terminal Count output for versatility in forming synchronous multistage counters. The AC/ACT161 has an asynchronous Master Reset input that overrides all other inputs and forces the outputs LOW. Features s ICC reduced by 50% s Synchronous counting and loading s High-speed synchronous expansion s Typical count rate of 125 MHz s Outputs source/sink 24 mA s ACT161 has TTL-compatible inputs Ordering Code: Order Number 74AC161SC 74AC161SJ 74AC161MTC 74AC161PC 74ACT161SC 74ACT161SJ 74ACT161MTC 74ACT161PC Package Number M16A M16D MTC16 N16E M16A M16D MTC16 N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Logic Symbols IEEE/IEC Pin Descriptions Pin Names CEP CET CP MR P0–P3 PE Q0–Q3 TC Description Count Enable Parallel Input Count Enable Trickle Input Clock Pulse Input Asynchronous Master Reset Input Parallel Data Inputs Parallel Enable Inputs Flip-Flop Outputs Terminal Count Output FACT is a trademark of Fairchild Semiconductor Corporation. © 2003 Fairchild Semiconductor Corporation DS009931 www.fairchildsemi.com 74AC161 • 74ACT161 Functional Description The AC/ACT161 count in modulo-16 binary sequence. From state 15 (HHHH) they increment to state 0 (LLLL). The clock inputs of all flip-flops are driven in parallel through a clock buffer. Thus all changes of the Q outputs (except due to Master Reset of the AC/ACT161) occur as a result of, and synchronous with, the LOW-to-HIGH transition of the CP input signal. The circuits have four fundamental modes of operation, in order of precedence: asynchronous reset, parallel load, count-up and hold. Five control inputs—Master Reset, Parallel Enable (PE), Count Enable Parallel (CEP) and Count Enable Trickle (CET)— determine the mode of operation, as shown in the Mode Select Table. A LOW signal on MR overrides all other inputs and asynchronously forces all outputs LOW. A LOW signal on PE overrides counting and allows information on the Parallel Data (Pn) inputs to be loaded into the flip-flops on the next rising edge of CP. With PE and MR HIGH, CEP and CET permit counting when both are HIGH. Conversely, a LOW signal on either CEP or CET inhibits counting. The AC/ACT161 use D-type edge-triggered flip-flops and changing the PE, CEP, and CET inputs when the CP is in either state does not cause errors, provided that the recommended setup and hold times, with respect to the rising edge of CP, are observed. The Terminal Count (TC) output is HIGH when CET is HIGH and counter is in state 15. To implement synchronous multistage counters, the TC outputs can be used with the CEP and CET inputs in two different ways. Figure 1 shows the connections for simple ripple carry, in which the clock period must be longer than the CP to TC delay of the first stage, plus the cumulative CET to TC delays of the intermediate stages, plus the CET to CP setup time of the last stage. This total delay plus setup time sets the upper limit on clock frequency. For faster clock rates, the carry lookahead connections shown in Figure 2 are recommended. In this scheme the ripple delay through the intermediate stages commences with the same clock that causes the first stage to tick over from max to min in the Up mode, or min to max in the Down mode, to start its final cycle. Since this final cycle requires 16 clocks to complete, there is plenty of time for the ripple to progress through the intermediate stages. The critical timing that lim- its the clock period is the CP to TC delay of the first stage plus the CEP to CP setup time of the last stage. The TC output is subject to decoding spikes due to internal race conditions and is therefore not recommended for use as a clock or asynchronous reset for flip-flops, registers or counters. Logic Equations: Count Enable = CEP • CET • PE TC = Q0 • Q1 • Q2 • Q3 • CET Mode Select Table PE X L H H H CET X X H L X CEP X X H X L Action on the Rising Clock Edge ( Reset (Clear) Load (Pn→Qn) Count (Increment) No Change (Hold) No Change (Hold) )  H = H IGH Voltage Level L = LOW Voltage Level X = Immaterial State Diagram FIGURE 1. Multistage Counter with Ripple Carry FIGURE 2. Multistage Counter with Lookahead Carry www.fairchildsemi.com 2 74AC161 • 74ACT161 Block Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 www.fairchildsemi.com 74AC161 • 74ACT161 Absolute Maximum Ratings(Note 1) Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) PDIP 140°C −0.5V to +7.0V −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V ±50 mA ±50 mA −65°C to +150°C Recommended Operating Conditions Supply Voltage (VCC) AC ACT Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate (∆V/∆t) AC Devices VIN from 30% to 70% of VCC VCC @ 3.3V, 4.5V, 5.5V Minimum Input Edge Rate (∆V/∆t) ACT Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V 125 mV/ns Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications. 2.0V to 6.0V 4.5V to 5.5V 0V to VCC 0V to VCC −40°C to +85°C 125 mV/ns DC Electrical Characteristics for AC Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level Output Voltage VCC (V) 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 VOL Maximum LOW Level Output Voltage 3.0 4.5 5.5 3.0 4.5 5.5 IIN (Note 4) IOLD IOHD ICC (Note 4) Maximum Input Leakage Current Minimum Dynamic Output Current (Note 3) Maximum Quiescent Supply Current 5.5 5.5 5.5 5.5 4.0 0.002 0.001 0.001 TA = +25°C Typ 1.5 2.25 2.75 1.5 2.25 2.75 2.99 4.49 5.49 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.56 3.86 4.86 0.1 0.1 0.1 0.36 0.36 0.36 ±0.1 TA = −40°C to +85°C Guaranteed Limits 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 VIN = VIL or VIH 2.46 3.76 4.76 0.1 0.1 0.1 VIN = VIL or VIH 0.44 0.44 0.44 ±1.0 75 −75 40.0 µA mA mA µA V IOL = 12 mA IOL = 24 mA IOL = 24 mA (Note 2) VI = VCC, GND VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC or GND V IOUT = 50 µA V IOH = −12 mA IOH = −24 mA IOH = −24 mA (Note 2) V IOUT = −50 µA V VOUT = 0.1V or VCC − 0.1V V Units Conditions VOUT = 0.1V or VCC − 0.1V Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. www.fairchildsemi.com 4 74AC161 • 74ACT161 DC Electrical Characteristics for ACT Symbol VIH VIL VOH Parameter Minimum HIGH Level Input Voltage Maximum LOW Level Input Voltage Minimum HIGH Level Output Voltage VCC (V) 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL Maximum LOW Level Output Voltage 4.5 5.5 4.5 5.5 IIN ICCT IOLD IOHD ICC Maximum Input Leakage Current Maximum ICC/Input Minimum Dynamic Output Current (Note 6) Maximum Quiescent Supply Current 5.5 5.5 5.5 5.5 5.5 4.0 0.6 0.001 0.001 TA = +25°C Typ 1.5 1.5 1.5 1.5 4.49 5.49 2.0 2.0 0.8 0.8 4.4 5.4 3.86 4.86 0.1 0.1 0.36 0.36 ±0.1 TA = −40°C to +85°C Guaranteed Limits 2.0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.44 0.44 ±1.0 1.5 75 −75 40.0 µA mA mA mA µA V V Units V V Conditions VOUT = 0.1V or VCC − 0.1V VOUT = 0.1V or VCC − 0.1V IOUT = −50 µA VIN = VIL or VIH V IOH = −24 mA IOH = −24 mA (Note 5) IOUT = 50 µA VIN = VIL or VIH V IOL = 24 mA IOL = 24 mA (Note 5) VI = VCC, GND VI = VCC − 2.1V VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC or GND Note 5: All outputs loaded; thresholds on input associated with output under test. Note 6: M aximum test duration 2.0 ms, one output loaded at a time. AC Electrical Characteristics for AC VCC Symbol Parameter (V) (Note 7) fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPHL tPHL Maximum Count Frequency Propagation Delay CP to Qn (PE Input HIGH or LOW) Propagation Delay CP to Qn (PE Input HIGH or LOW) Propagation Delay CP to TC Propagation Delay CP to TC Propagation Delay CET to TC Propagation Delay CET to TC Propagation Delay MR to Qn Propagation Delay MR to TC Note 7: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V TA = +25°C CL = 50 pF Min 70 110 2.0 1.5 1.5 1.5 3.0 2.0 3.5 2.0 2.0 1.5 2.5 2.0 2.0 1.5 3.5 2.5 Typ 111 167 7.0 5.0 7.0 5.0 9 6 8.5 6.5 5.5 3.5 6.5 5 6.5 5.5 10 8.5 12 9.0 12 9.5 15 10.5 14 11 9.5 6.5 11 8.5 12 9.5 15 13 Max TA = −40°C to +85°C CL = 50 pF Min 60 95 1.5 1.0 1.5 1.5 2.5 1.5 2.5 2.0 1.5 1.0 2.0 1.5 1.5 1.5 3.0 2.5 13.5 9.5 13 10 16.5 11.5 15.5 11.5 11 7.5 12.5 9.5 13.5 10 17.5 13.5 Max MHz ns ns ns ns ns ns ns ns Units 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 5 www.fairchildsemi.com 74AC161 • 74ACT161 AC Operating Requirements for AC VCC Symbol tS tH tS tH tS tH tW tW Parameter Setup Time, HIGH or LOW Pn to CP Hold Time, HIGH or LOW Pn to CP Setup Time, HIGH or LOW PE to CP Hold Time, HIGH or LOW PE to CP Setup Time, HIGH or LOW CEP or CET to CP Hold Time, HIGH or LOW CEP or CET to CP Clock Pulse Width (Load) HIGH or LOW Clock Pulse Width (Count) HIGH or LOW tW tREC MR Pulse Width, LOW Recovery Time MR to CP Note 8: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V TA = +25°C CL = 50 pF Typ 6.0 3.5 −7.0 −4.0 6.5 4.0 −6.0 −3.5 3.0 2.0 −3.5 −2 2.0 2.0 2.0 2.0 3.0 2.5 −2 −1 13.5 8.5 −1 0 11.5 7.5 0 0.5 6.0 4.5 0 0 3.5 2.5 4.0 3.0 5.5 4.5 −0.5 0 TA = −40°C to +85°C CL = 50 pF Guaranteed Minimum 16 10.5 −0.5 0 14 8.5 0 1 7 5 0 0.5 4 3 4.5 3.5 7.5 6.0 0 0.5 ns ns ns ns ns ns ns ns Units (V) (Note 8) 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 ns ns AC Electrical Characteristics for ACT VCC Symbol fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPHL tPHL Parameter Maximum Count Frequency Propagation Delay CP to Qn (PE Input HIGH or LOW) Propagation Delay CP to Qn (PE Input HIGH or LOW) Propagation Delay CP to TC Propagation Delay CP to TC Propagation Delay CET to TC Propagation Delay CET to TC Propagation Delay MR to Qn Propagation Delay MR to TC Note 9: Voltage Range 5.0 is 5.0V ± 0.5V TA = +25°C CL = 50 pF Min 115 1.5 1.5 2.0 1.5 1.5 1.5 1.5 2.5 Typ 125 5.5 6.0 7.0 8.0 5.5 6.5 6.0 8.0 9.5 10.5 11.0 12.5 8.5 9.5 10.0 13.5 Max TA = −40°C to +85°C CL = 50 pF Min 100 1.5 1.5 1.5 1.5 1.5 1.5 1.5 2.0 10.5 11.5 12.5 13.5 10.0 10.5 11.0 14.5 Max MHz ns ns ns ns ns ns ns ns Units (V) (Note 9) 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 www.fairchildsemi.com 6 74AC161 • 74ACT161 AC Operating Requirements for ACT VCC Symbol tS tH tS tH tS tH tW tW Parameter Setup Time, HIGH or LOW Pn to CP Hold Time, HIGH or LOW Pn to CP Setup Time, HIGH or LOW PE to CP Hold Time, HIGH or LOW PE to CP Setup Time, HIGH or LOW CEP or CET to CP Hold Time, HIGH or LOW CEP or CET to CP Clock Pulse Width, (Load) HIGH or LOW Clock Pulse Width, (Count) HIGH or LOW tW tREC MR Pulse Width, LOW Recovery Time MR to CP Note 10: Voltage Range 5.0 is 5.0V ± 0.5V TA = +25°C CL = 50 pF Typ 4.0 −5.0 4.0 −5.5 2.5 −3.0 2.0 2.0 3.0 0 9.5 0 8.5 −0.5 5.5 0 3.0 3.0 3.0 0 TA = −40°C to +85°C CL = 50 pF Guaranteed Minimum 11.5 0 9.5 −0.5 6.5 0 3.5 3.5 7.5 0.5 ns ns ns ns ns ns ns ns ns ns Units (V) (Note 10) 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 Capacitance Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance Typ 4.5 45.0 Units pF pF VCC = OPEN VCC = 5.0V Conditions 7 www.fairchildsemi.com 74AC161 • 74ACT161 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A www.fairchildsemi.com 8 74AC161 • 74ACT161 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D 9 www.fairchildsemi.com 74AC161 • 74ACT161 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 www.fairchildsemi.com 10 74AC161 • 74ACT161 Synchronous Presettable Binary Counter Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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